DSP102JP

DSP101_05 BURR-BROWN | Alldatasheet

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FEATURES

G ZERO-CHIP INTERFACE TO STANDARD DSP ICs: AD, AT&T, MOTOROLA, TI G SINGLE CHANNEL: DSP101 G DUAL CHANNEL: DSP102 Two Serial Outputs or Cascade to Single 32-Bit Word G SAMPLING RATE TO 200kHz G DYNAMIC SPECIFICATIONS: Signal/(Noise + Distortion) = 85dB; Spurious-Free Dynamic Range = 94dB; THD = –91dB G SERIAL OUTPUT DATA COMPATIBLE WITH 16-, 24-, AND 32-BIT DSP IC FORMATS

DESCRIPTION

The DSP101 and DSP102 are high performance sam- pling Analog-to-Digital (A/D) converters designed for simplicity of use with modern digital signal process- ing ICs. Both are complete with all interface logic for use directly with DSP ICs, and provide full sampling and conversion at rates up to 200kHz. The DSP101 offers a single conversion channel, with 18 bits of serial data output, allowing the user to drive 16-bit, 24-bit, or 32-bit DSP ports. The DSP102 offers two complete conversion channels, with either two full 18-bit output ports, or a mode to cascade two 16-bit conversions into a 32-bit port as one word. Both the DSP101 and DSP102 are packaged in stan- dard, low-cost DIP-28 packages. Each is offered in two performance grades to match application require- ments. 18-Bit Sampling ADC 18-Bit Sampling ADC Reference Convert Command Analog Input Channel A Analog Input Channel B Channel B on DSP102 Only Control Logic Select Sync Format Channel A User Tag In Sync Bit Clock Channel A Data/ Cascaded Data Channel B Data Channel B User Tag In Cascade DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS DSP101 DSP102 Copyright © 1990, Texas Instruments Incorporated SBAS003A Printed in U.S.A. February, 2001 www.ti.com

DSP101, 1022 SBAS003A DSP101JP DSP101KP DSP102JP-1 DSP102JP DSP102KP PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS RESOLUTION 18 ✻✻ Bits ANALOG INPUT Voltage Range ±2.75V ✻✻ V Impedance 1 ✻✻ kΩ Capacitance 20 ✻✻ pF THROUGHPUT SPEED Complete Cycle Acquisition + Conversion 5 ✻✻ µs Throughput Rate 200 ✻✻ kHz AC ACCURACY (1) Signal-to-(Noise + Distortion) Ratio f IN = 1kHz 76 79 79 82 82 85 dB (2) fIN = 1kHz (–60dB) 32 ✻✻ dB fIN = 25kHz 82 ✻✻ dB Total Harmonic Distortion f IN = 1kHz –90 –86 –91 –89 –91 –89 dB Spurious-Free Dynamic Range f IN = 1kHz 89 92 92 94 92 94 dB Signal-to-Noise Ratio (SNR) f IN = 1kHz 79 82 82 85 85 88 dB DC ACCURACY Gain Error ±5 ✻✻ % Gain Error Mismatch DSP102 Channels ±2 ✻✻ % Integral Linearity ±2.75V Input Range Differential Linearity ±2.75V Input Range Integral Linearity Error ±0.7V Input Range ±0.003 ✻✻ % Differential Linearity Error ±0.7V Input Range ±0.002 ✻✻ % No Missing Codes ±0.7V Input Range 14 ✻✻ Bits Bipolar Zero Error (3) ±2 mV Bipolar Zero Mismatch (3) DSP102 Channels ±2 mV Power Supply Sensitivity –5.25V < V A– < –4.75V –60 ✻✻ dB SAMPLING DYNAMICS Aperture Delay 30 ✻✻ ns Aperture Jitter 100 ✻✻ ps, rms Transient Response 1 ✻✻ µs Overvoltage Recovery 5 ✻✻ µs DIGITAL INPUTS Logic Levels (Except OSC1) VIL IL = ±10µA 0 +0.8 ✻✻ ✻ ✻ V VIH IH = ±10µA +2.4 +5 ✻✻ ✻ ✻ V OSC1 Clock Frequency 16 MHz Data Transfer Clock (XCLK) Frequency 0.1 12 ✻✻ ✻ ✻ MHz Duty Cycle 40 50 60 ✻✻ ✻ ✻ % Conversion Clock (CLKIN) Frequency 0.5 5.33 ✻✻ ✻ ✻ MHz DIGITAL OUTPUTS Format Coding Logic Levels (Except OSC2) V OL ISINK = 4mA 0 +0.4 ✻✻ ✻ ✻ V VOH ISOURCE = 4mA +2.4 +5 ✻✻ ✻ ✻ V OSC2 Conversion Clock (CLKOUT) Drive Capability ±2mA ✻✻ mA POWER SUPPLIES Rated Voltage V Power Consumption XCLK = OSC1 = 12MHz 250 425 ✻✻ ✻ ✻ mW Supply Current XCLK = OSC1 = 12MHz ID 51 5 ✻✻ ✻ ✻ mA TEMPERATURE RANGE Specification 0 +70 ✻✻ ✻ ✻ oC Storage –65 +125 ✻✻ ✻ ✻ oC NOTES: (1) All dynamic specifications are based on 2048-point FFTs, using four-term Blackman-Harris window. (2) All specifications in dB are referred to a full-scale input, ±2.75Vp-p. (3) Adjustable to zero with external potentiometer. SPECIFICATIONS At TA = 0°C to 70°C, ±2.75V input signal, sampling frequency (fS) = 200kHz, VA+ = VD = +5V, VA– = –5V, 16MHz external clock on OSC1, CLKOUT tied to CLKIN, 8MHz data transfer clock on XCLK, data analysis band-limited to 20kHz, unless otherwise specified. Sufficient to meet AC Accuracy Specifications 74HC Compatible Serial: MSB first; 16/18-bit and Cascaded 32-bit Mode Binary Two’s Complement Can only be used to drive crystal oscillator.

3DSP101, 102 SBAS003A TYPICAL DSP102 FFT SETUP REF VINB VPOTB Burr-Brown ZPB34 DSP Processor CASC SSF OSC1 CLKOUT CLKIN CONV XCLK SYNC SOUTA DSP102 200kHz 150Ω 16MHz TTL Oscillator FFT Software ÷80 ÷2 +5V 16 8MHz 0.1µF 10µF+ 10µF+ 220pF 150Ω 220pF Brüel & Kjaer Model 1049 Digital Signal Generator

6 Pole,

±2.75V VINA ABSOLUTE MAXIMUM RATINGS oC ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Texas Instruments recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. PACKAGE/ORDERING INFORMATION SIGNAL-TO- NUMBER (NOISE + DIST.) PACKAGE SPECIFICATION OF RATIO DRAWING TEMPERATURE ORDERING TRANSPORT PRODUCT CHANNELS dB (min) PACKAGE NUMBER RANGE NUMBER MEDIA DSP101JP 1 79 DIP-28 215 –25°C to +85°C DSP101JP Rails DSP101KP 1 82 DIP-28 215 –25°C to +85°C DSP101KP Rails DSP102JP-1 2 76 DIP-28 215 –25°C to +85°C DSP102JP-1 Rails DSP102JP 2 79 DIP-28 215 –25°C to +85°C DSP102JP Rails DSP102KP 2 82 DIP-28 215 –25°C to +85°C DSP102KP Rails

DSP101, 1024 SBAS003A DSP101 PIN ASSIGNMENTS PIN # NAME DESCRIPTION 1 VPOT Trim Reference Out. 10 µF Tantalum to AGND. Voltage on this pin is approximately 2.75V. 2 VIN Analog In. 3 MSB MSB Adjust In. 4 VOS VOS Adjust In. A–– 5V Analog Power. 6V A+ +5V Analog Power. 7 DGND Digital Ground. 8 DGND Digital Ground. D +5V Digital Power. 10 CLKIN Conversion Clock In. 11 CLKOUT Conversion Clock Out. Can drive multiple DSP101/DSP102s to synchronize conversion. 12 SSF Select Synch Format In. If HIGH, SYNC will be active High. If LOW, SYNC will be active Low. See timing diagram (Figure 1). 13 OSC1 Oscillator Point 1 Input/External Clock In. If using external clock, drive with 74HC logic levels. Connect to DGND if not used. 14 OSC2 Oscillator Point 2 Output. Provides drive for crystal oscillator. Make no electrical connection if using external clock. 15 SYNC Data Synchronization Out. Active High when SSF is HIGH; active Low when SSF is LOW. 16 XCLK Data Transfer Clock In. 17 No Internal Connection. 18 TAG User Tag In. Data clocked into this pin is appended to the conversion results on SOUT. See timing diagram (Figure 1). 19 No Internal Connection. 20 SOUT Serial Data Out. MSB first, Binary Two ’s Complement format. 21 CONV Convert Command In. Falling edge puts converter into hold state, initiates conversion, and transmits previous conversion results to DSP IC with appropriate SYNC pulse. 22 DGND Digital Ground. 23 No Internal Connection. 24 No Internal Connection. 25 No Internal Connection. 26 CAP Bypass Capacitor. 10 µF Tantalum to AGND. Voltage on this pin is approximately 2.7V. 27 REF Reference Bypass. 0.1 µF Ceramic to AGND. Voltage on this pin is approximately 3.8V. 28 AGND Analog Ground. DSP101 PIN CONFIGURATION VPOT VIN MSB VOS V – V + DGND DGND V D CLKIN CLKOUT SSF OSC1 OSC2 A A AGND REF CAP DGND CONV SOUT TAG XCLK SYNC DSP101 Top View DIP

5DSP101, 102 SBAS003A DSP102 PIN ASSIGNMENTS PIN # NAME DESCRIPTION 1 VPOTA Channel A Trim Reference Out. 10 µF Tantalum to AGND. Voltage on this pin is approximately 2.75V. 2 VINA Channel A Analog In. 3 MSBA Channel A MSB Adjust In. 4 VOSA Channel A VOS Adjust In. A–– 5V Analog Power. 6V A+ +5V Analog Power. 7 DGND Digital Ground. 8 DGND Digital Ground. D +5V Digital Power. 10 CLKIN Conversion Clock In. 11 CLKOUT Conversion Clock Out. Can drive multiple DSP101/ DSP102s to synchronize conversion. 12 SSF Select Synch Format In. If HIGH, SYNC will be active High. If LOW, SYNC will be active Low. See timing diagram (Figure 1). 13 OSC1 Oscillator Point 1 Input / External Clock In. If using external clock, drive with 74HC logic levels. Connect to DGND if not used. 14 OSC2 Oscillator Point 2 Output. Provides drive for crystal oscillator. Make no electrical connection if using external clock. 15 SYNC Data Synchronization Out. Active High when SSF is HIGH; active Low when SSF is LOW. 16 XCLK Data Transfer Clock In. 17 SOUTB Channel B Serial Data Out. MSB first, Binary Two ’s Complement format. 18 TAGA Channel A User Tag In. Data clocked into this pin is appended to the conversion results of SOUTA. See timing diagram (Figure 1). 19 TAGB Channel B User Tag In. Data clocked into this pin is appended to the conversion results of SOUTB. See timing diagram (Figure 1). 20 SOUTA Channel A Serial Data Out. MSB first, Binary Two ’s Complement format. If CASC is HIGH, 32 bits of data output, with first 16 bits being Channel A data. 21 CONV Convert Command In. Falling edge puts converter into hold state, initiates conversion, and transmits previous conversion results to DSP IC with appropriate SYNC pulse. 22 CASC Select Cascade Mode In. If HIGH, DSP102 transmits a 32-bit word on SOUTA, with the first 16 bits being data on Channel A. If LOW, DSP102 transmits data for both channels simultaneously. 23 VOSB Channel B VOS Adjust In. 24 MSBB Channel B MSB Adjust In. 25 VINB Channel B Analog In. 26 VPOTB Channel B Trim Reference Out. 10 µF Tantalum to AGND. Voltage on this pin is approximately 2.75V. 27 REF Reference Bypass. 0.1 µF Ceramic to AGND. Voltage on this pin is approximately 3.8V. 28 AGND Analog Ground. DSP102 PIN CONFIGURATION Top View DIP VPOTA VINA MSBA VOSA V VA+ DGND DGND V D CLKIN CLKOUT SSF OSC1 OSC2 AGND REF VPOTB VINB MSBB VOSB CASC CONV SOUTA TAGB TAGA SOUTB XCLK SYNC DSP102

DSP101, 1026 SBAS003A DSP102 CHANNEL SEPARATION ON CHANNEL B WITH ±2.75V, 1kHz INPUT ON CHANNEL A Frequency (kHz) Magnitude (dB) –20 –40 –60 –80 –100 –120 25 50 75 100 FREQUENCY SPECTRUM of ±2.75V, 451kHz INPUT (Using Four-Term Blackman-Harris Window) Frequency (kHz) Magnitude (dB) –20 –40 –60 –80 –100 –120 25 50 75 100 Undersampling SINAD means Signal-to-(Noise + Distortion) Ratio. THD means Total Harmonic Distortion thru 8th harmonic. SNR means Signal-to-Noise Ratio excluding harmonics SFDR means Spurious Free Dynamic Range, including thru the 8th. harmonics. TYPICAL PERFORMANCE CURVES At TA = +25°C, VA+ = VD + = +5V, VA– = VD – = –5V, Sampling Frequency fS = 200kHz; External Clock Input at OSC1 = 80fS = 16MHz, XCLK = 40fS = 8MHz; Using 2048 Point FFT; Data analysis limited to 0 to 20kHz band; Unless otherwise specified. –55 –40 –25 0 25 70 85 125 Ambient Temperature (°C) DYNAMIC PERFORMANCE vs TEMPERATURE SINAD, SNR and SFDR (dB) THD (dB) –80 –85 –90 –95 –100100 fIN = 1kHz, ±2.75V SINAD THD SNR SFDR FREQUENCY SPECTRUM of ±2.75V, 1kHz INPUT (Average of 12 FFTs, No Window Used) Frequency (kHz) 0 25 50 75 100 Magnitude (dB) –30 –60 –90 –120 FREQUENCY SPECTRUM of ±2.75V, 20kHz INPUT (Using Four-Term Blackman-Harris Window) Frequency (kHz) Magnitude (dB) –20 –40 –60 –80 –100 –120 25 50 75 100 INTERMODULATION DISTORTION WITH 1kHz AND 3kHz INPUTS (Using Four-Term Blackman-Harris Window) Frequency (kHz) Magnitude (dB) –20 –40 –60 –80 –100 –120 25 50 75 100

7DSP101, 102 SBAS003A –55 –40 –25 0 25 70 85 125 Ambient Temperature (°C) DYNAMIC PERFORMANCE vs TEMPERATURE (Data Analysis Over Full 0 to 100kHz Band) SINAD, SNR and SFDR (dB) THD (dB) –75 –80 –85 –90 –95 –100100 fIN = 1kHz, ±2.75V SINAD THD SFDR SNR TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VA+ = VD + = +5V, VA– = VD – = –5V, Sampling Frequency fS = 200kHz; External Clock Input at OSC1 = 80fS = 16MHz, XCLK = 40fS = 8MHz; Using 2048 Point FFT; Data analysis limited to 0 to 20kHz band; Unless otherwise specified. 000E Output Code and Equivalent Voltage (Binned at 16-bit level) HISTOGRAM OF 5k CONVERSION RESULTS ON DSP102 (Both Inputs Grounded) Number of Conversions Yielding This Code 2500 2000 1500 1000 500 Channel A Channel B 1.17mV 0000 FFF7FFF1 –1.26mV Code Voltage –70 –75 –80 –85 –90 –95 100 –100 300 60 90 120 150 180 Conversion Rate (kHz) SINAD, SNR and SFDR (dB) THD (dB) DYNAMIC PERFORMANCE vs CONVERSION RATE (Data Analysis over Full 0 to fS/2 Band, OSC1 = 12.288MHz, XCLK = 3.072MHz) SINAD SNR THD SFDR fIN = 1kHz, ±2.75V (0dB) –60 –70 –80 –90 1 10 100 1000 Input Frequency (kHz) Total Harmonic Distortion (dB) TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY –100 ±2.75V Input (0dB) –55 –40 –25 0 25 70 85 125 Ambient Temperature (°C) DYNAMIC PERFORMANCE vs TEMPERATURE (fS = 180kHz Asychronous to 12.288MHz Crystal Between OSC1 and OSC2) SINAD, SNR and SFDR (dB) THD (dB) –70 –75 –80 –85 –90 –95 –100100 Ambient Temperature (°C) fIN = 1kHz, ±2.75V THD SFDR SNR SINAD 100 0.1 1 10 100 Input Frequency (kHz) SINAD (dB) SINAD vs INPUT FREQUENCY (Data Analysis over Full 0 to 100kHz Band) ±2.75V Input (0dB) ±0.275V Input (–20dB) ±2.75mV Input (–60dB)

FIGURE 1. DSP101 and DSP102 Timing.

FIGURE 4. Output Structure of DSP102. although they will still be present on the serial data line. for details of the Cascade mode. output data, Sync pulse, and Tag inputs to the bit clock. design can easily have more effect. LOW, respectively, is input at SSF (pin 12). operation of the internal data shift registers on the DSP102. the figure, showing the SOUTA path. NOTE: (1) Signal internal to DSP101/DSP102 which also generates SYNC pulse.

output channel B conversion data and tag data as usual. ing applications with wide dynamic range requirements. transition points at +1.375V and –1.375V levels. including clocks, reference noise, etc. tion) Ratio undersampling 500kHz input signals. quality become very important. FIGURE 8. DSP101 or DSP102 Optional MSB and Offset Adjust. bypassed with the 10µF Tantalum capacitor.

poor because longer lead lengths create inductance. the same potential as the system analog ground. is taken to analyze and design for current flows. FIGURE 9. Driving a 16-bit Parallel Port from the DSP101.

9 CLK

cations, external trims are not required. ground with 0.01µF capacitors, as close as possible to the A/D. can be adjusted until there is no DC offset of the signal. with 0.01µF capacitors, as close as possible to the A/D. FIGURE 10. A Complete Eight-Channel Analog Input System Using the DSP202 and the HI-508A. with unused inputs tied to ground.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DSP101JP OBSOLETE PDIP NTD 28 TBD Call TI Call TI DSP101KP OBSOLETE PDIP NTD 28 TBD Call TI Call TI DSP102JP OBSOLETE PDIP NTD 28 TBD Call TI Call TI DSP102JP-1 OBSOLETE PDIP NTD 28 TBD Call TI Call TI DSP102KP OBSOLETE PDIP NTD 28 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 Addendum-Page 1

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