DSM2180F3

DSM2180F3_08 STMICROELECTRONICS | Alldatasheet

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Technical content

This is information on a product still in production but not recommended for new designs. Memory Overlay and 16-bit I/O Mem space. trol panel, displays, LCD, UART devices, etc. Figure 1. Packages

Obsolete Product(s) - Obsolete Product(s) DSM2180F3 TABLE OF CONTENTS

Obsolete Product(s) - Obsolete Product(s) DSM2180F3

memory (no DMA setup overhead). Figure 2. PLCC Connections PC or note-book parallel port. Figure 3. PQFP Connections mable by JTAG ISP, just like the Flash memory. PLD include chip selects fo r external devices (i.e. available at no charge from www.psdst.com.

39 AD15

38 AD14

37 AD13

36 AD12

35 AD11

34 AD10

33 AD9

32 AD8

30 AD7

29 AD6

28 AD5

27 AD4

Figure 4. System Block Diagram, Two-Chip Solution ideal for battery powered products.

16 MACROCELL PLD

8 I/O

8 DATA

13 FLAGS / 4 INTR

data port even while the security bit is set. Table 1. DSM2180F3 DSP Memory System Devices Table 2. Compatible Analog Devices DSPs

Obsolete Product(s) - Obsolete Product(s) DSM2180F3 ARCHITECTURAL OVERVIEW Major functional blocks are shown in Figure 5. DSP Address/Data/Control Interface These DSP signals attach directly to the DSM in- puts for a glueless connection. An 8-bit data con- nection is formed and all 22 DSP address lines can be decoded while the DSP operates in full memory mode. DSP memory strobes; BMS, DMS, and IOMS are used for BDMA, data, & I/O access respectively (no program memory access, PMS). Flash Memory The 1 Mbit (128K x 8) Flash memory is divided into eight equally-sized 16K byte sectors that are indi- vidually selectable through the Decode PLD. Each Flash memory sector can be located at any ad- dress as defined by the user with PSDsoft Ex- press. The flexibility of the Decode PLD and Page Register logic allow the DSP to access Flash memory as Byte DMA (BDMA) or as external data overlay memory across several memory pages. BDMA transfers are good for initial bootloading and for loading internal overlay memory at run- time, but BDMA is not efficient writing to Flash memory because Flash memory is unlocked, writ- ten, and status is checked one byte at a time, re- quiring an initialization of the BDMA channel for each and every byte transfer. The DSM device al- lows the DSP to alternatively access Flash memo- ry as data overlay memory (using DMS instead of BMS). Writing Flash memory this way is faster and requires simpler code. Note: During a DSP data access using the DMS strobe, only the upper byte of a 16-bit DSP data word is used. DSM Flash memory sector size of 16K bytes matches the DSP external Data Memory Overlay window size of 16K locations (two 8K windows when DMOVLAY register is used, see Analog De- vices ADSP-218X data sheets). This alignment provides convenient data management. Also, each 16K byte sector can be loaded with contents from different firmware or data files specified in PSDsoft Express TM. Miscellaneous: The DSP can erase Flash memory by individual sectors or the entire Flash memory array may be erased at one time. The Flash mem- ory automatically goes to standby between DSP read or write accesses to conserve power. Maxi- mum access times include sector decoding time. Maximum erase cycles is 100K and data retention is 15 years minimum. Flash memory, as well as the entire DSM device may be programmed with the JTAG ISP interface with no DSP involvement.

Figure 5. Block Diagram ting is controlled at runtime by DSP software. Port Pins, CPLD logic feedback. flop within in each OMC to realize sequential logic. ed to pins on Port B or PortC.

16 INPUT

16 OUTPUT MICRO<>CELLS

3 OPTIONAL OUTPUTS TO PORT D

8 SEGMENTS, 16 KB

128 KBytes TOTAL

Obsolete Product(s) - Obsolete Product(s) DSM2180F3 without clocking or latching. The DSP may read the IMCs at any time. Runtime Control Registers A block of 256 bytes is decoded inside the DSM device as DSM control and status registers. 27 registers are used in the block of 256 locations to control the output state of I/O pins, to read I/O pins, to control power management, to read/write macrocells, and other functions at runtime. See Table 4 for description. The base address of these 256 locations is referred to in this data sheet as csiop (Chip Select I/O Port). Individual registers within this block are accessed with an offset from the base address. The DSP accesses csiop regis- ters using I/O memory with the IOMS strobe. csiop registers are accessed as bytes, so only the lower half of a DSP I/O word is used during access. Memory Page Register This 8-bit register can be loaded and read by the DSP at runtime as one of the csiop registers. Its outputs feed directly into the PLDs. The page reg- ister is a powerful feature that allows the DSP to access all 128K Bytes of DSM Flash memory in 16K byte pages. This size matches the 16K loca- tion data overlay window the ADSP-218X family. Page register outputs may also be used as CPLD inputs for general use. I/O Ports The DSM has 19 individually configurable I/O pins distributed over the three ports (Ports B, C, and D). Each I/O pin can be individually configured for dif- ferent functions such as standard MCU I/O ports or PLD I/O on a pin by pin basis. (MCU I/O means that for each pin, its output state can be controlled or its input value can be read by the DSP at run- time using the csiop registers like an MCU would do.) Port C hosts the JTAG ISP signals. Since JTAG- ISP does not occur frequently during the life of a product, those Port C pi ns are under-utilized. In applications that need every I/O pin, JTAG signals can be multiplexed with general I/O signals to use them for I/O when not performing ISP. See section titled “Programming In-Circuit using JTAG ISP” on page 41 for muxing JTAG pins on Port C, and Ap- plication Note AN1153. The static configuration of all Port pins is defined with the PSDsoft Express TM software develop- ment tool. The dynamic action of the Ports pins is controlled by DSP runtime software. JTAG ISP Port In-System Programming (ISP) can be performed through the JTAG signals on Port C. This serial in- terface allows programming of the entire DSM device or subsections (that is, only Flash memory but not the PLDs) without the participation of the DSP. A blank DSM device soldered to a circuit board can be completely programmed in 10 to 20 seconds. The basic JTAG signals; TMS, TCK, TDI, and TDO form the IEEE-1149.1 interface. The DSM device does not implement the IEEE- 1149.1 Boundary Scan functions. The DSM uses the JTAG interface for ISP only. However, the DSM device can reside in a standard JTAG chain with other JTAG devices an d it will remain in BY- PASS mode while other devices perform Bound- ary Scan. ISP programming time can be reduced as much as 30% by using two more signals on Port C, TSTAT and TERR in addition to TMS, TCK, TDI and TDO. The FlashLINK TM JTAG programming cable is available from STMicroelectronics for $59USD and PSDsoft Express software is available at no charge from www.psdst.com. That is all that is needed to program a DSM device using the paral- lel port on any PC or note-book. See section titled “Programming In-Circuit using JTAG ISP” on page 41. Power Management The DSM has bits in csiop control registers that are configured at run-time by the DSP to reduce power consumption of the CPLD. The Turbo bit in the PMMR0 register can be set to logic 1 and the CPLD will go to Non-Turb o mode, meaning it will latch its outputs and go to sleep until the next tran- sition on its inputs. There is a slight penalty in PLD performance (longer propagation delay), but sig- nificant power savings are realized. Additionally, bits in two csiop registers can be set by the DSP to selectively block signals from enter- ing the CPLD which reduces power consumption. See section titled “Power Management” on page 39. Security and NVM Sector Protection A programmable security bit in the DSM protects its contents from unauthorized viewing and copy- ing. When set, the security bit will block access of programming devices (JTAG or others) to the DSM Flash memory and PLD configuration. The only way to defeat the security bit is to erase the entire DSM device, after which the device is blank and may be used again. Additionally, the contents of each individual Flash memory sector can be write protected (sector pro- tection) by configuration with PSDsoft Express TM. This is typically used to protect DSP boot code from being corrupted by inadvertent writes to Flash memory from the DSP. Pin Assignments Pin assignment are shown for the 52-pin PLCC package in Figure 2, and the 52-pin PQFP pack- age in Figure 3.

Table 3. Pin Description ADIO0-15 In Sixteen addres s inputs from the DSP . CNTL1 In Active low read strobe input (RD ) from the DSP . CNTL2 In Active low Byte Memory Select (BMS ) signal from the DSP . DSM configuration registers. Must be logic Low at Power-up. PA0-7 I/O Eight data bus signals c onnected to DSP pins D8 - D15.

1. MCU I/O – DSP may write or read pins di rectly at runtime with csiop registers.
2. CPLD Output Macrocell (McellAB0-7 or McellBC0-7) outputs.
3. Inputs to the PLDs (Input Macrocells).

run-time as either standard CMOS or Open Drain Outputs.

1. MCU I/O – DSP may write or read pins directly at runtime with csiop registers.
2. CPLD Output Macrocell (McellBC0-7) output.
3. Input to the PLDs (Input Macrocells).
4. Pins PC0, PC1, PC5, and PC6 can optionally form the JTAG IEEE-1149.1 ISP serial

interface as signals TMS, TCK, TDI, and TDO respectively.

1. Pins PC3 and PC4 can optionally form the enhanced JTAG signals TSTAT and TERR

standard four JTAG signals: TDI, TDO, TMS, TCK.

1. Pin PC3 can optionally be configured as the Ready/Busy output to indicate Flash memory

functions as DSP address A16 in DSP Full Memory Mode. See Figure 6. functions as DSP address A17 in DSP Full Memory Mode. See Figure 6. as either standard CMOS or Open Drain Outputs. Note 4: The JTAG ISP pins may be multiplexed with other I/O functions.

1. MCU I/O – DSP may write or read pins di rectly at runtime with csiop registers.
2. Input to the PLDs (no associated Input Macrocells, routes directly into PLDs).
3. CPLD output (External Chip Select). Does not consume Output Macrocells.
4. Pin PD1 can optionally be configured as CLKIN, a common clock input to PLD.
5. Pin PD2 can optionally be configured as CSI, an active low Chip Select Input to select Flash

connect CSI to ADSP-218X PWDACK output signal. active low I/O Memory Select strobe. See Figure 6. low Data Memory Select strobe. See Figure 6. Power Down mode is used. See Figure 6.

Obsolete Product(s) - Obsolete Product(s) DSM2180F3 TYPICAL CONNECTIONS Figure 6 shows a typical connection scheme. Many connection possibilities exist since most DSM pins are multipurpose. The scheme illustrat- ed is ideal for a design that needs fast JTAG ISP, Eight additional general I/O with PLD capability, access to Flash memory as Byte DMA or as Data Overlay memory, and the DSP uses Power Down mode. If your design needs more I/O, or Byte DMA access to Flash memory is all that is needed (no Data Overlay), or lowest power consumption is not an issue, then consider the following options. Port C JTAG: Figure 6 shows all six JTAG sig- nals in use full time (not multiplexed with I/0). Us- ing six-pin JTAG can reduce ISP time by as much as 30% compared to four-pin JTAG. Alternatively, four-pin JTAG (TMS, TCK, TDI, TDO) can be used if more general I/O pins are needed and the few extra seconds of programming time is not crucial, freeing up pins PC3 and PC4. Other JTAG options include mutiplexing JTAG pins with general I/O (see “Programming In-Circuit using JTAG ISP” on page 41 and Application Note AN1153) or not us- ing JTAG at all. If no JTAG is used, the DSM de- vice has to be programmed on a conventional programmer before it is installed on the circuit board. Using no JTAG makes more I/O available. Pin PD1. If Flash memory will be accessed only using Byte DMA mode in your design, and no ex- ternal Data Overlay memory accesses are used, then pin PD1 can be used for other purposes (MCUI/O, common CPLD clock input, external chip select, or PLD input) Pin PD2. If the DSP will not use Power Down mode, then PD2 can be used for other purposes (MCUI/O, external chip select, PLD input) Pins PC2 and PC7. In Figure 6, these two pins are used as dedicated address inputs connected to DSP address outputs. This will route DSP ad- dress signals A16 and A17 directly into the DPLD. Be aware that any free pin on Port B, Port C, or Port D may be used for DSP address inputs, it does not have to be pins PC2 and PC7. Pin PB0. This pin is shown as a chip select for an external peripheral device such as a 16450 or 16550 UART. Equivalently, any free pin on Ports B, C, or D may be used for this.

Figure 6. Typical Connections

Obsolete Product(s) - Obsolete Product(s) DSM2180F3 MEMORY MAP Figure 7 shows a typical system memory map. The nomenclature fs0..fs7 are individual 16K Byte Flash memory segment designators. csiop desig- nates the DSM control register block. The DSP runs in Full Memory Mode. Memory contents of the DSM device may lie in one or more of three dif- ferent DSP address spaces; I/O space, Byte DMA space, and/or External Data Overlay Memory space. Since the DSM device is a byte-wide mem- ory, it typically is not used in DSP Program Mem- ory space ( PMS active). The designer may easily specify memory mapping in a point-and-click software environment using PSDsoft Express TM. Since the memory mapping is implemented with the DPLD and the Page Regis- ter, many possibilities exist. Figure 7 shows a typ- ical memory map with the following attributes: I/O Address Space. The 256 byte locations for DSM control registers ( csiop) reside in DSP I/O address space, selected by the DSP IOMS signal. Since DSP I/O accesses are by 16 bits, not 8 bits, the upper byte of a 16-bit DSP I/O access must be ignored. Byte DMA Address Space. The DSP may boot- load or fetch overlay bytes from 128K Bytes of Flash memory using the DSP BDMA channel. The DSP may also write to Flash memory using the Byte DMA channel. DSM Flash memory is ac- cessed in 128K continuous byte address locations through the BDMA channel and is selected when- ever the DSP BMS signal is active. Flash memory in the DSM device must be un- locked and written by the DSP one byte at a time, checking status after ea ch write (typical Flash memory programming algorithm). A DMA channel is not optimum for this scenario since the channel must be initialized on each byte access. That is why the 128K Bytes of Flash memory also lie in DSP Data Overlay Memory space as described next. Data Overlay Memory Address Space. All 128K Bytes of Flash memory also reside in DSP External Data Overlay Memory space, selected by DMS, allowing more efficient byte writes to Flash memory. The DSP uses its external data overlay window of 8K locations to access external memory as data. The DSP doubles the size of this window to 16K locations by manipulating its A13 address line using its DMOVLAY register (See ADSP-218X data sheets for details). Since all 128K Bytes of Flash memory must be accessed through a win- dow of only 16K locations, the DSP uses the Page Register inside the DSM device to page through 8 pages of 16K Bytes as shown in Figure 7. Since DSP Data accesses are by 16 bits, not 8 bits, the upper byte of a 16-bit DSP Data access must be ignored.

Figure 7. Typical System Memory Map

16 KBytes

256 CONTROL REGS

8 UART REGS00200

Figure 8. HDL Statements Generated from PSDsoft Express to Implement Memory Map nal chip select signals (UART, etc.).

Figure 9. PSDsoft ExpressTM Memory Mapping

Table 4. CSIOP Registers and their Offsets (in hex) MCU I/O mode. Configures Port pin as input or output. Write to set direction of Port pins. Logic 1 = out, Logic 0 = in. Read to check status. on other pins. Read to check status. Input Macrocells 0B 18 Read to obtain state of IMCs. No writes. each I/O Port driver. No writes. Output Macrocells AB 20 Read to get logic state of output of OMC bank AB. Write to load registers of OMC bank AB. Output Macrocells BC 21 Read to get logic state of output of OMC bank BC. Write to load registers of OMC bank BC. corresponding OMC. A logic 0 will pass OMC value. corresponding OMC. A logic 0 will pass OMC value. Security Bit C2 Read to determine if DSM devices Security Bit is active. Logic 1 = device secured. No writes. PMMR0 B0 Power Management Register 0. Write and read. PMMR2 B4 Power Management Register 2. Write and read. Page E0 Memory Page Register. Write and read.

Obsolete Product(s) - Obsolete Product(s) DSM2180F3 DETAILED OPERATION Figure 5 shows major functional areas of the de- vice: ■ Flash Memory ■ PLDs (DPLD, CPLD, Page Register) ■ DSP Bus Interface (Address, Data, Control) ■ I/O Ports ■ Runtime Control Registers ■ JTAG ISP Interface The following describes these functions in more detail. Flash Memory The Flash memory array is divided evenly into eight equal 16K byte sectors. Each sector is se- lected by the DPLD can be separately protected from program and erase cycles. This configuration is specified by using PSDsoft Express TM. Memory Sector Select Signals. The DPLD gen- erates the Select signals for all the internal memo- ry blocks (see Figure 14). Each of the eight sectors of the Flash memory has a Select signal ( FS0- FS7) which contains up to three product terms. Having three product terms for each Select signal allows a given sector to be mapped into multiple areas of system memory. Ready/Busy (PC3). This signal can be used to output the Ready/ Busy status of the device. The output on Ready/ Busy (PC3) is a 0 (Busy) when Flash memory is being written, or when Flash memory is being erased. The output is a 1 (Ready) when no Write or Erase cycle is in progress. This signal may be polled by the DSP or used as a DSP interrupt to indicate when an erase or program cy- cle is complete. Memory Operation. The Flash memory is ac- cessed through the DSP Address, Data, and Con- trol Bus Interface. The DSP can access Flash memory as BDMA mode or as External Data Memory Overlay. But from the DSM perspective, it sees either type of access as a series of byte op- erations (reads and writes). If the DSP accesses the DSM in BDMA mode, then the DSP BDMA channel must be initialized and run for each byte (or block of bytes) read from Flash memory or it must initialize the DMA channel for each byte writ- ten to Flash memory. Alternatively, if the DSP ac- cesses the DSM in External Data Memory Overlay mode, then the DSP must only ensure the PSD Page Register and the DSP DMOVLAY register contains the correct value, then it performs a nor- mal data read or data write operation without the burden of initializing the BDMA channel for each operation (upper byte of 16-bit word is ignored). DSPs and MCUs cannot write to Flash memory as it would an SRAM device. Flash memory must first be “unlocked” with a special sequence of byte write operations to invoke an internal algorithm, then a single data byte is written to the Flash mem- ory array, then programming status is checked by a byte read operation or by checking the Ready/ Busy pin (PC3). Table 5 lists all of the special in- struction sequences to program (write) data to the Flash memory array, erase the array, and check for different types of status from the array. These instruction sequences are different combinations of individual byte write and byte read operations. Once the Flash memory array is programmed (written) and then it is in “Read Array” mode, the DSP will read from Flash me mory just as if would from any 8-bit ROM or SRAM device.

Table 5. Instruction Sequences1,2,3,4

1. A desired internal Flash memory sector select signal (FS0 - FS7) must be active for each write or read cycle. Only one of FS0 - FS7

press. FS0 - FS7 are active high logic internally.

1. DSP addresses A17 through A12 are Don’t Care during the instruction sequence decoding. Only address bits A11-A0 are used

ing the instruction sequences determines the complete address.

1. For write operations, addresses are latched on the falling edge of Write Strobe (WR
2. No Unlock or Instruction cycles are required when the device is in the Read Array mode. Operation is like reading a ROM devic e.
3. The Reset Flash instruction is required to return to the normal Read Array mode if the Error Flag (DQ5) bit goes High, or after read-

ing the Flash Identifier or after reading the Sector Protection Status.

1. The DSP cannot invoke this instruction sequence while executing code from the same Flash memory as that for which the instruc-

tifier or Sector Protection Status.

1. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
2. Directing this command to any individual active Flash memory segment (FS0 - FS7) will invoke the bulk erase of all eight Flas h
3. DSP writes command sequece to initial segment to be erased, then writes the byte 30h to additional sectors to be erased. The byte

address within a desired sector). No more than 80uS can elapse between subsequent additional sector erase commands.

1. The system may perform Read and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protect Status,

when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction sequence is valid only during a Sector Erase cycle.

1. The Resume Sector Erase instruction sequence is valid only during the Suspend Sector Erase mode.

1. For efficient decoding of the instruction se-

selected internally (active, which is logic 1). scribe these read instruction sequences. part of an instruction sequence. or 00h if the sector is not protected. Table 6. Status Bit Definition Note: 1. X = Not guaranteed value, can be read either 1 or 0.

1. DQ7-DQ0 represent the Data Bus bits, D7-D0.

bits can be read as many times as needed.

Obsolete Product(s) - Obsolete Product(s) DSM2180F3 section entitled “Programming Flash Memory”, on page 21, for details. Data Polling Flag (DQ7). When erasing or pro- gramming in Flash memory, the Data Polling Flag (DQ7) bit outputs the complement of the bit being entered for programming/writing on the Data Poll- ing Flag (DQ7) bit. Once the Program instruction sequence or the write operation is completed, the true logic value is read on the Data Polling Flag (DQ7) bit (in a read operation). Flash memory instruction features: ■ Data Polling is effective after the fourth Write pulse (for a Program instruction sequence) or after the sixth Write pulse (for an Erase instruction sequence). It must be performed at the address being programmed or at an address within the Flash memory sector being erased. ■ During an Erase cycle, the Data Polling Flag (DQ7) bit outputs a 0. After completion of the cycle, the Data Polling Flag (DQ7) bit outputs the last bit programmed (it is a 1 after erasing). ■ If the byte to be programmed is in a protected Flash memory sector, the instruction sequence is ignored. ■ If all the Flash memory sectors to be erased are protected, the Data Polling Flag (DQ7) bit is reset to 0 for about 100 µs, and then returns to the previous addressed byte. No erasure is performed. Toggle Flag (DQ6). The device offers another way for determining when the Flash memory Pro- gram cycle is completed. During the internal write operation and when the Sector Select FS0-FS7 is true, the Toggle Flag (DQ6) bit toggles from 0 to 1 and 1 to 0 on subsequent attempts to read any byte of the memory. When the internal cycle is complete, the toggling stops and the data read on the Data Bus D0-7 is the addressed memory byte. The device is now accessible for a new read or write operation. The cycle is finished when two successive reads yield the same output data. Flash memory specific fea- tures: ■ The Toggle Flag (DQ6) bit is effective after the fourth write operation (for a Program instruction sequence) or after the sixth write operation (for an Erase instruction sequence). ■ If the byte to be programmed belongs to a protected Flash memory sector, the instruction sequence is ignored. ■ If all the Flash memory sectors selected for erasure are protected, the Toggle Flag (DQ6) bit toggles to 0 for about 100 µs and then returns to the previous addressed byte. Error Flag (DQ5). During a normal Program or Erase cycle, the Error Flag (DQ5) bit is to 0. This bit is set to 1 when there is a failure during Flash memory Byte Program, Sector Erase, or Bulk Erase cycle. In the case of Flash memory programming, the Er- ror Flag (DQ5) bit indicates the attempt to program a Flash memory bit from the programmed state, 0, to the erased state, 1, which is not valid. The Error Flag (DQ5) bit may also indicate a Time-out condi- tion while attempting to program a byte. In case of an error in a Flash memory Sector Erase or Byte Program cycle, the Flash memory sector in which the error occurred or to which the pro- grammed byte belongs must no longer be used. Other Flash memory sect ors may still be used. The Error Flag (DQ5) bit is reset after a Reset Flash instruction sequence. Erase Time-out Flag (DQ3). The Erase Time- out Flag (DQ3) bit reflects the time-out period al- lowed between two consecutive Sector Erase in- struction sequence bytes. The Erase Time-out Flag (DQ3) bit is reset to 0 after a Sector Erase cy- cle for a time period of 100 µs + 20% unless an ad- ditional Sector Erase instruction sequence is decoded. After this time period, or when the addi- tional Sector Erase instruction sequence is decod- ed, the Erase Time-out Flag (DQ3) bit is set to 1. Programming Flash Memory When a byte of Flash memory is programmed, in- dividual bits are programmed to logic 0. You can- not program a bit in Flash memory to a logic 1 once it has been programmed to a logic 0. A bit must be erased to logic 1, and programmed to log- ic 0. That means Flash memory must be erased prior to being programmed. A byte of Flash mem- ory is erased to all 1s (FFh). The DSP may erase the entire Flash memory array all at once or indi- vidual sector-by-sector, but not byte-by-byte. However, the DSP may program Flash memory byte-by-byte. The Flash memory requires the DSP to send an in- struction sequence to program a byte or to erase sectors (see Table 5). Once the DSP issues a Flash memory Program or Erase instruction sequence , it must check for the status bits for completion. The embedded algo- rithms that are invoked inside the device provide several ways give status to the DSP. Status may be checked using any of three methods: Data Poll- ing, Data Toggle, or Ready/Busy (pin PC3). Data Polling. Polling on the Data Polling Flag (DQ7) bit is a method of checking whether a Pro-

ed. Figure 10 shows the Data Polling algorithm. byte that was intended to be written. Polling Flag (DQ7) bit and the Error Flag (DQ5) bit. Figure 10. Data Polling Flowchart ure 11 shows the Data Toggle algorithm. the Error Flag (DQ5) bit (see Figure 11).

Figure 11. Data Toggle Flowchart byte that was intended to be written. Flag (DQ6) bit and the Error Flag (DQ5) bit. and the entire array (all segments) will be erased. mand was sent to just one Flash memory sector. this automatically before erasing (byte=FFh). gramming Flash Memory”, on page 21.

addressed to other desired segments (FS0 - FS7). terminates the time out period. automatically set to Read mode. that was being erased outputs invalid data. was being erased is invalid. Flash Memory Sector Protect. lected for each sector using PSDsoft Express. operation results in a read of the protected data. ters (in the csiop block) as defined in Table 7. Table 7. Sector Protection/Security Bit Definition – Flash Protection Register Sec<i>_Prot 1 = Flash memory sector <i> is write protected. Sec<i>_Prot 0 = Flash memory sector <i> is not write protected. Table 8. Security Bit Definition 1 = Security Bit in device has been set.

register in the csiop block as defined in Table 8. Flash memory Program or Erase cycle. Flash memory back into normal Read Array mode. Array mode within a few milliseconds. cleared to logic 0 at reset. Figure 12. Page Register The PLDs bring programmable logic to the device. vice and available upon Power-up. Table 9. DPLD and CPLD Inputs for recommended connections.

1. Additional DSP control signals may enter the DMS device

ponents, such as memory, registers, and I/O ports. (ECS0-ECS2) signals on Port D. The AND Array is used to form product terms. PLDs. Input signals are shown in Table 9. Figure 13. PLD Diagram

16 Input Macrocell

16 Output

3 PORT D Inputs

pins, each with one product term. Figure 14. DPLD Logic Array

8 Flash Memory

the Input and Output Macrocells (IMC and OMC). standard PLD macro cell architectures. Figure 15. Macrocell and I/O Port pins and are named as McellBC0-McellBC7.

(PD1). The preset and clear are active High inputs. Each clear input can use up to two product terms. OMC can be routed to one Port pin only, not both. Figure 16. OMC Allocator Table 10. Output Macrocell Port and Data Bit Assignments terms and may borrow up to six more.

not add any propagation delay to the logic. location and product term expansion. MCELLAB0-7 and MCELLBC0-7 (see Table 4). puts to the flip-flop can be overridden by the DSP. Figure 17. CPLD Output Macrocell

Figure 18. Input Macrocell

1. The IMCs are individually configurable, and

product term and 7-4 by another.

connected to the Port Data Buffer (PDB). “Input Macrocell”, on page 31. The I/O Ports have several modes of operation. Note AN1171 for more detail. are described in the following sections. Table 11. Port Operating Modes Note: 1. Can be multiplexed with other I/O functions. the Data In buffer. See Figure 19. Port B come from the OMC group MCELLAB0-7. in PSDsoft Express by specifying PLD equations. each bit in the register controls its respective pin.

(PCR), are shown in Table 12. Default is logic 0. Table 12. Port Configuration Registers (PCR) Note: 1. See Table 16 for Drive Register bit definition. for Port B corresponds to Port B pin PB0. mode for all port pins is input. Table 13. Port Pin Direction Control, Output Table 14. Port Pin Direction Control, Output Table 15. Port Direction Assignment Example three least significant bits active. pin configured as Open Drain is Vcc + 0.7V.

1. The default pin drive is CMOS.

ister is set to 1. The default rate is standard slew.

1 B,C,D Write/Read

0 Input

1 Output

Table 16. Drive Register Pin Assignment Note: 1. NA = Not Applicable. Figure 20. Port B Structure McellBC0 can be connected to Port B or Port C. ■ CPLD Input – Via the Input Macrocells (IMC). be configured to Open Drain Mode.

Figure 21. Port C Structure can be connected to Port B or Port C.

Figure 22. Port D Structure enable product term or the Direction Register.

Figure 23. Port D External Chip Select Signals

are changing—it happens automatically. no PLD inputs are changing (zero DC current). 18 define the PMMR registers. initial transition from deselected to selected. Table 17. Power Management Mode Registers PMMR01 Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset ) pulses do not clear the registers. Bit 0 X 0 Not used, and should be set to zero. Bit 1 X 0 Not used, and should be set to zero. Bit 2 X 0 Not used, and should be set to zero. 1 = off PLD Turbo mode is off, saving power. CLKIN (PD1) Powers-up the PLD when Turbo bit is 0. 1 = off CLKIN (PD1) input to PLD AND Array is blocked, saving power. 0 = on CLKIN (PD1) input to the PLD Macrocells is passed onto PLDs. 1 = off CLKIN (PD1) input to PLD Macrocells is blocked, saving power. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero.

AC power, and propagation delay. frequency of inputs to the PLDs. Table 18. Power Management Mode Registers PMMR2 Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (Reset ) pulses do not clear the registers. input to the PLD AND Array and the OMCs. by setting bits 4 or 5 to a 1 in PMMR0. Bit 0 X 0 Not used, and should be set to zero. Bit 1 X 0 Not used, and should be set to zero. 0 = on Cntl0 input to the PLD AND Array is passed onto PLDs. 1 = off Cntl0 input to PLD AND Array is blocked, saving power. 0 = on Cntl1 input to the PLD AND Array is passed onto PLDs. 1 = off Cntl1 input to PLD AND Array is blocked, saving power. 0 = on Cntl2 input to the PLD AND Array is passed onto PLDs. 1 = off Cntl2 input to PLD AND Array is blocked, saving power. 0 = on PD0 input to the PLD AND Array is passed onto PLDs. 1 = off PD0 input to PLD AND Array is blocked, saving power. 0 = on PC7 input to the PLD AND Array is passed onto PLDs. 1 = off PC7 input to PLD AND Array is blocked, saving power. Bit 7 X 0 Not used, and should be set to zero.

Figure 24. Reset (RESET) Timing Table 19. Status During Power-On Reset, Warm Reset and Power-down Mode be completely programmed in 10 to 20 seconds.

and TERR in addition to TMS, TCK, TDI and TDO. parallel port on any PC or laptop. JTAG In-System Programming (ISP). the four pins are enabled for JTAG operation.

1. PSDsoft Express Pin Configuration -OR-
2. PSDsoft Express PLD equation -OR-
3. DSP writes to register in csiop block

JTAG pins using this method is not recommended. Table 20. JTAG Port Signals nel. See Application Note AN1153. memory Program or Erase cycles are in progress.

Obsolete Product(s) - Obsolete Product(s) DSM2180F3 to use 10 kΩ pull-up resistors to VCC on all JTAG- ISP signals on your circuit board. Initial Delivery State When delivered from ST, the device has all bits in the memory and PLDs erased to logic 1. The DSM Configuration Register bits are set to 0. The code, configuration, and PLD logic are loaded using the programming procedure. The four basic JTAG ISP signals (TCK, TMS, TDI, TDO) are ready for ISP function.

is considerably different if the Turbo bit is 0. number of Product Terms (PT) used. Figure 25. PLD I

Table 21. Absolute Maximum Ratings

Table 22. Operating Conditions Table 23. AC Measurement Conditions Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 26. AC Measurement I/O Waveform Figure 27. AC Measurement Load Circuit Table 24. Capacitance Note: 1. Sampled only, not 100% tested.

1. Typical values are for T A = 25°C and nominal supply voltages.

Table 25. AC Symbols for PLD Timing Figure 28. Switching Waveforms – Key

Table 26. DC Characteristics

1. PLD is in non-Turbo mode, and none of the inputs are switching.
2. Please see Figure 25 for the PLD current calculation.

Table 27. CPLD Combinatorial Timing Note: 1. Fast Slew Rate output available on PB3-PB0, and PD2-PD0.

Table 28. CPLD Macrocell Synchronous Clock Mode Timing Note: 1. Fast Slew Rate output available on PB3-PB0, and PD2-PD0.

1. CLKIN (PD1) t CLCL = tCH + tCL .

Table 29. CPLD Macrocell Asynchronous Clock Mode Timing

Table 30. Input Macrocell Timing Note: 1. Inputs from Port B, and C relative to register/ latch clock from the PLD. Figure 33. Input Macrocell Timing (product term clock)

Table 31. Read Timing Note: 1. Any input used to select an internal DSM function. Figure 34. Read Timing

Table 32. Write Timing Note: 1. Any input used to select an internal DSM function.

1. Assuming data is stable before active write signal.
2. Assuming write is active before data becomes valid.
3. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal DSM memory.

Figure 35. Write Timing

Table 33. Flash Memory Program, Write and Erase Times Note: 1. Programmed to all zero before erase.

1. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

Table 34. Reset (Reset) Timing Note: 1. Reset (RESET ) does not reset Flash memory Program or Erase cycles.

1. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in Read mode.

Figure 36. Reset (RESET) Timing

Table 35. ISC Timing Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.

1. For Program or Erase PLD only.

Figure 37. ISC Timing

Obsolete Product(s) - Obsolete Product(s) DSM2180F3 PACKAGE MECHANICAL In order to meet environmental requirements, ST offers the DSM2180F3V in ECOPACK ® packag- es. These packages have a Lead-free second-lev- el interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Stan- dard JESD97. The maximum ratings rela ted to soldering condi- tions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK speci- fications are available at: www.st.com. PLCC52 – 52 lead Plastic Leaded Chip Carrier, rectangular Note: Drawing is not to scale. PLCC52 – 52 lead Plastic Leaded Chip Carrier, rectangular Symbol mm inches A 4.19 4.57 0.165 0.180 A1 2.54 2.79 0.100 0.110 A2 – 0.91 – 0.036 B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 C 0.246 0.261 0.0097 0.0103 D 19.94 20.19 0.785 0.795 D1 19.05 19.15 0.750 0.754 D2 17.53 18.54 0.690 0.730 E 19.94 20.19 0.785 0.795 E1 19.05 19.15 0.750 0.754 E2 17.53 18.54 0.690 0.730 PLCC-B D E1 E 1 N CP b D2/E2 e A D3/E3 M L C

Table 36. Assignments – PLCC52

2 PB5 28 PA1

4 PB3 30 AD0

5 PB2 31 AD1

6 PB1 32 AD2

7 PB0 33 AD3

10 PD0 36 AD6

11 PC7 37 AD7

12 PC6 38 V

13 PC5 39 AD8

14 PC4 40 AD9

15 VCC 41 AD10

16 GND 42 AD11

17 PC3 43 AD12

18 PC2 (VSTBY) 44 AD13

19 PC1 45 AD14

20 PC0 46 AD15

21 PA7 47 CNTL0

22 PA6 48 RESET

23 PA5 49 CNTL2

24 PA4 50 CNTL1

25 PA3 51 PB7

26 GND 52 PB6

Obsolete Product(s) - Obsolete Product(s) DSM2180F3 PQFP52 - 52 lead Plastic Quad Flatpack Note: Drawing is not to scale. PQFP52 - 52 lead Plastic Quad Flatpack Symb. mm inches A 2.35 0.093 A1 0.25 0.010 b 0.22 0.38 0.009 0.015 c 0.11 0.23 0.004 0.009 e 0.65 – – 0.026 L1 1.60 – – 0.063 α 0° 7° 0° 7° N5 2 5 2 Nd 13 13 Ne 13 13 CP 0.10 0.004 QFP Nd CP b e A N LA1 α D ENe c

Table 37. Pin Assignments – PQFP52

8 VCC 34 AD10

9 GND 35 AD11

10 PC3 36 AD12

11 PC2 37 AD13

12 PC1 38 AD14

13 PC0 39 AD15

14 PA7 40 CNTL0

15 PA6 41 RESET

16 PA5 42 CNTL2

17 PA4 43 CNTL1

18 PA3 44 PB7

19 GND 45 PB6

20 PA2 46 GND

21 PA1 47 PB5

22 PA0 48 PB4

23 AD0 49 PB3

24 AD1 50 PB2

25 AD2 51 PB1

26 AD3 52 PB0

Table 38. Ordering Information Scheme Note: 1. The 3.3V±10% devices are not covered by this data sheet, but by the DSM2180F3V data sheet.

Obsolete Product(s) - Obsolete Product(s) DSM2180F3

REVISION HISTORY

Table 39. Document Revision History Updated datasheet status to “not for new design”. Added ECOPACK text in cover page and section titled “Package Mechanical”.