DSM2150F5V

DSM2150F5V STMICROELECTRONICS | Alldatasheet

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Technical content

DSPs from Analog Devices, Inc. calibration and configuration constants. Eliminate external serial EEPROM. Figure 1. TQFP 80-pin Package PC. Available from www.st.com/psm .

ory device for use with the Analog Devices DSPs. to 35 seconds with no involvement of the DSP. party programmers. See www.st.com/psm . up to 32 configurable I/O pins to the DSP system. bus, even with security bit set. Figure 2. System Block Diagram, Two Chip Solution

512 Kbytes

16 MACROCELL PLD

16 I/O

32 Kbytes

Table 1. DSM2150F5V DSP Memory System Devices Table 2. Compatible Analog Devices DSPs

512 KBytes,

32 KBytes,

Figure 3. TQFP Connections

60 CNTL1

59 CNTL0

58 PA7

57 PA6

56 PA5

55 PA4

54 PA3

53 PA2

52 PA1

51 PA0

50 GND

49 GND

48 PC7

47 PC6

46 PC5

45 PC4

44 PC3

43 PC2

42 PC1

41 PC0

Table 3. Pin Description (Pin Assignments in Appendix A ) AD0-15 In Sixteen address inputs from the DSP . Active low WRITE strobe input from the DSP , typically connected to DSP WR signal. Also functions as WRL for DSPs which use WRL strobe when writing low byte only in 16-bit word. CNTL1 In Active low READ strobe input from the DSP . operation. BHE = ’0’ will allow a byte WRITE from data lines D8-D15 ignoring data lines D0-D7. are not affected by BHE (always read both bytes). Active low reset input from system. – MCU I/O – DSP may write or read pins directly at runtime with csiop registers. – CPLD Output Macrocell (McellA0-7) outputs. – Inputs to the PLDs (via Input Macrocells). Can be used to input address A16 and above. Note: PA0-PA7 may be configured at run-time as standard CMOS or Open Drain Outputs. – MCU I/O – DSP may write or read pins directly at runtime with csiop registers. – CPLD Output Macrocell (McellB0-7 or McellC0-7) outputs. – Inputs to the PLDs (via Input Macrocells). Can be used to input address A16 and above. Note: PB0-PB7 may be configured at run-time as standard CMOS or Open Drain Outputs. – MCU I/O – DSP may write or read pins directly at runtime with csiop registers. – DPLD chip-select outputs (ECS0-7, does not consume MicroCells). – Inputs to the PLDs (via Input Macrocells). Can be used to input address A16 and above. Note: PC0-PC7 may be configured at run-time as standard CMOS or Faster Slew Rate Output. – MCU I/O – DSP may write or read pins directly at runtime with csiop registers. input address A16 and above. – PD1 can be configured as CLKIN, a common clock input to PLD. memory is disabled to conserve more power when CSI is logic high. – PD3 can be used for WRH strobe from DSP to write high byte only for 16-bit configuration.

Eight configurable Port E signals with the following functions: – MCU I/O – DSP may write or read pins directly at runtime with csiop registers. – PE0, PE1, PE2, and PE3 can form the JTAG IEEE-1149.1 ISP serial interface as signals TMS, TCK, TDI, and TDO respectively. – PE4 and PE5 can form the enhanced JTAG signals TSTAT and TERR respectively. Reduces ISP programming time up to 30% when used in addition to the standard four JTAG signals: TDI, TDO, TMS, TCK. – PE4 can be configured as the Ready/Busy output to indicate Flash memory programming status during parallel programming. May be polled by DSP or used as DSP interrupt. Note 1: PE0-PE7 may be configured at run-time as either standard CMOS or Open Drain Outputs. Note 2: The JTAG ISP pins may be multiplexed with other I/O functions. PF0-7 I/O Port F connects to eight data bus signals, D0 - D7 from DSP . PG0-7 I/O Port G connects to eight data bus signals, D8 - D15 from DSP if 16-bit data path is used. Otherwise, PG0-PG7 can be used for general purpose MCU I/O pins. Note: PG0-PG7 may be configured at run-time as standard CMOS or Open Drain Outputs. V CC Supply Voltage GND Ground pins Pin Name Type Description

Major functional blocks are shown in Figure 4. switch between 8-bits and 16-bits during runtime. DSM2150F5V and different DSPs. Figure 4. Block Diagram

4 BLOCKS, 8 KB

32 KBytes total

8 BLOCKS, 64 KB

512 KBytes total

24 INPUT

16 OUTPUT MICROCELLS

The 4M bit (512 KByte) Main Flash memory is di- vided into eight equally-sized 64 KByte sectors that are individually selectable through the De- code PLD. Each Flash memory sector can be lo- cated at any address as defined by the user with PSDsoft Express. DSP code and data are easily placed in flash memory using PSDsoft Express, the software development tool. Secondary Flash Memory The 256Kbit (32 KByte) Secondary Flash memory is divided into eight equally-sized 8 KByte sectors that are individually selectable through the De- code PLD. Each Flash memory sector can be lo- cated at any address as defined by the user with PSDsoft Express. DSP code and data can also be placed Secondary Flash memory using the PSD- soft Express development tool. Secondary flash memory is good for storing data because of its smaller sectors. Software EEPROM emulation techniques can be used for small data sets that change frequently on a byte-by-byte ba- sis. Secondary flash may also be used to store custom start-up code for applications that do not “boot” us- ing DMA, but instead start executing code from ex- ternal memory upon reset (bypass internal DSP boot ROM). Storing code here can keep the entire Main Flash free of initialization code for clean soft- ware partitioning. If only one or more 8 KByte sec- tors are needed for start-up code, the remaining sectors of Secondary Flash may be used for data storage. In-Application-Programming (IAP) may be imple- mented using Secondary Flash. For example, code to implement IAP over a USB channel may be stored here. The DSP executes code from Sec- ondary Flash array while erasing and writing new code to the Main Flash array as it is received over the USB channel. Any communication channel that the DSP supports can be used for IAP. Secondary Flash may also be used as an exten- sion to Main Flash memory producing a total of 544 KBytes. Miscellaneous: Main and Secondary Flash memo- ries are totally independent, allowing concurrent operation. The DSP can read from one memory while erasing or programming the other. The DSP can erase Flash memories by individual sectors or the entire Flash memory array may be erased at one time. Each sector in either Flash memory ar- ray may be individually write protected, blocking any WRITEs from the DSP (good for boot and start-up code protection). The Flash memories au- tomatically go to standby between DSP READ or WRITE accesses to conserve power. Maximum access times include sector decoding time. Maxi- mum erase cycles is 100K and data retention is 15 years minimum. Flash memory, as well as the en- tire DSM device may be programmed with the JTAG ISP interface with no DSP involvement. Programmable Logic (PLDs) The DSM family contains two PLDS that may op- tionally run in Turbo or Non-Turbo Mode. PLDs op- erate faster (less propagation delay) while in Turbo Mode but consume more power than Non- Turbo Mode. Non-Turbo Mode allows the PLDs to automatically go to standby when no inputs are change to conserve power. The Turbo Mode set- ting is controlled at runtime by DSP software. Decode PLD (DPLD). This is programmable log- ic used to select one of the eight individual Main Flash memory segments, one of four individual Secondary Flash memory segments, or the group of control registers within the DSM device. The DPLD can also drive external chip select signals on Port C pins. DPLD input signals include: DSP address and control signals, Page Register out- puts, DSM Port Pins, CPLD logic feedback. Complex PLD (CPLD). This programmable logic is used to create both combinatorial and sequen- tial general purpose logic. The CPLD contains 16 Output Macrocells (OMCs) and 24 Input Macro- cells (IMCs). PSD Macrocell registers are unique in that they have direct connection to the DSP data bus allowing them to be loaded and read directly by the DSP at runtime. This direct access is good for making small peripheral devices (shiftier, counters, state machines, etc.) that are accessed directly by the DSP with little overhead. DPLD in- puts include DSP address and control signals, Page Register outputs, DSM Port Pins, and CPLD feedback. OMCs: The general structure of the CPLD is simi- lar in nature to a 22V10 PLD device with the famil- iar sum-of-products (AND-OR) construct. True and compliment versions of 73 input signals are available to a large AND array. AND array outputs feed into a multiple product-term OR gate within each OMC (up to 10 product-terms for each OMC). Logic output of the OR gate can be passed on as combinatorial logic or combined with a flip- flop within in each OMC to realize sequential logic. OMCs can be used as a buried nodes with feed- back to the AND array or OMC output can be rout- ed to pins on Port A or Port B. IMCs: Inputs from pins on Ports A, B or C are rout- ed to IMCs for conditioning (clocking or latching) as they enter the chip, which is good for sampling and debouncing inputs. Alternatively, IMCs can pass Port input signals directly to PLD inputs with- out clocking or latching. The DSP may read the IMCs at any time.

A block of 256 bytes is decoded inside the DSM device for control and status registers. 50 registers are used from the block of 256 locations to control the output state of I/O pins, to READ I/O pins, to control power management, to READ/WRITE macrocells, and other functions at runtime. See Table 4., page 13 for description. The base ad- dress of these 256 locations is referred to in this data sheet as csiop (Chip Select I/O Port). Individ- ual registers within this block are accessed with an offset from the base address. Some DSPs can ac- cess csiop registers using I/O memory with the IOMS strobe (if equipped). csiop registers are bytes. When the DSM is configured for 16-bit op- eration, csiop registers are read in byte pairs at even addresses only. Care should be taken while writing csiop registers to ensure the proper byte is written within the byte pair. This is not a problem for DSPs that support the BHE (Byte High Enable) signal on the CNTL2 input pin, or WRL, WRH (WRITE low byte, WRITE high byte) on the CNTL0 and PD3 input pins of the DSM2150F5V. Memory Page Register This 8-bit register can be loaded and read by the DSP at runtime as one of the csiop registers. Its outputs feed directly into both PLDs. The page register can be used for special memory mapping requirements and also for general logic. I/O Ports The DSM has 52 individually configurable I/O pins distributed over the seven ports (Ports A, B, C, D, E, F, and G). At least 32 I/O are available when DSM2150F5V is connected with 8-bit data path, and at least 24 I/O are available with 16-bit data path. Each I/O pin can be individually configured for different functions such as standard MCU I/O ports or PLD I/O on a pin by pin basis. (MCU I/O means that for each pin, its output state can be controlled or its input value can be read by the DSP at runtime using the csiop registers like an MCU would do.) The static configuration of all Port pins is defined with the PSDsoft Express ™ software development tool. The dynamic action of the Ports pins is con- trolled by DSP runtime software. JTAG ISP Port In-System Programming (ISP) can be performed through the JTAG signals on Port E. This serial in- terface allows programming of the entire DSM de- vice or subsections (that is, only Flash memory, for example) without the participation of the DSP. A blank DSM device soldered to a circuit board can be completely programmed in 15 to 35 seconds. The basic JTAG signals; TMS, TCK, TDI, and TDO form the IEEE-1149.1 interface. The DSM device does not implement the IEEE-1149.1 Boundary Scan functions. The DSM uses the JTAG interface for ISP only. However, the DSM device can reside in a standard JTAG chain with other JTAG devices and it will remain in BYPASS Mode while other devices perform Boundary Scan. ISP programming time can be reduced as much as 30% by using two more signals on Port E, TSTAT and TERR in addition to TMS, TCK, TDI and TDO. The FlashLINK™ JTAG programming cable is available from STMicroelectronics for $USD59 and PSDsoft Express software is available at no charge from www.st.com/psm . That is all that is needed to program a DSM device using the paral- lel port on any PC or notebook. See PROGRAM- MING IN-CIRCUIT USING JTAG ISP, page 49. Power Management The DSM has bits in csiop registers that are con- figured at run-time by the DSP to reduce power consumption of the CPLD. The Turbo Bit in the PMMR0 register can be set to logic '1' and the CPLD will go to Non-Turbo Mode, meaning it will latch its outputs and go to sleep until the next tran- sition on its inputs. There is a slight penalty in PLD performance (longer propagation delay), but sig- nificant power savings are realized. Additionally, other bits in two csiop registers can be set by the DSP to selectively block signals from entering the CPLD which reduces power con- sumption. Both Flash memories automatically go to standby current between accesses. No user action re- quired. Security and NVM Sector Protection A programmable security bit in the DSM protects its contents from unauthorized viewing and copy- ing. When set, the security bit will block access of programming devices (JTAG or others) to the DSM Flash memory and PLD configuration. The only way to defeat the security bit is to erase the entire DSM device, after which the device is blank and may be used again. Additionally, the contents of each individual Flash memory sector can be write protected (sector pro- tection) by configuration with PSDsoft Express ™ . This is typically used to protect DSP boot code from being corrupted by inadvertent WRITEs to Flash memory from the DSP.

csiop base. See Appendix B for bit definitions. Table 4. CSIOP Registers and Their Offsets (in Hexadecimal) level of Port pins. No WRITEs. Port pins. Read to check status. output. Write to set direction of Port pins. Logic ’1’ = out, Logic ’0’ = in. Read to check status. high slew rate on other pins. Read to check status. Macrocells 0A 0B 1A Read to obtain state of IMCs. No WRITEs. on each I/O Port driver. No WRITEs. Macrocells A 20 Read to get logic state of output of OMC bank A. Write to load registers of OMC bank A. Macrocells B 21 Read to get logic state of output of OMC bank B. Write to load registers of OMC bank B. corresponding OMC. Logic ’0’ will pass OMC value. corresponding OMC. Logic ’0’ will pass OMC value. active. Logic ’1’ = device secured. PMMR0 B0 Power Management Register 0. WRITE and READ. PMMR2 B4 Power Management Register 2. WRITE and READ. Page E0 Memory Page Register. WRITE and READ. Memory_ID0 F0 Read to get size of Main Flash memory. No WRITEs. Memory_ID1 F1 Read to get size of 2nd Flash memory. No WRITEs.

Figure 4., page 10 shows major functional areas of the device: I Flash Memories I PLDs (DPLD, CPLD, Page Register) I DSP Bus Interface (Address, Data, Control) I I/O Ports I Runtime Control Registers I JTAG ISP Interface The following describes these functions in more detail. Flash Memories The Main Flash memory array is divided into eight equal 64 KByte sectors. The Secondary Flash memory array is divided into four equal 8 KByte sectors. Each sector is selected by the DPLD can be separately protected from program and erase cycles. This configuration is specified by using PS- Dsoft Express ™ . Memory Sector Select Signals.The DPLD gen- erates the Select signals for all the internal memo- ry blocks (see Figure 7., page 26) . E a c h o f t h e twelve sectors of the Flash memories has a select signal (FS0-FS7, or CSBOOT0-CSBOOT3 ) which contains up to three product terms. Having three product terms for each select signal allows a given sector to be mapped into multiple areas of system memory if needed. Ready/Busy (PE4).This signal can be used to output the Ready/Busy status of the device. Ready/ Busy is a ’0’ (Busy) when either Flash memory ar- ray is being written, or when either Flash memory array is being erased. The output is a ’1’ (Ready) when no WRITE or Erase cycle is in progress. This signal may be polled by the DSP or used as a DSP interrupt to indicate when an erase or program cy- cle is complete. Memory Operation. The Flash memories are ac- cessed through the DSP Address, Data, and Con- trol Bus Interface. DSPs and MCUs cannot write to Flash memory as it would an SRAM device. Flash memory must first be “unlocked” with a special sequence of WRITE operations to invoke an internal algorithm, then a single data byte (or word if DSM2150F5V is con- figured for 16-bit operation) is written to the Flash memory array, then programming status is checked by a READ operation or by checking the Ready/ Busy pin (PE4). This “unlocking” sequence optionally may be bypassed by using the Unlock Bypass command to reduce programming time. Table 5., page 15 lists all of the special instruction sequences to program (write) data to the Flash memory arrays, erase the arrays, and check for different types of status from the arrays when the DSM2150F5V is configured to operate as an 8-bit device. Table 6 lists instruction sequences when the DSM2150F5V is configured for 16-bit opera- tion. These instruction sequences are different combinations of individual WRITE and READ op- erations. IMPORTANT: The DSP cannot read and execute code from the same Flash memory array for which it is directing an instruction sequence. Or more simply stated, the DSP may not read code from the same Flash array that is writing or erasing. In- stead, the DSP must execute code from an alter- nate memory (like its own internal SRAM or a different Flash array) while sending instructions to a given Flash array. Since the two Flash memory arrays inside the DSM device are completely inde- pendent, the DSP may read code from one array while sending instructions to the other. After a Flash memory array is programmed (writ- ten) it will go to “Read Array” Mode, then the DSP can read from Flash memory just as if would from any ROM or SRAM device.

Table 5. Instruction Sequences for 8-bit Operation (Notes 1,2,3,4)

1. A desired internal Flash memory sector select signal (FS0 - FS7 or CSBOOT0 - CSBOOT3) must be active for each WRITE or

DSP and the memory mapping defined in PSDsoft Express. FS0 - FS7 and CSBOOT0-CSBOOT3 are active high logic internally.

1. Only address Bits A11-A0 are used during Flash memory instruction sequence decoding bus cycles. The individual sector select

signal (FS0 - FS7 or CSBOOT0-CSBOOT3) which is active during the instruction sequences determines the complete address.

1. For WRITE operations, addresses are latched on the falling edge of Write Strobe (WR, CNTL0), Data is latched on the rising edge
2. No Unlock or Instruction cycles are required when the device is in the Read Array Mode. Operation is like reading a ROM device.

1. The Reset Flash instruction is required to return to the normal Read Array Mode if the Error Flag Bit (DQ5) goes High, or after read- ing the Flash Identifier or after reading the Sector Protection Status. 7. The DSP cannot invoke this instruction sequence while executing code from the same Flash memory as that for which the instruc- tion sequence is intended. The DSP must fetch, for example, the code from the DSP SRAM when reading the Flash memory Iden- tifier or Sector Protection Status. 8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0) = (1,0) 9. Directing this command to any individual active Flash memory segment (FS0 - FS7) will invoke the bulk erase of all eight Flash memory sectors. Likewise, directing command to any Secondary Flash sector (CSBOOT0-3) will invoke erase of all four sectors. 10. DSP writes command sequence to initial segment to be erased, then writes the byte 30h to additional sectors to be erased. 30h must be addressed to one of the other Flash memory segments (FS0-7 or CSBOOT0-3) for each additional segment (write 30h to any address within a desired sector). No more time than tTIMEOUT can elapse between subsequent additional sector erase com- mands. 11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protect Status, when in the Suspend Sector Erase Mode. The Suspend Sector Erase instruction sequence is valid only during a Sector Erase cycle. 12. The Resume Sector Erase instruction sequence is valid only during the Suspend Sector Erase Mode. 13. The Unlock Bypass instructions required prior to the Unlock Bypass Program Instruction. 14. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in Unlock Bypass Mode.

Table 6. Instruction Sequences for 16-bit Operation (Notes 1,2,3,4,15)

1. A desired internal Flash memory sector select signal (FS0 - FS7 or CSBOOT0 - CSBOOT3) must be active for each WRITE or

DSP and the memory mapping defined in PSDsoft Express. FS0 - FS7 and CSBOOT0-CSBOOT3 are active high logic internally.

1. Only address Bits A11-A0 are used during Flash memory instruction sequence decoding bus cycles. The individual sector select

signal (FS0 - FS7 or CSBOOT0-CSBOOT3) which is active during the instruction sequences determines the complete address.

1. For WRITE operations, addresses are latched on the falling edge of Write Strobe (WR, CNTL0), Data is latched on the rising edge
2. No Unlock or Instruction cycles are required when the device is in the Read Array Mode. Operation is like reading a ROM device.
3. The Reset Flash instruction is required to return to the normal Read Array Mode if the Error Flag Bit (DQ5) goes High, or after read-

ing the Flash Identifier or after reading the Sector Protection Status.

9 Write XXAAh

1. The DSP cannot invoke this instruction sequence while executing code from the same Flash memory as that for which the instruc- tion sequence is intended. The DSP must fetch, for example, the code from the DSP SRAM when reading the Flash memory Iden- tifier or Sector Protection Status. 8. The data is XX00h for an unprotected sector, and XX01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0) = (1,0) 9. Directing this command to any individual active Flash memory segment (FS0 - FS7) will invoke the bulk erase of all eight Flash memory sectors. Likewise, directing command to any Secondary Flash sector (CSBOOT0-3) will invoke erase of all four sectors. 10. DSP writes command sequence to initial segment to be erased, then writes the word XX30h to additional sectors to be erased. XX30h must be addressed to one of the other Flash memory segments (FS0-7 or CSBOOT0-3) for each additional segment (write XX30h to any address within a desired sector). No more time than tTIMEOUT can elapse between subsequent additional sector erase commands. 11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protect Status, when in the Suspend Sector Erase Mode. The Suspend Sector Erase instruction sequence is valid only during a Sector Erase cycle. 12. The Resume Sector Erase instruction sequence is valid only during the Suspend Sector Erase Mode. 13. The Unlock Bypass instructions required prior to the Unlock Bypass Program Instruction. 14. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in Unlock Bypass Mode. 15. All bus cycles in an instruction sequence are WRITEs or READs to an even address (XXAAAh or XX554h), and only the low byte, D0-D7, is significant (upper byte on D8-D15 is ignored). A Flash memory Program bus cycle writes a word to an even address.

specific WRITE or READ operations. programmed in bytes to even or odd addresses. until the entire command string has been received. Table 7. Status Bit Definition

1. DQ7-DQ0 represent the Data Bus bits, D7-D0.
2. When the DSM2150F5V is configured for 16-bit operation, DQ8-DQ15 are not significant and can be ignored.

Under typical conditions, the DSP may read the Flash memory using READ operations just as it would a ROM or RAM device. Alternately, the DSP may use READ operations to obtain status infor- mation about a Program or Erase cycle that is cur- rently in progress. Lastly, the DSP may use instruction sequences to read special data from these memory blocks. The following sections de- scribe these READ instruction sequences. Read Memory Contents Flash memory is placed in the Read Array Mode after Power-up, chip reset, or a Reset Flash mem- ory instruction sequence (see Table 5., page 15 or Table 6., page 17). The DSP can read the memory contents of the Flash memory by using READ op- erations any time the READ operation is not part of an instruction sequence. Bytes are read from even or odd addresses when the DSM2150F5V is configured for 8-bit operation. Only 16-bit words are read from even addresses when the DSM2150F5V is configured for 16-bit operations. Read Main Flash Identifier The Main Flash memory identifier is read with an instruction sequence composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 5., page 15 or Table 6., page 17). Dur- ing the READ operation the appropriate internal Sector Select (FS0-FS7 ) must be active. The iden- tifier is E8h (or XXE8h for 16-bit mode). Not appli- cable to Secondary Flash. Read Memory Sector Protection Status The Flash memory Sector Protection Status is read with an instruction sequence composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 5., page 15 or Table 6., page 17). The READ operation will produce 01h (XX01h for 16-bit mode) if the Flash sector is protected or 00h (XX00h or 16-bit mode) if the sec- tor is not protected. Internal Sector Select (FS0- FS7 or CSBOOT0-CSBOOT3) designates the Flash memory sector whose protection has to be verified. Alternatively, the sector protection status can also be read by the DSP accessing the Flash memory Protection registers in csiop space. See the sec- tion entitled “Flash Memory Sector Protect” for register definitions. Reading the Erase/Program Status Bits The device provides several status bits to be used by the DSP to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the DSP spends per- forming these tasks and are defined in Table 7., page 19. The status bits can be read as many times as needed. DQ8 - DQ15 are insignificant and can be ignored when the DSM2150F5V is configured to operate in 16-bit mode, however, the READ operation must occur on an even address boundary. For Flash memory, the DSP can perform a READ operation to obtain these status bits while an Erase or Program instruction sequence is being executed by the embedded algorithm. See PRO- GRAMMING FLASH MEMORY, page 22 , for de- tails. Data Polling Flag (DQ7) When erasing or programming in Flash memory, the Data Polling Flag Bit (DQ7) outputs the com- plement of the bit being entered for programming/ writing on the Data Polling Flag Bit (DQ7). Once the Program instruction sequence or the WRITE operation is completed, the true logic value is read on the Data Polling Flag Bit (DQ7). – Data Polling is effective after the fourth WRITE pulse (for a Program instruction sequence) or after the sixth WRITE pulse (for an Erase instruction sequence). It must be performed at the address being programmed or at an address within the Flash memory sector being erased. – During an Erase cycle, the Data Polling Flag Bit (DQ7) outputs a ’0.’ After completion of the cycle, the Data Polling Flag Bit (DQ7) outputs the last bit programmed (it is a ’1’ after erasing). – If the byte/word to be programmed is in a protected Flash memory sector, the instruction sequence is ignored. – If all the Flash memory sectors to be erased are protected, the Data Polling Flag Bit (DQ7) is reset to ’0’ for t TIMOUT , and then returns to the previous addressed byte. No erasure is performed.

Toggle Flag (DQ6) The device offers an alternative way for determin- ing when the Flash memory Program cycle is com- pleted. During the internal WRITE operation and when the Sector Select FS0-FS7 (or CSBOOT0- CSBOOT3) is true, the Toggle Flag Bit (DQ6) tog- gles from ’0’ to ’1’ and ’1’ to ’0’ on subsequent at- tempts to read any byte of the memory. When the DSM2150F5V is configured to operate in 16-bit mode, status READs must occur at even address- es, DQ8 - DQ15 are insignificant and can be ig- nored. When the internal cycle is complete, the toggling stops and the data READ on the Data Bus is the addressed memory byte/word. The device is now accessible for a new READ or WRITE operation. The cycle is finished when two successive READs yield the same output data. – The Toggle Flag Bit (DQ6) is effective after the fourth WRITE operation (for a Program instruction sequence) or after the sixth WRITE operation (for an Erase instruction sequence). – If the byte/word to be programmed belongs to a protected Flash memory sector, the instruction sequence is ignored. – If all the Flash memory sectors selected for erasure are protected, the Toggle Flag Bit (DQ6) toggles to ’0’ for t TIMOUT and then returns to the previous addressed byte. Error Flag (DQ5) During a normal Program or Erase cycle, the Error Flag Bit (DQ5) is to ’0.’ This bit is set to ’1’ when there is a failure during Flash memory byte/word Program operation, Sector Erase, or Bulk Erase operation. In the case of Flash memory programming, the Er- ror Flag Bit (DQ5) indicates the attempt to program a Flash memory bit from the programmed state, logic ’0,’ to the erased state, logic ’1’, which is not valid. The Error Flag Bit (DQ5) may also indicate a Time-out condition while attempting to program a byte/word. In case of an error in a Flash memory Sector Erase or byte/word Program cycle, the Flash memory sector in which the error occurred or to which the programmed byte/word belongs must no longer be used. Other Flash memory sectors may still be used. The Error Flag Bit (DQ5) is reset after a Re- set Flash instruction sequence. Erase Time-out Flag (DQ3) The Erase Time-out Flag Bit (DQ3) reflects the time-out period allowed between two consecutive Sector Erase instruction sequence bytes/words. The Erase Time-out Flag Bit (DQ3) is reset to ’0’ after a Sector Erase cycle for a time period t TIMOUT unless an additional Sector Erase instruction se- quence is decoded. After this time period, or when the additional Sector Erase instruction sequence is decoded, the Erase Time-out Flag Bit (DQ3) is set to ’1.’

in 8-bit bytes to even or odd addresses. grammed in 16-bit words to even addresses only. byte (or word-by-word for 16-bit mode). Table 8. 16-Bit Data Bus with BHE Table 9. 16-Bit Data Bus with WRH and WRL

The PLDs bring programmable logic to the device. vice and available upon Power-up. ponents, such as memory, registers, and I/O ports. lect (ECS0-ECS7) signals on Port C. The AND Array is used to form product terms. the PLDs. Input signals are shown in Table 10. block DSP control signals from entering the PLDs. unique characteristics suited for its applications. They are described in the following sections. Table 10. DPLD and CPLD Inputs

1. Additional DSP control signals may enter the DMS device

Figure 6. PLD Diagram

24 Input Macrocell

16 Output

4 PORT D Inputs

4 Secondary Flash Memory Selects

pins, each with one product term. Figure 7. DPLD Logic Array

8 Flash Main

4 Secondary

in most standard PLD macro cell architectures. Figure 8. Macrocell and I/O Port

McellB0-McellB7, are connected to Ports B pins. be driven from a product term of the AND Array. use up to two product terms. Table 11. Output Macrocell Port and Data Bit Assignments

The CPLD has a Product Term Allocator. PSDsoft Express™ uses the Product Term Allocator to bor- row and place product terms from one Macrocell to another. This happens automatically in PSDsoft Express ™ , but understanding how allocation works will help you if your logic design does not “fit”, in which case you may try selecting a different pin or different OMC where the allocation resourc- es may differ and the design will then fit. The fol- lowing list summarizes how product terms are allocated: I McellA0-McellA7 all have three native product terms and may borrow up to six more I McellB0-McellB3 all have four native product terms and may borrow up to five more I McellB4-McellB7 all have four native product terms and may borrow up to six more. Each Macrocell may only borrow product terms from certain other Macrocells. Product terms al- ready in use by one Macrocell are not available for another Macrocell. Product term allocation does not add any propagation delay to the logic. If an equation requires more product terms than are available to it through product term allocation, then “external” product terms are required, which consumes other OMC. This is called product term expansion and also happens automatically in PS- Dsoft Express ™ as needed. Product tern expan- sion causes additional propagation delay because an OMC is consumed by the expansion and it’s output is rerouted (or fed back) into the AND array. You can examine the fitter report generated by PSDsoft Express to see resulting product term al- location and product term expansion. Loading and Reading the OMCs Each of the two OMC blocks (8 OMCs each) occu- pies a memory location in the DSP address space, as defined in the csiop block MCELLA0-7 and MCELLB0-7 (see Table 4., page 13). The flip- flops in each of the 16 OMCs can be loaded from the data bus by a DSP. Loading the OMCs with data from the DSP takes priority over internal func- tions. As such, the preset, clear, and clock inputs to the flip-flop can be overridden by the DSP. The ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. Data is loaded into the OMC on the trailing edge of Write Strobe coming from CNTL0.

Figure 9. CPLD Output Macrocell

There is one Mask Register for each of the two groups of eight OMCs. The Mask Registers can be used to block the loading of data to individual OMCs. The default value for the Mask Registers is 00h, which allows loading of all the OMCs. When a given bit in a Mask Register is set to a ’1,’ the DSP is blocked from writing to the associated OMC. For example, suppose McellA0-3 are being used for a state machine. You would not want a DSP WRITE to McellA to overwrite the state ma- chine registers. Therefore, you would want to load the Mask Register for McellA group with the value 0Fh. The Output Enable of the OMC The OMC block can be connected to an I/O port pin as a PLD output. The output enable of each port pin driver is controlled by a single product term from the AND Array, ORed with the Direction Register output. The pin is enabled upon Power- up if no output enable equation is defined and if the pin is declared as a PLD output in PSDsoft Ex- press. If the OMC output is specified as an internal node and not as a port pin output in the PSDsoft Ex- press, then the port pin can be used for other I/O functions. The internal node feedback can be rout- ed as an input to the AND Array. Input Macrocells (IMC) The CPLD has 24 IMCs, one for each pin on Ports A, B and C. The architecture of the IMCs is shown in Figure 10., page 32. The IMCs are individually configurable, and can be used as a latch, a regis- ter, or to pass incoming Port signals prior to driving them onto the PLD input bus. This is useful for sampling and debouncing inputs to the AND array (keypad inputs, etc.). Additionally, the outputs of the IMCs can be read by the DSP asynchronously at any time through the internal data bus using the csiop register block (see Table 4., page 13). The enable for the latch and clock for the register are driven by a product term from the CPLD. Each product term output is used to latch or clock four IMCs. Port inputs 3-0 can be controlled by one product term and 7-4 by another. Configurations for the IMCs are specified by equa- tions specified in PSDsoft Express. See Applica- tion Note AN1171.

Figure 10. Input Macrocell

The “no-glue logic” DSP Bus Interface allows di- rect connection. DSP address, data, and control signals connect directly to the DSM device. See Appendices for typical connections. DSP address, data and control signals are routed to Flash memory, I/O control (csiop), OMCs, and IMCs within the DMS. The DSP address range for each of these components is specified in PSDsoft Express ™ . Typical Memory Map, DSM2150F5V and ADSP21535 BLACKFIN DSP There many different ways to place (or map) the addresses of DSM memory and I/O depending on system requirements. The DPLD allows complete mapping flexibility. Figure 11., page 34 shows one possible system memory map. In this example, the DSP will bypass it’s internal boot ROM at power-on and begin executing code directly from the DSM2150F5V secondary Flash memory. While executing this code, the DSP will load the contents of the DSM2150F5V main Flash memory into the ADSP-21535 internal SRAM, then execute code from that high performance SRAM. The advantage of this is speed, flexibility, IAP, clean software partitioning, and parameter stor- age. – Loading external Flash memory to internal SRAM by 16-bits is faster than booting by 8- bits. Also, subsequent loading of new memory overlays during runtime is also faster by 16- bits. – Bypassing internal DSP boot ROM and executing from DSM secondary memory provides total flexibility to meet system requirements. Like having custom boot ROM programmable by JTAG. – In-Application Programming (IAP) can be implemented by placing custom loader code in DSM secondary flash which, when executed, allows the DSP to receive data over any communication channel (i.e. USB) and write new code/data the DSM main flash memory. Since the DSM Flash arrays are independent, it is possible to read from the secondary flash while writing to the main Flash. – Since the DSM secondary Flash has smaller sector sizes, small data sets and calibration constants may be stored there. EEPROM emulation techniques can be used. – Placing start-up and IAP code in DSM secondary Flash keeps it totally separate DSM main flash memory, affording clean software partitioning. This also ensures robust system operaton since start-up code will always be there and removed from accitental WRITEs or erasures of DSM main flash. The nomenclature fs0..fs7 in Figure 11., page 34 are designators for the individual sectors of Main Flash memory, 64 KBytes each. csboot0..csboot3 are designators for the individual Secondary Flash memory segments, 8 KBytes each. csiop desig- nates the DSM control register block. The designer may easily specify memory mapping in a point-and-click software environment using PSDsoft Express ™ . Specifying the Memory Map with PSDsoft Express™ The memory map shown in Figure 11., page 34 can be easily implemented using PSDsoft Ex- press™ in a point-and-click environment. PSDsoft Express™ will generate Hardware Definition Lan- guage (HDL) statements of the ABEL language. Table 12., page 35 shows the resulting equations generated by PSDsoft Express™ . Specifying these equations using PSDsoft Ex- press™ is very simple. Figure 12., page 35 shows how to specify the equation for the 64 KByte Flash memory segment, fs0. Notice fs0 is qualified with the signal AMS0 . This specification process is re- peated for all other Flash memory segments, the csiop register block, and any external chip select signals that may be needed.

Figure 11. Memory Map, ADSP-21535

Table 12. HDL Statements Generated from PSDsoft Express to Implement Memory Map Figure 12. PSDsoft Express™ Memory Mapping

Figure 13. Typical Connections, DSM2150F5V and ADSP-21535 Blackfin DSP

512 KByte x16

32 KByte x16

8 DATA

Figure 14. Typical Connections, DSM2150F5V and ADSP-21062 SHARC DSP

512 KByte x8

32 KByte x8

16 Cell PLD

Figure 15. Typical Connections, ADSP-TS101S TigerSHARC DSP

Figure 16. Typical Connections, DSM2150F5V and ADSP-2191M

Figure 17. Typical Connections, DSM2150F5V and ADSP-2188M

8 DATA (Upper byte)

There are seven programmable I/O ports: Ports A, B, C, D, E, F, and G. However, typically only four of these ports are available in 8-bit DSP data con- figuration, and 3 ports with 16-bit data. Each of the ports is eight bits except Port D, which is 4 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft Express ™ or by the DSP writing to on-chip registers in the csiop block. The topics discussed in this section are: I General Port architecture I Port operating modes I csiop Port registers I Port Data Registers I Individual Port functionality. General Port Architecture The general architecture of the I/O Port block is shown in Figure 19., page 44. Individual Port ar- chitectures are shown in Figure 19., page 44 to Figure 21., page 46. In general, once the purpose for a port pin has been defined in PSDsoft Ex- press ™ , that pin is no longer available for other purposes. Exceptions are noted. The ports contain an output multiplexer whose se- lect signals are driven by the configuration bits de- termined by PSDsoft Express. Inputs to the multiplexer include the following: I Output data from the Data Out register (for MCU I/O Mode) I CPLD Macrocell output (OMC) I External Chip Selects ESC0-7 from the DPLD to Port C pins only. The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read by the DSP. The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and can be read by the DSP. The Data Out and Macrocell out- puts, Direction and Drive Registers, and port pin input are all connected to the Port Data Buffer (PDB). The Port pin’s tri-state output driver enable is con- trolled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CPLD output in PSDsoft Express ™ , then the Direction Register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the DSP. The Port Data Buffer (PDB) feedback path allows the DSP to check the contents of the registers. Ports A, B, and C have IMCs. The IMCs can be configured as registers (for sampling or debounc- ing), as transparent latches, or direct inputs to the PLDs. The registers and latches are clocked by a product term from the PLD AND Array. The out- puts from the IMCs drive the PLD input bus and can be read by the DSP. See Input Macrocell, page 32. Port Operating Modes The I/O Ports have several modes of operation. Modes are defined using PSDsoft Express ™ , and then runtime control from the DSP can occur using the registers in the csiop block. See Application Note AN1171 for more detail. Table 13., page 43 summarizes which modes are available on each port. Each of the port operating modes are described in the following sections.

Figure 18. General Port Architecture In MCU I/O Mode, DSP I/O Ports are expanded. any time to determine the logic state of a Port pin. DSM or driven internally from the DSM device. rides the Data Out register.

’1.’ The default pin drive is CMOS. ister is set to ’1.’ The default rate is standard slew. See Appendix A for Drive Register bit definitions. DSM2150F5V is configured for 8-bit operation. D15 when configured for 16-bit operation. PLDs are routed directly in and do not use IMCs.

1194.1 JTAG bus for In-System Programming

and Application Note AN1153 . The Enable Out register can be read by the DSP. and the pin is in input mode. Table 13. Port Operating Modes Note: 1. Can be multiplexed with other I/O functions.

1. Only in 8-bit DSP data bus configuration.

1 No No

ECS0) can be connected to Port C. I CPLD Input – Via the Input Macrocells (IMC). configured to Open Drain Mode. Figure 19. Port A, B, and C Structure

some 16-bit DSP connections. Figure 20. Port D Structure

I MCU I/O Mode in 8-bit configuration. Drain Mode in 8-bit configuration. Figure 21. Port E and G Structure

The device offers configurable power saving op- tions. These options may be used individually or in combinations, as follows: – All memory blocks in the device are built with zero-power technology. Zero-power technology puts the memories into Standby Mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an address input, the affected memory “wakes up”, changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve memory Standby Mode when no inputs are changing— it happens automatically. Both PLDs (DPLD and CPLD) are also Zero- power, but this is not the default operation. The DSP must set a bit at run-time to achieve Zero-power as described. – PSD Chip Select Input (CSI , PD2) can be used to disable the internal memories and csiop registers, placing them in Standby Mode even if address inputs are changing. This feature does not block any internal signals or disable the PLDs. There is a slight penalty in memory access time when PSD Chip Select Input (CSI , PD2) makes its initial transition from deselected to selected. – The PMMR registers can be written by the DSP at run-time to manage power. The device has a Turbo Bit in the PMMR0 register. This bit can be set to turn the Turbo Mode off (the default is with Turbo Mode turned on). While Turbo Mode is off, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo Mode is on. When the Turbo Mode is on, there is a significant DC current component and the AC component is higher. – Further significant power savings can be achieved by blocking signals that are not used in DPLD or CPLD logic equations. The “blocking bits” in PMMR registers can be set to logic ’1’ by the DSP to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figure 23., page 51), so blocking unused PLD inputs can significantly lower PLD operating frequency and power consumption. The DSP also has the option of blocking certain PLD inputs when not needed, then letting them pass for when needed for specific logic operations. Table 4., page 13 and Appendix A define the PMMR registers.

shows the timing of the Power-up and warm reset. Figure 22. Reset (RESET) Timing Table 14. Status During Power-on Reset, Warm Reset and Power-down Mode

be completely programmed in 15to 35 seconds. in addition to TMS, TCK, TDI and TDO. the parallel port on any PC or laptop. on a blank device (and as shipped from factory). JTAG In-System Programming (ISP). ditions that are logically ORed. the four pins are enabled for JTAG operation.

1. PSDsoft Express Pin Configuration -OR-
2. PSDsoft Express PLD equation -OR-
3. DSP writes to register in csiop block

Flashlink cable when multiplexing JTAG signals. See Application Note AN1153 for details. cleared, which turns off the JTAG-ISP function. Table 15. JTAG Port Signals

TSTAT and TERR are two JTAG extension signals (must be used as a pair) enabled by a command received over the four standard JTAG signals (TMS, TCK, TDI, and TDO) by PSDsoft Express. They are used to speed Program and Erase cycles by indicating status on device pins instead of hav- ing to scan the status out serially using the stan- dard JTAG channel. See Application Note AN1153. TERR indicates if an error has occurred when erasing a sector or programming a byte in Flash memory. This signal goes Low (active) when an Error condition occurs. TSTAT behaves the same as Ready/Busy de- scribed previously. TSTAT is inactive logic ’1’ when the device is in READ Mode (Flash memory con- tents can be read). TSTAT is logic ’0’ when Flash memory Program or Erase cycles are in progress. TSTAT and TERR can be configured as open- drain type signals with PSDsoft Express. This fa- cilitates a wired-OR connection of TSTAT signals from multiple DSM2150F5V devices and a wired- OR connection of TERR signals from those same devices. This is useful when several devices are “chained” together in a JTAG environment. PSD- soft Express puts TSTAT and TERR signals to open-drain by default. Click on 'Properties' in the JTAG-ISP window of PSDsoft Express to change to standard CMOS push-pull. It is recommended to use 10kΩ pull-up resistors to V CC on all JTAG- ISP signals on your circuit board. INITIAL DELIVERY STATE When delivered from ST, the device has all bits in the memory and PLDs erased to logic ’1.’ The DSM Configuration Register Bits are set to ’0.’ The code, configuration, and PLD logic are loaded us- ing the programming procedure. The four basic JTAG ISP signals (TCK, TMS, TDI, TDO) are ready for ISP function.

Table 16. Absolute Maximum Ratings

Table 17. Operating Conditions Table 18. AC Measurement Conditions Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 24. AC Measurement I/O Waveform Figure 25. AC Measurement Load Circuit Table 19. Capacitance Note: 1. Sampled only, not 100% tested.

1. Typical values are for TA = 25°C and nominal supply voltages.

Figure 26. Switching Waveforms – Key Table 20. AC Symbols for PLD Timing Example:tAVWL – Time from Address Valid to WRITE Input Low.

Table 21. DC Characteristics

1. CSI deselected (CSI >VCC –0.3V) or the DSP is not changing state of any address signal.
2. PLD is in non-Turbo Mode, and none of the PLD inputs are switching.
3. No inputs floating, must be solid logic ’1’ or ’0’ (pull up to VCC or GND, or actively driven)
4. See Figure 23., page 51 for the PLD current calculation.
5. IOUT = 0mA, meaning outputs are driving no loads.

Figure 27. Input to Output Disable / Enable Table 22. CPLD Combinatorial Timing Note: 1. Fast Slew Rate output available on Port C and Port F.

Figure 28. Synchronous Clock Mode Timing – PLD Table 23. CPLD MicroCell Synchronous Clock Mode Timing Note: 1. Fast slew rate output available on Port C and Port F.

1. CLKIN (PD1) tCLCL = tCH + tCL .

Figure 31. Input MicroCell Timing (Product Term Clock) Table 25. Input MicroCell Timing Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD.

Figure 32. READ Timing Table 26. READ Timing Note: 1. Any input used to select an internal DSM function.

Figure 33. WRITE Timing Table 27. WRITE Timing Note: 1. Any input used to select an internal PSM function.

1. Assuming data is stable before active WRITE signal.
2. Assuming WRITE is active before data becomes valid.

WHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal DSM memory.

1. tWHAX_16 is 11ns when writing to the Output Microcells

Table 28. Flash Memory Program, WRITE and Erase Times Note: 1. Programmed to all zero before erase.

1. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.

Figure 34. Reset (RESET) Timing Table 29. Reset (RESET ) Timing Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.

1. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.

Figure 35. ISC Timing Table 30. ISC Timing Note: 1. For non-PLD Programming, Erase or in By-pass Mode.

1. For Program or Erase PLD only.

Figure 36. 80-lead, Plastic, Quad Flatpack, Package Outline Note: Drawing is not to scale.

Table 31. TQFP80 - 80-lead, Plastic, Quad Flatpack, Package Mechanical Data

Table 32. Ordering Information Scheme please contact your nearest ST Sales Office.

Table 33. Connections (Figure 3., page 7)

10 AD5

11 AD6

12 AD7

13 AD8

14 AD9

15 AD10

16 AD11

17 AD12

18 AD13

19 AD14

20 AD15

21 PG0

22 PG1

23 PG2

24 PG3

25 PG4

26 PG5

27 PG6

28 PG7

30 GND

31 PF0

32 PF1

33 PF2

34 PF3

35 PF4

36 PF5

37 PF6

38 PF7

39 RESET

40 CNTL2

61 PB0

62 PB1

63 PB2

64 PB3

65 PB4

66 PB5

67 PB6

68 PB7

70 GND

71 PE0

72 PE1

73 PE2

74 PE3

75 PE4

76 PE5

77 PE6

78 PE7

79 PD0

80 PD1

Table 34. Data-In Registers – Ports A, B, C, D, E, G Read Port pin status when Port is in MCU I/O Input Mode. Table 35. Data-Out Registers – Ports A, B, C, D, E, G Latched data for output to Port pin when pin is configured in MCU I/O Output Mode. Table 36. Direction Registers – Ports A, B, C, D, E, G Port pin <i> 0 = Port pin <i> is configured in Input Mode (default). Port pin <i> 1 = Port pin <i> is configured in Output Mode. Table 37. Drive Registers – Ports A, B, E, G Port pin <i> 0 = Port pin <i> is configured for CMOS Output driver (default). Port pin <i> 1 = Port pin <i> is configured for Open Drain output driver. Table 38. Drive Registers – Port C Port pin <i> 0 = Port pin <i> is configured for CMOS Output driver (default). Port pin <i> 1 = Port pin <i> is configured in Slew Rate Mode. Table 39. Enable-Out Registers – Ports A, B, C Port pin <i> 0 = Port pin <i> is in tri-state driver (default). Port pin <i> 1 = Port pin <i> is enabled. Table 40. Input Macrocells – Ports A, B, C Read Input Macrocell (IMC7-IMC0) status on Ports A, B and C.

Table 41. Output Macrocells A Register Write Register: Load MCellA7-MCellA0 with 0 or 1. Read Register: Read MCellA7-MCellA0 output status. Table 42. Output Macrocells B Register Write Register: Load MCellB7-MCellB0 with 0 or 1. Read Register: Read MCellB7-MCellB0 output status. Table 43. Mask Macrocells A Register McellA<i>_Prot 0 = Allow MCellA<i> flip-flop to be loaded by MCU (default). McellA<i>_Prot 1 = Prevent MCellA<i> flip-flop from being loaded by DSP. Table 44. Mask Macrocells B Register McellB<i>_Prot 0 = Allow MCellB<i> flip-flop to be loaded by MCU (default). McellB<i>_Prot 1 = Prevent MCellB<i> flip-flop from being loaded by DSP. Table 45. Flash Memory Protection Register Sec<i>_Prot 1 = Primary Flash memory Sector <i> is write protected. Sec<i>_Prot 0 = Primary Flash memory Sector <i> is not write protected. Table 46. Flash Boot Protection Register Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected. Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected. Security_Bit 0 = Security Bit in device has not been set. Security_Bit 1 = Security Bit in device has been set. Table 47. JTAG Enable Register JTAGEnable 1 = JTAG Port is enabled. JTAGEnable 0 = JTAG Port is disabled.

Table 48. Page Register Configure Page input to PLD. Default is PGR7-PGR0=0. Table 49. PMMR0 Register Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers. PLD Turbo 0 = PLD Turbo is on. 1 = PLD Turbo is off, saving power. PLD Array CLK 0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off. 1 = CLKIN to the PLD AND array is disconnected, saving power. PLD MCells CLK 0 = CLKIN to the PLD Macrocells is connected. 1 = CLKIN to the PLD Macrocells is disconnected, saving power. Table 50. PMMR2 Register Note: For Bit 4, Bit 3, Bit 2: See Table 49 for the signals that are blocked on pins CNTL0-CNTL2. PLD Array Addr 0 = Address A7-A0 are connected to the PLD array. 1 = Address A7-A0 are blocked from the PLD array, saving power. PLD Array CNTL2 0 = CNTL2 input to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off. 1 = CNTL2 input to the PLD AND array is disconnected, saving power. PLD Array CNTL1 0 = CNTL1 input to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off. 1 = CNTL1 input to the PLD AND array is disconnected, saving power. PLD Array CNTL0 0 = CNTL0 input to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off. 1 = CNTL0 input to the PLD AND array is disconnected, saving power. PLD Array WRH 0 = WRH input to the PLD AND array is connected. 1 = WRH input to the PLD AND array is disconnected, saving power. Table 51. Memory_ID0 Register Table 52. Memory_ID1 Register

REVISION HISTORY

Table 53. Document Revision History

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