DSLVDS1047 TI | Alldatasheet
Document overview
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Technical content
intellectual property matters and other important disclaimers. PRODUCTION DATA.
1 Features
- 3.3-V Power Supply Design
- 300-ps Typical Differential Skew
- 400-ps Maximum Differential Skew
- 1.7-ns Maximum Propagation Delay
- ±350-mV Differential Signaling
- Low Power Dissipation (13 mW at 3.3-V Static)
- Interoperable With Existing 5-V LVDS Receivers
- High impedance on LVDS Outputs on Power Down
- Flow-Through Pinout Simplifies PCB Layout
- Meets or Exceeds TIA/EIA-644 LVDS Standard
- Industrial Operating Temperature Range (−40°C to +85°C)
- Available in TSSOP Package
2 Applications
- Multifunction Printers
- Board-to-Board Communication
- Test and Measurement
- Printers
- Data Center Interconnect
- Lab Instrumentation
- Ultrasound Scanners
3 Description
has a flow-through pinout for easy PCB layout. to-point interface applications. Figure 1. Application Diagram
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12.1 Receiving Notification of Documentation Updates 20
13 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES September 2018 * Initial release.
1EN 16 DOUT1 í 2D IN1 15 DOUT1+ 3D IN2 14 DOUT2+ 4VCC 13 DOUT2 í 5GND 12 DOUT3 í 6D IN3 11 DOUT3+ 7D IN4 10 DOUT4+ 8EN* 9 DOUT4 í Not to scale DSLVDS1047 www.ti.com SNLS623 – SEPTEMBER 2018 Product Folder Links: DSLVDS1047 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated
5 Pin Configuration and Functions
NO. NAME
2 DIN1
I Driver input pin, TTL/CMOS compatible
3 DIN2
6 DIN3
7 DIN4
10 DOUT4+
O Non-inverting driver output pin, LVDS levels
11 DOUT3+
14 DOUT2+
15 DOUT1+
9 DOUT4−
O Inverting driver output pin, LVDS levels
12 DOUT3−
13 DOUT2−
16 DOUT1−
1 EN I
Driver enable pin: When EN is low, the driver is disabled. When EN is high and EN* is low or open, the driver is enabled. If both EN and EN* are open circuit, then the driver is disabled.
8 EN* I
Driver enable pin: When EN* is high, the driver is disabled. When EN* is low or open and EN is high, the driver is enabled. If both EN and EN* are open circuit, then the driver is disabled.
5 GND — Ground pin
4 VCC — Power supply pin, +3.3 V ± 0.3 V
SNLS623 – SEPTEMBER 2018 www.ti.com Product Folder Links: DSLVDS1047 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6 Specifications
6.1 Absolute Maximum Ratings
See (1) MIN MAX UNIT Supply voltage (VCC) −0.3 4 V Input voltage (DIN) −0.3 VCC + 0.3 V Enable input voltage (EN, EN*) −0.3 VCC + 0.3 V Output voltage (DOUT+, DOUT–) −0.3 3.9 V Short-circuit duration (DOUT+, DOUT–) Continuous Maximum package power dissipation at +25°C PW0016A package 866 mW Derate PW0016A package above +25°C 6.9 mW/°C Lead temperature Soldering (4 s) 260 °C Maximum junction temperature 150 °C Storage temperature, Tstg −65 150 °C (1) ESD Ratings: HBM (1.5 kΩ, 100 pF) EIAJ (0 Ω, 200 pF) (2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
V(ESD) Electrostatic discharge(1) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2) ±1200 VCharged-device model (CDM), per JEDEC specification JESD22- C101(3) ±200 Machine Model ±1200
6.3 Recommended Operating Conditions
Supply voltage, VCC 3 3.3 3.6 V Operating free air temperature, TA −40 25 85 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.4 Thermal Information
THERMAL METRIC(1) DSLVDS1047 UNITPW (TSSOP)
16 PINS
RθJA Junction-to-ambient thermal resistance 114 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51 °C/W RθJB Junction-to-board thermal resistance 59 °C/W ψJT Junction-to-top characterization parameter 8 °C/W ψJB Junction-to-board characterization parameter 58 °C/W
www.ti.com SNLS623 – SEPTEMBER 2018 Product Folder Links: DSLVDS1047 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: VOD1 and ΔVOD1. (2) All typicals are given for: VCC = 3.3 V, TA = +25°C. (3) The DSLVDS1047 is a current mode device and only functions within datasheet specifications when a resistive load is applied to the driver outputs typical range is (90 Ω to 110 Ω). (4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
6.5 Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified(1)(2)(3) PARAMETER TEST CONDITIONS PIN MIN TYP MAX UNIT VOD1 Differential output voltage RL = 100 Ω (Figure 18) DOUT− DOUT+ 250 310 450 mV ΔVOD1 Change in magnitude of VOD1 for complementary output states 1 35 |mV| VOS Offset voltage 1.125 1.17 1.375 V ΔVOS Change in magnitude of VOS for complementary output states 1 25 |mV| VOH Output high voltage 1.33 1.6 V VOL Output low voltage 0.9 1.02 V VIH Input high voltage DIN, EN, EN*
2 VCC V
VIL Input low voltage GND 0.8 V IIH Input high current VIN = VCC or 2.5 V 2 15 µA IIL Input low current VIN = GND or 0.4 V 2 15 µA VCL Input clamp voltage ICL = −18 mA −1.5 −0.8 V IOS Output short-circuit current(4) ENABLED, DIN = VCC, DOUT+ = 0 V or DIN = GND, DOUT− = 0 V DOUT− DOUT+ −4 −8 mA IOSD Differential output short-circuit current(4) ENABLED, VOD = 0 V −4.2 −9 mA IOFF Power-off leakage VOUT = 0 V or 3.6 V, VCC = 0 V or Open −20 ±1 20 µA IOZ Output TRI-STATE current EN = 0.8 V and EN* = 2.0 V VOUT = 0 V or VCC −10 ±1 10 µA ICC No load supply current drivers enabled DIN = VCC or GND VCC 4 8 mA ICCL Loaded supply current drivers enabled RL = 100 Ω all channels, DIN = VCC or GND (all inputs) 20 30 mA ICCZ No load supply current drivers disabled DIN = VCC or GND, EN = GND, EN* = VCC 2.2 6 mA
SNLS623 – SEPTEMBER 2018 www.ti.com Product Folder Links: DSLVDS1047 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) All typicals are given for: VCC = 3.3 V, TA = +25°C. (2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns. (3) CL includes probe and jig capacitance. (4) tSKD1 |tPHLD – tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. (5) tSKD2 is the differential channel-to-channel skew of any event on the same device. (6) tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. (7) tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. (8) fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% / 55%, VOD > 250 mV, all channels switching.
6.6 Switching Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPHLD Differential propagation delay high to low RL = 100 Ω, CL = 15 pF (Figure 19 and Figure 20) 0.5 0.9 1.7 ns tPLHD Differential propagation delay low to high 0.5 1.2 1.7 ns tSKD1 Differential pulse skew |tPHLD − tPLHD|(4) 0.3 0.4 ns tSKD2 Channel-to-channel skew(5) 0.4 0.5 ns tSKD3 Differential part-to-part skew(6) 0 1 ns tSKD4 Differential part-to-part skew(7) 0 1.2 ns tTLH Rise time 0.5 1.5 ns tTHL Fall time 0.5 1.5 ns tPHZ Disable time high to Z RL = 100 Ω, CL = 15 pF (Figure 21 and Figure 22) 2 5 ns tPLZ Disable time low to Z 2 5 ns tPZH Enable time Z to high 3 7 ns tPZL Enable time Z to low 3 7 ns fMAX Maximum operating frequency(8) 200 250 MHz
6.7 Typical Characteristics
Figure 2. Output High Voltage vs Power Supply Voltage Figure 3. Output Low Voltage vs Power Supply Voltage Figure 4. Output Short Circuit Current vs Figure 5. Output TRI-STATE Current vs Figure 6. Differential Output Voltage vs Figure 7. Differential Output Voltage vs Load Resistor
Figure 14. Differential Skew vs Ambient Temperature Figure 15. Transition Time vs Power Supply Voltage Figure 16. Transition Time vs Ambient Temperature Figure 17. Data Rate vs Cable Length
7 Parameter Measurement Information
Figure 18. Driver VOD and VOS Test Circuit
Figure 22. Driver TRI-STATE Delay Waveform
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8 Detailed Description
8.1 Overview
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 24. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic differential impedance of the media is in the range of 100 Ω. A termination resistor of 100 Ω (selected to match the media), and is located as close to the receiver input pins as possible. The termination resistor converts the driver output current (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DSLVDS1047 differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The output current is typically 3.1 mA, a minimum of 2.5 mA, and a maximum of 4.5 mA. The current mode driver requires that a resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 24. AC or unterminated configurations are not allowed. The 3.1-mA loop current develops a differential voltage of 310 mV across the 100-Ω termination resistor which the receiver detects with a 250-mV minimum differential noise margin, (driven signal minus receiver threshold (250 mV – 100 mV = 150 mV). The signal is centered around +1.2 V (Driver Offset, VOS) with respect to ground as shown in Figure 23. NOTE The steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 620 mV. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most case from 20 MHz to 50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers. The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required.
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8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 LVDS Fail-Safe
This section addresses the common concern of fail-safe biasing of LVDS interconnects, specifically looking at the DSLVDS1047 driver outputs and the DSLVDS1048 receiver inputs. The LVDS receiver is a high-gain, high-speed device that amplifies a small differential signal (20 mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, take care to prevent noise from appearing as a valid signal. The internal fail-safe circuitry of the receiver is designed to source or sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated, or shorted receiver inputs. 1. Open Input Pins. The DSLVDS1048 is a quad receiver device, and if an application requires only 1, 2, or 3 receivers, the unused channel(s) inputs must be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pullup and pulldown resistors to set the output to a HIGH state. This internal circuitry ensures a HIGH, stable output state for open inputs. 2. Terminated Input. If the DSLVDS1047 driver is disconnected (cable unplugged), or if the DSLVDS1047 driver is in a TRI-STATE or power-off condition, the receiver output is again in a HIGH state, even with the end of cable 100-Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10 mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect must be used. Twisted pair cable offers better balance than flat ribbon cable. 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0-V differential input voltage, the receiver output remains in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (GND to 2.4 V). It is only supported with inputs shorted and no external common-mode voltage applied.
approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry. Figure 23. Driver Output Levels
8.4 Device Functional Modes
Table 1 lists the functional modes DSLVDS1047. Table 1. Truth Table
9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.
9.2 Typical Application
Figure 24. Point-to-Point Application
9.2.1 Design Requirements
impedance of about 100 Ω. They should not introduce major impedance discontinuities. CAT5 (Category 5) twisted pair cable works well, is readily available and relatively inexpensive. Table 2. Design Requirements
9.2.2 Detailed Design Procedure
9.2.2.1 Probing LVDS Transmission Lines
scope. Improper probing gives deceiving results.
9.2.2.2 Data Rate vs Cable Length Graph Test Procedure
Lines and Data Signal Quality (SNLA028).
9.2.3 Application Curve
Figure 25. Power Supply Current vs Frequency
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10 Power Supply Recommendations
Although the DSLVDS1047 draws very little power while at rest. At higher switching frequencies there is a dynamic current component which increases the overall power consumption. The DSLVDS1047 power supply connection must take this additional current consumption into consideration for maximum power requirements.
11 Layout
11.1 Layout Guidelines
- Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals.
- Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).
- Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
11.1.1 Power Decoupling Recommendations
Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended) 0.1-µF and 0.001-µF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Additional scattered capacitors over the printed-circuit board improves decoupling. Multiple vias must be used to connect the decoupling capacitors to the power planes. A 10-µF (35-V) or greater solid tantalum capacitor must be connected at the power entry point on the printed-circuit board between the supply and ground.
11.1.2 Differential Traces
Use controlled impedance traces which match the differential impedance of your transmission medium (that is, cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs must be < 10 mm long). This helps eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1 mm apart radiate far less noise than traces 3 mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals, which destroys the magnetic field cancellation benefits of differential signals and EMI, results. NOTE The velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number or vias and other discontinuities on the line. Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels. Within a pair of traces, the distance between the two traces must be minimized to maintain common-mode rejection of the receivers. On the printed-circuit board, this distance must remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable.
11.1.3 Termination
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor must be between 90 Ω and 130 Ω. Remember that the current mode outputs need the termination resistor to generate the differential voltage. LVDS does not work without resistor termination. Typically, connecting a single resistor across the pair at the receiver end will suffice.
11.2 Layout Example
Figure 26. Layout Recommendation
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DSLVDS1047PWR Active Production TSSOP (PW) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 DSLVDS 1047 DSLVDS1047PWR.B Active Production TSSOP (PW) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 DSLVDS 1047 DSLVDS1047PWT Active Production TSSOP (PW) | 16 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 85 DSLVDS 1047 DSLVDS1047PWT.B Active Production TSSOP (PW) | 16 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 85 DSLVDS 1047 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 9-Aug-2022 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DSLVDS1047PWR TSSOP PW 16 2500 367.0 367.0 35.0 DSLVDS1047PWT TSSOP PW 16 250 210.0 185.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.19 TYP6.6 6.2
1.2 MAX
0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 5.1 4.9 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017
0.1 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9
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