DSD1796DBRG4

DSD1796 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 63

Technical content

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 /C0050/C0052/C0262/C0066/C0073/C0084/C0044 /C0049/C0057/C0050/C0262/C0107/C0072/C0122 /C0083/C0065/C0077/C0080/C0076/C0073/C0078/C0071/C0044 /C0065/C0068/C0086/C0065/C0078/C0067/C0069/C0068 /C0083/C0069/C0071/C0077/C0069/C0078/C0084/C0044 /C0065/C0085/C0068/C0073/C0079 /C0083/C0084/C0069/C0082/C0069/C0079 /C0068/C0073/C0071/C0073/C0084/C0065/C0076/C0262/C0084/C0079/C0262/C0065/C0078/C0065/C0076/C0079/C0071 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006

FEATURES

/C0068Supports Both DSD and PCM Formats /C006824-Bit Resolution /C0068Analog Performance: − Dynamic Range: 123 dB − THD+N: 0.0005% /C0068Differential Current Output: 4 mA p-p /C00688× Oversampling Digital Filter: − Stop-Band Attenuation: –98 dB − Pass-Band Ripple: ±0.0002 dB /C0068Sampling Frequency: 10 kHz to 200 kHz /C0068System Clock: 128, 192, 256, 384, 512, or 768 fS With Autodetect /C0068Accepts 16-, 20-, and 24-Bit Audio Data /C0068PCM Data Formats: Standard, I2S, and Left-Justified /C0068DSD Format Interface Available /C0068Interface Available for Optional External Digital Filter or DSP /C0068TDMCA Interface Available /C0068User-Programmable Mode Controls: − Digital Attenuation: 0 dB to –120 dB, 0.5 dB/Step − Digital De-Emphasis − Digital Filter Rolloff: Sharp or Slow − Soft Mute /C0068Compatible With DSD1792 (Pins and Mode Controls) /C0068Dual Supply Operation: − 5-V Analog, 3.3-V Digital /C00685-V Tolerant Digital Inputs /C0068Small 28-Lead SSOP Package

APPLICATIONS

/C0068A/V Receivers /C0068SACD Players /C0068DVD Players /C0068HDTV Receivers /C0068Car Audio Systems /C0068Digital Multi-Track Recorders /C0068Other Applications Requiring 24-Bit Audio

DESCRIPTION

The DSD1796 is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI’s advanced-segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The DSD1796 provides balanced current outputs, allowing the user to optimize analog performance externally. The DSD1796 accepts the PCM and DSD audio data formats, providing easy interfacing to audio DSP and decoder chips. The DSD1796 also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through an SPI serial control port, which supports register write and readback functions. The DSD1796 also supports the time-division-multiplexed command and audio (TDMCA) data format. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0066/C0117/C0114/C0114/C0262/C0066/C0114/C0111/C0119/C0110 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0102/C0114/C0111/C0109 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 Copyright  2006, Texas Instruments Incorporated

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com

ORDERING INFORMATION

PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA DSD1796DB 28-lead SSOP 28DB –25°C to 85°C DSD1796 DSD1796DB Tube DSD1796DB 28-lead SSOP 28DB –25°C to 85°C DSD1796 DSD1796DBR Tape and reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) DSD1796 Supply voltage VCC 1, VCC 2L, VCC 2R –0.3 V to 6.5 V Supply voltage VDD –0.3 V to 4 V Supply voltage differences: VCC 1, VCC 2L, VCC 2R ±0.1 V Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, DGND ±0.1 V Digital input voltage PLRCK, PDATA, PBCK, SCK, RST, MS(2), MDI, MC, DSDL(2), DSDR(2), DBCK –0.3 V to 6.5 V Digital input voltageDSDL (3), DSDR(3), MS(3), MDO –0.3 V to (VDD + 0.3 V) < 4 V Analog input voltage –0.3 V to (VCC + 0.3 V) < 6.5 V Input current (any pins except supplies) ±10 mA Ambient temperature under bias –40°C to 125°C Storage temperature –55°C to 150°C Junction temperature 150°C Lead temperature (soldering) 260°C, 5 s Package temperature (IR reflow, peak) 260°C (1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2)Input mode (3)Output mode

ELECTRICAL CHARACTERISTICS

all specifications at TA = 25°C, VCC 1 = VCC 2L = VCC 2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted PARAMETER TEST CONDITIONS DSD1796DB UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION 24 Bits DATA FORMAT (PCM Mode) Audio data interface format Standard, I2S, left-justified Audio data bit length 16-, 20-, 24-bit selectable Audio data format MSB first, 2s complement fS Sampling frequency 10 200 kHz System clock frequency 128, 192, 256, 384, 512, 768 fS DATA FORMAT (DSD Mode) Audio data interface format DSD (direct stream digital) Audio data bit length 1 bit fS Sampling frequency 2.8224 MHz System clock frequency 2.8224 11.2896 MHz

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC 1 = VCC 2L = VCC 2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted PARAMETER TEST CONDITIONS DSD1796DB UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic family TTL compatible VIH Input logic level VDCVIL Input logic level 0.8 VDC IIH Input logic current VIN = VDD 10 µAIIL Input logic current VIN = 0 V –10 µA VOH Output logic level IOH = –2 mA 2.4 VDCVOL Output logic level IOL = 2 mA 0.4 VDC IOHZ High-impedance output logic current(1) VOUT = VDD 10 µAIOLZ High-impedance output logic current(1) VOUT = 0 V –10 µA DYNAMIC PERFORMANCE (PCM MODE) (2)(3) fS = 44.1 kHz 0.0005% 0.001% THD+N at VOUT = 0 dB fS = 96 kHz 0.001%THD+N at VOUT = 0 dB fS = 192 kHz 0.0015% EIAJ, A-weighted, fS = 44.1 kHz 120 123 Dynamic range EIAJ, A-weighted, fS = 96 kHz 123 dBDynamic range EIAJ, A-weighted, fS = 192 kHz 123 dB EIAJ, A-weighted, fS = 44.1 kHz 120 123 Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz 123 dBSignal-to-noise ratio EIAJ, A-weighted, fS = 192 kHz 123 dB fS = 44.1 kHz 116 119 Channel separation fS = 96 kHz 118 dBChannel separation fS = 192 kHz 117 dB Level linearity error VOUT = –120 dB ±1 dB DYNAMIC PERFORMANCE (MONO MODE) (2)(3)(4) fS = 44.1 kHz 0.0005% THD+N at VOUT = 0 dB fS = 96 kHz 0.001%THD+N at VOUT = 0 dB fS = 192 kHz 0.0015% EIAJ, A-weighted, fS = 44.1 kHz 126 Dynamic range EIAJ, A-weighted, fS = 96 kHz 126 dBDynamic range EIAJ, A-weighted, fS = 192 kHz 126 dB EIAJ, A-weighted, fS = 44.1 kHz 126 Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz 126 dBSignal-to-noise ratio EIAJ, A-weighted, fS = 192 kHz 126 dB (1)Pin 13 (MDO) (2)Filter condition: THD+N: 20-Hz HPF, 20-kHz AES17 LPF Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Channel separation: 20-Hz HPF, 20-kHz AES17 LPF Analog performance specifications are measured using the System Two Cascade audio measurement system by Audio Precision in the averaging mode. (3)Dynamic performance and DC accuracy are specified at the output of the postamplifier as shown in Figure 32. (4)Dynamic performance and DC accuracy are specified at the output of the measurement circuit as shown in Figure 34. Audio Precision and System Two are trademarks of Audio Precision, Inc. Other trademarks are the property of their respective owners.

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC 1 = VCC 2L = VCC 2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted PARAMETER TEST CONDITIONS DSD1796DB UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT DSD MODE DYNAMIC PERFORMANCE (1) (2) (44.1 kHz, 64 fS) THD+N at FS 2 V rms 0.0007% Dynamic range –60 dB, EIAJ, A-weighted 122 dB Signal-to-noise ratio EIAJ, A-weighted 122 dB ANALOG OUTPUT Gain error –7 ±2 7 % of FSR Gain mismatch, channel-to-channel –3 ±0.5 3 % of FSR Bipolar zero error At BPZ –2 ±0.5 2 % of FSR Output current Full scale (0 dB) 4 mA p-p Center current At BPZ –3.5 mA DIGITAL FILTER PERFORMANCE De-emphasis error ±0.1 dB FILTER CHARACTERISTICS-1: SHARP ROLLOFF Pass band ±0.0002 dB 0.454 fSPass band –3 dB 0.49 fS Stop band 0.546 fS Pass-band ripple ±0.0002 dB Stop-band attenuation Stop band = 0.546 fS –98 dB Delay time 38/fS s FILTER CHARACTERISTICS-2: SLOW ROLLOFF Pass band ±0.001 dB 0.21 fSPass band –3 dB 0.448 fS Stop band 0.79 fS Pass-band ripple ±0.001 dB Stop-band attenuation Stop band = 0.732 fS –80 dB Delay time 38/fS s (1)Filter condition: THD+N: 20-Hz HPF, 20-kHz AES17 LPF Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Channel separation: 20-Hz HPF, 20-kHz AES17 LPF Analog performance specifications are measured using the System Two Cascade audio measurement system by Audio Precision in the averaging mode. (2)Dynamic performance and DC accuracy are specified at the output of the postamplifier as shown in Figure 33.

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC 1 = VCC 2L = VCC 2R = 5 V,, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted PARAMETER TEST CONDITIONS DSD1796DB UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY REQUIREMENTS VDD 3 3.3 3.6 VDC VCC 1 Voltage rangeVCC 2L Voltage range 4.75 5 5.25 VDC VCC 2R (1) fS = 44.1 kHz 7 9 IDD (1) fS = 96 kHz 13 mAIDD Supply current (1) fS = 192 kHz 25 mA Supply current (1) fS = 44.1 kHz 18 23 ICC fS = 96 kHz 19 mAICC fS = 192 kHz 20 mA (1) fS = 44.1 kHz 115 150 Power dissipation (1) fS = 96 kHz 140 mWPower dissipation (1) fS = 192 kHz 180 mW TEMPERATURE RANGE Operation temperature –25 85 °C θJA Thermal resistance 28-pin SSOP 100 °C/W (1)Input is BPZ data. PIN ASSIGNMENTS DSDL DSDR DBCK PLRCK PDATA PBCK SCK DGND VDD MS MDI MC MDO RST VCC 2L AGND3L I OUT L– IOUT L+ AGND2 V CC 1 VCOM L VCOM R IREF AGND1 I OUT R– IOUT R+ AGND3R V CC 2R DSD1796 (TOP VIEW)

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com Terminal Functions TERMINAL I/O DESCRIPTIONSNAME PIN I/O DESCRIPTIONS AGND1 19 – Analog ground (internal bias) AGND2 24 – Analog ground (internal bias) AGND3L 27 – Analog ground (L-channel DACFF) AGND3R 16 – Analog ground (R-channel DACFF) DBCK 3 I Bit clock input for DSD mode (1) DGND 8 – Digital ground DSDL 1 I/O L-channel audio data input for DSD mode PCM mode zero flag for L-channel when in zero-flag output mode(2) DSDR 2 I/O R-channel audio data input for DSD mode PCM mode zero flag for R-channel when in zero-flag output mode (2) IOUT L+ 25 O L-channel analog current output + IOUT L– 26 O L-channel analog current output – IOUT R+ 17 O R-channel analog current output + IOUT R– 18 O R-channel analog current output – IREF 20 – Output current reference bias pin MC 12 I Mode control clock input(1) MDI 11 I Mode control data input (1) MDO 13 O Mode control readback data output (3) MS 10 I/O Mode control chip-select input(2) PBCK 6 I Bit clock input for PCM mode (1) PDATA 5 I Serial audio data input for PCM mode (1) PLRCK 4 I Left and right clock (fS) input for PCM mode (1) RST 14 I Reset(1) SCK 7 I System clock input (1) VCC 1 23 – Analog power supply, 5 V VCC 2L 28 – Analog power supply (L-channel DACFF), 5 V VCC 2R 15 – Analog power supply (R-channel DACFF), 5 V VCOM L 22 – L-channel internal bias decoupling pin VCOM R 21 – R-channel internal bias decoupling pin VDD 9 – Digital power supply, 3.3 V (1)Schmitt-trigger input, 5-V tolerant (2)Schmitt-trigger input and output. 5-V tolerant input, and CMOS output (3)3-state output

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com FUNCTIONAL BLOCK DIAGRAM System Clock Manager Power Supply DBCK DSDL DSDR RST SCK Advanced Segment DAC Modulator IOUT L+ IOUT L– IOUT R– Current Segment DAC IOUT R+ Bias and Vref VCOM L VCOM R AGND2 VDD VCC 1 VCC 2L VCC 2R AGND1 I/V and Filter/C00328 Oversampling Digital Filter and Function Control Audio Data Input I/FPLRCK PBCK PDATA MDO MDI MC MS AGND3L AGND3R DGND Current Segment DAC IREF VOUT L I/V and Filter VOUT R Function Control I/F

or master reset circuit to force the DSD1796 to initialize to its default reset state.

1024 System Clocks

2.4 V (Max)

2 V (Typ)

1.6 V (Min)

Figure 24. Power-On Reset Timing Figure 25. External Reset Timing

between PLRCK and the system clock. timing diagram for the serial audio interface. Figure 26. Timing of Audio Interface

Figure 27. Audio Data Input Formats

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com External Digital Filter Interface and Timing The DSD1796 supports an external digital filter interface comprising a 3- or 4-wire synchronous serial port, which allows the use of an external digital filter. External filters include the Texas Instruments DF1704 and DF1706, the Pacific Microsonics PMD200, or a programmable digital signal processor. In the external DF mode, PLRCK (pin 4), PBCK (pin 6) and PDATA (pin 5) are defined as WDCK, the word clock; BCK, the bit clock; and DATA, the monaural data, respectively. The external digital filter interface is selected by using the DFTH bit of control register 20, which functions to bypass the internal digital filter of the DSD1796. When the DFMS bit of control register 19 is set, the DSD1796 can process stereo data. In this case, DSDL (pin 1) and DSDR (pin 2) are defined as L-channel data and R-channel data input, respectively. Detailed information for the external digital filter interface mode is provided in the APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE section of this data sheet. Direct Stream Digital (DSD) Format Interface and Timing The DSD1796 supports the DSD format interface operation, which includes out-of-band noise filtering using an internal analog FIR filter. The DSD format interface consists of a 3-wire synchronous serial port, which includes DBCK (pin 3), DSDL (pin 1), and DSDR (pin 2). DBCK is the serial bit clock. DSDL and DSDR are the L-channel and R-channel DSD data input, respectively. They are clocked into the DSD1796 on the rising edge of DBCK. PLRCK (pin 4) and PBCK (pin 6) must be connected to GND in the DSD mode. The DSD format (DSD mode) interface is activated by setting the DSD bit of control register 20. Detailed information for the DSD mode is provided in the APPLICA TION FOR DSD FORMAT (DSD MODE) INTERFACE section of this data sheet. TDMCA Interface The DSD1796 supports the time-division-multiplexed command and audio (TDMCA) data format to enable control of and communication with a number of external devices over a single serial interface. Detailed information for the TDMCA format is provided in the TDMCA INTERFACE FORMAT section of this data sheet.

1.4 VMS

Figure 30. Control Interface Timing

conditions and associated register index. Table 2. User-Programmable Function Controls (1)When in DSD mode, DMF[1:0] is defined as DSD filter (analog FIR) performance selection. (2)When in DSD mode, OS[1:0] is defined as DSD filter (analog FIR) operation rate selection.

register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only. Table 3. Mode Control Register Map When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. These bits are available for read and write. Each DAC output has a digital attenuator associated with it. The attenuator can be set from 0 dB to –120 dB, in 0.5-dB steps. Alternatively, the attenuator can be set to infinite attenuation (or mute).

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 18 R/W 0 0 1 0 0 1 0 ATLD FMT2 FMT1 FMT0 DMF1 DMF0 DME MUTE R/W : Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 ATLD: Attenuation Load Control This bit is available for read and write. Default value: 0 ATLD = 0 Attenuation control disabled (default) ATLD = 1 Attenuation control enabled The ATLD bit is used to enable loading of the attenuation data contained in registers 16 and 17. When ATLD = 0, the attenuation settings remain at the previously programmed levels, ignoring new data loaded from registers 16 and 17. When ATLD = 1, attenuation data written to registers 16 and 17 is loaded normally. FMT[2:0]: Audio Interface Data Format These bits are available for read and write. Default value: 101 FMT[2:0] Audio Data Format Selection 000 16-bit standard format, right-justified data 001 20-bit standard format, right-justified data 010 24-bit standard format, right-justified data 011 24-bit MSB-first, left-justified format data 100 16-bit I2S-format data 101 24-bit I2S-format data (default)

110 Reserved

111 Reserved

The FMT[2:0] bits are used to select the data format for the serial audio interface. For the external digital filter interface mode (DFTH mode), this register is operated as shown in the APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE section of this data sheet. DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function These bits are available for read and write. Default value: 00 DMF[1:0] De-Emphasis Sampling Frequency Selection

00 Disabled (default)

10 44.1 kHz 11 32 kHz The DMF[1:0] bits are used to select the sampling frequency used by the digital de-emphasis function when it is enabled by setting the DME bit. The de-emphasis curves are shown in the TYPICAL PERFORMANCE CURVES section of this data sheet. For the DSD mode, analog FIR filter performance can be selected using this register. A register map and filter response plots are shown in the APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE section of this data sheet.

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com DME: Digital De-Emphasis Control This bit is available for read and write. Default value: 0 DME = 0 De-emphasis disabled (default) DME = 1 De-emphasis enabled The DME bit is used to enable or disable the de-emphasis function for both channels. MUTE: Soft Mute Control This bit is available for read and write. Default value: 0 MUTE = 0 Mute disabled (default) MUTE = 1 Mute enabled The MUTE bit is used to enable or disable the soft mute function for both channels. Soft mute is operated as a 256-step attenuator. The speed for each step to –∞ dB (mute) is determined by the attenuation rate selected in the ATS register. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 19R/W 0 0 1 0 0 1 1 REV ATS1 ATS0 OPE ZOE DFMS FLT INZD R/W : Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 REV: Output Phase Reversal This bit is available for read and write. Default value: 0 REV = 0 Normal output (default) REV = 1 Inverted output The REV bit is used to invert the output phase for both channels. ATS[1:0]: Attenuation Rate Select These bits are available for read and write. Default value: 00 ATS[1:0] Attenuation Rate Selection

00 Every PLRCK (default)

01 PLRCK/2

10 PLRCK/4

11 PLRCK/8

The ATS[1:0] bits are used to select the rate at which the attenuator is decremented/incremented during level transitions.

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com OPE: DAC Operation Control This bit is available for read and write. Default value: 0 OPE = 0 DAC operation enabled (default) OPE = 1 DAC operation disabled The OPE bit is used to enable or disable the analog output for both channels. Disabling the analog outputs forces them to the bipolar zero level (BPZ) even if digital audio data is present on the input. ZOE: Zero Flag Pin Operation Control This bit is available for read and write. Default value: 0 ZOE = 0 DSD data input (default) ZOE = 1 Zero flag output The ZOE bit is used to change the DSDL (pin 1) and DSDR (pin 2) pin assignments. When the ZOE bit is set to 0, DSDL and DSDR are inputs for L-channel and R-channel data. When the ZOE bit is set to 1, DSDL and DSDR become outputs for the L-channel and R-channel zero flags, respectively. See the PCMZ and DZ[1:0] bit descriptions of register 21. DFMS: Stereo DF Bypass Mode Select This bit is available for read and write. Default value: 0 DFMS = 0 Monaural (default) DFMS = 1 Stereo input enabled The DFMS bit is used to enable stereo operation in the DF bypass mode. In the DF bypass mode, when DFMS is set to 0, the pin for the input data is PDATA (pin 5) only, therefore the DSD1796 operates as a monaural DAC. When DFMS is set to 1, the DSD1796 can operate as a stereo DAC with inputs of input L-channel and R-channel data on DSDL (pin 1) and DSDR (pin 2), respectively. FLT: Digital Filter Rolloff Control This bit is available for read and write. Default value: 0 FLT = 0 Sharp rolloff (default) FLT = 1 Slow rolloff The FLT bit is used to select the digital filter rolloff characteristic. The filter responses for these selections are shown in the TYPICAL PERFORMANCE CURVES section of this data sheet. INZD: Infinite Zero Detect Mute Control This bit is available for read and write. Default value: 0 INZD = 0 Infinite zero detect mute disabled (default) INZD = 1 Infinite zero detect mute enabled The INZD bit is used to enable or disable the zero detect mute function. Setting INZD to 1 forces muted analog outputs to hold a bipolar zero level when the DSD1796 detects zero data in both channels continuously for 1024 sampling periods (1/fS). The infinite zero detect mute function is not available in the DSD mode.

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 20R/W 0 0 1 0 1 0 0 RSV SRST DSD DFTH MONO CHSL OS1 OS0 R/W : Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 SRST: System Reset Control This bit is available for write only. Default value: 0 SRST = 0 Normal operation (default) SRST = 1 System reset operation (generate one reset pulse) The SRST bit is used to reset the DSD1796 to the initial system condition. DSD: DSD Interface Mode Control This bit is available for read and write. Default value: 0 DSD = 0 DSD interface mode disabled (default) DSD = 1 DSD interface mode enabled The DSD bit is used to enable or disable the DSD interface mode. DFTH: Digital Filter Bypass (or Through Mode) Control This bit is available for read and write. Default value: 0 DFTH = 0 Digital filter enabled (default) DFTH = 1 Digital filter bypassed for external digital filter The DFTH bit is used to enable or disable the external digital filter interface mode. MONO: Monaural Mode Selection This bit is available for read and write. Default value: 0 MONO = 0 Stereo mode (default) MONO = 1 Monaural mode The MONO function is used to change the operation mode from the normal stereo mode to the monaural mode. When the monaural mode is selected, both DACs operate in a balanced mode for one channel of audio input data. Channel selection is available for L-channel or R-channel data, determined by the CHSL bit as described immediately following. CHSL: Channel Selection for Monaural Mode This bit is available for read and write. Default value: 0 CHSL = 0 L-channel selected (default) CHSL = 1 R-channel selected This bit is available when MONO = 1. The CHSL bit selects L-channel or R-channel data to be used in monaural mode.

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com OS[1:0]: Delta-Sigma Oversampling Rate Selection These bits are available for read and write. Default value: 00 OS[1:0] Operation Speed Select 00 64 times fS (default) 01 32 times fS 10 128 times fS

11 Reserved

The OS bits are used to change the oversampling rate of delta-sigma modulation. Use of this function enables the designer to stabilize the conditions at the post low-pass filter for different sampling rates. As an application example, programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, and 32 times in 192-kHz operation allows the use of only a single type (cutoff frequency) of post low-pass filter. The 128-f S oversampling rate is not available at sampling rates above 100 kHz. If the 128-fS oversampling rate is selected, a system clock of more than 256 fS is required. In DSD mode, these bits are used to select the speed of the bit clock for DSD data coming into the analog FIR filter. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 21 R/W 0 0 1 0 1 0 1 RSV RSV RSV RSV RSV DZ1 DZ0 PCMZ R/W : Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 DZ[1:0]: DSD Zero Output Enable These bits are available for read and write. Default value: 00 DZ[1:0] Zero Output Enable

01 Even pattern detect

The DZ bits are used to enable or disable the output zero flags, and to select the zero pattern in the DSD mode. The DSD1796 sets zero flags when the numbers of 1s and 0s are equal in every 8 bits of DSD input data, or the DSD input data is 1001 0110 continuously for 23 ms. PCMZ: PCM Zero Output Enable These bits are available for read and write. Default value: 1 PCMZ = 0 PCM zero output disabled PCMZ = 1 PCM zero output enabled (default) The PCMZ bit is used to enable or disable the output zero flags in the PCM mode and the external DF mode. The DSD1796 sets the zero flags when the input data is continuously zero for 1024 PLRCKs in the PCM mode or 1024 WDCKs in the external filter mode. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 22 R 0 0 1 0 1 1 0 RSV RSV RSV RSV RSV RSV ZFGR ZFGL R: Read Mode Select Value is always 1, specifying the readback mode.

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com ZFGx: Zero-Detection Flag Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback. Default value: 00 ZFGx = 0 Not zero ZFGx = 1 Zero detected When the DSD1796 detects that audio input data is continuously zero, the ZFGx bit is set to 1 for the corresponding channel(s). B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 23 R 0 0 1 0 1 1 1 RSV RSV RSV ID4 ID3 ID2 ID1 ID0 R: Read Mode Select Value is always 1, specifying the readback mode. ID[4:0]: Device ID The ID[4:0] bits hold a device ID in the TDMCA mode.

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com

APPLICATION INFORMATION

TYPICAL CONNECTION DIAGRAM PDATA 24 DSD1796 PBCK SCK DGND VDD MS MDI MC MDO RST AGND2 IOUT R– VCC 1 VCOM L VCOM R IREF IOUT R+ AGND3R AGND1 DSDL1 DSDR DBCK PLRCK VCC 2L AGND3L IOUT L– IOUT L+ DSD Audio Data Source VOUT L-Channe l 5 V VCC 2R 0.1 µF Controller 10 µF 3.3 V PCM Audio Data Source 0.1 µF 10 µF C f R f Differential to Single Converter With Low-Pass Filter 10 kΩ C f R f VOUT R-Channe l C f R f Differential to Single Converter With Low-Pass Filter– C f R f 47 µF 5 V 10 µF 0.1 µF 10 µF

5 V +

Figure 31. Typical Application Circuit is capable. This is because noise and distortion that are generated in an application circuit are not negligible. In the third-order LPF circuit of Figure 32, the output level is 2.1 V rms and 123 dB S/N is achieved. Figure 33 shows a circuit for the DSD mode, which is a fourth-order LPF in order to reduce the out-of-band noise. The current of the DSD1796 on each of the output pins (IOUT L+, IOUT L–, IOUT R+, IOUT R–) is 4 mA p-p at 0 dB (full scale). performance of the I/V section. channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-pass filter function. The operational amplifier recommended for the differential circuit is the low-noise type.

Figure 32. Measurement Circuit for PCM

Figure 33. Measurement Circuit for DSD

Figure 35. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com Application for Interfacing With an External Digital Filter For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as it can provide improved stop-band attenuation when compared to the internal digital filter of the DSD1796. The DSD1796 supports several external digital filters, including: /C0068Texas Instruments DF1704 and DF1706 /C0068Pacific Microsonics PMD200 HDCD filter/decoder IC /C0068Programmable digital signal processors The external digital filter application mode is accessed by programming the following bit in the corresponding control register: /C0068DFTH = 1 (register 20) The pins used to provide the serial interface for the external digital filter are shown in the connection diagram of Figure 35. The word clock (WDCK) signal must be operated at 8× or 4× the desired sampling frequency, f Pin Assignment When Using the External Digital Filter Interface /C0068PLRCK (pin 4): WDCK as word clock input /C0068PBCK (pin 6): BCK as bit clock for audio data /C0068PDATA (pin 5): DATA as monaural audio data input when the DFMS bit is not set to 1 /C0068DSDL (pin 1): DATAL as L-channel audio data input when the DFMS bit is set to 1 /C0068DSDR (pin 2): DATAR as R-channel audio data input when the DFMS bit is set to 1

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com Functions Available in the External Digital Filter Mode The external digital filter mode is selected by setting DSD = 0 (register 20, B5) and DFTH = 1 (register 20. B4). The external digital filter mode allows access to the majority of the DSD1796 mode control functions. The following table shows the register mapping available when the external digital filter mode is selected, along with descriptions of functions which are modified when using this mode selection. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 16 R/W 0 0 1 0 0 0 0 – – – – – – – – Register 17 R/W 0 0 1 0 0 0 1 – – – – – – – – Register 18 R/W 0 0 1 0 0 1 0 – FMT2 FMT1 FMT0 – – – – Register 19 R/W 0 0 1 0 0 1 1 REV – – OPE – DFMS – INZD Register 20 R/W 0 0 1 0 1 0 0 – SRST 0 1 MONO CHSL OS1 OS0 Register 21 R/W 0 0 1 0 1 0 1 – – – – – – – PCMZ Register 22 R 0 0 1 0 1 1 0 – – – – – – ZFGR ZFGL NOTE : –: Function is disabled. No operation even if data bit is set FMT[2:0]: Audio Data Format Selection Default value: 000 FMT[2:0] Audio Data Format Select 000 16-bit right-justified format (default) 001 20-bit right-justified format 010 24-bit right-justified format Other N/A OS[1:0]: Delta-Sigma Modulator Oversampling Rate Selection Default value: 00 OS[1:0] Operation Speed Select 00 8 times WDCK (default) 01 4 times WDCK 10 16 times WDCK The effective oversampling rate is determined by the oversampling performed by both the external digital filter and the delta-sigma modulator. For example, if the external digital filter is 8× oversampling, and the user selects OS[1:0] = 00, then the delta-sigma modulator oversamples by 8×, resulting in an effective oversampling rate of 64×. The 16× WDCK oversampling rate is not available above a 100-kHz sampling rate. If the oversampling rate selected is 16× WDCK, the system clock frequency must be over 256 fS.

(1)The system clock can be removed after setting the register to the DSD mode. Figure 38. Connection Diagram in DSD Mode This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CD/C0116 (SACD) applications. The DSD mode is accessed by programming the following bit in the corresponding control register. responses are available, and are selected by the DMF[1:0] bits of control register 18. commands are not accepted through the serial control interface. Super Audio CD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan.

/C0068/C0083/C0068/C0049/C0055/C0057/C0054 SLES101A – DECEMBER 2003 – REVISED NOVEMBER 2006 www.ti.com DSD MODE CONFIGURATION AND FUNCTION CONTROLS Configuration for the DSD Interface Mode The DSD interface mode is selected by setting DSD = 1 (register 20, B5). B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 16 R/W 0 0 1 0 0 0 0 – – – – – – – – Register 17 R/W 0 0 1 0 0 0 1 – – – – – – – – Register 18 R/W 0 0 1 0 0 1 0 – – – – DMF1 DMF0 – – Register 19 R/W 0 0 1 0 0 1 1 REV – – OPE – – – – Register 20 R/W 0 0 1 0 1 0 0 – SRST 1 – MONO CHSL OS1 OS0 Register 21 R 0 0 1 0 1 0 1 – – – – – DZ1 DZ0 – Register 22 R 0 0 1 0 1 1 0 – – – – – – ZFGR ZFGL NOTE : –: Function is disabled. No operation even if data bit is set DMF[1:0]: Analog FIR Performance Selection Default value: 00 DMF[1:0] Analog-FIR Performance Select

00 FIR-1 (default)

01 FIR-2

10 FIR-3

11 FIR-4

Plots for the four analog FIR filter responses are shown in the ANALOG FIR FILTER PERFORMANCE IN DSD MODE section of this data sheet. OS[1:0]: Analog-FIR Operation-Speed Selection Default value: 00 OS[1:0] Operation Speed Select 00 fDBCK (default) 01 fDBCK /2

10 Reserved

The OS bit in the DSD mode is used to select the operating rate of the analog FIR. The OS bits must be set before setting the DSD bit to 1.

serial interface. The TDMCA format is designed not only for the McBSP of TI DSPs but also for any programmable devices. maximum number of audio channels depends on the BCK frequency. frames. Any TDMCA commands can be issued during the next TDMCA frame after the TDMCA mode is entered.

2 BCK

Figure 49. LRCK and BCK Timing for Determination of TDMCA Mode be connected directly to other devices. Table 4. TDMCA Terminal Descriptions PLRCK LRCK I TDMCA frame start signal. It must be the same as the sampling frequency. PBCK BCK I TDMCA clock. Its frequency must be high enough to communicate a TDMCA frame within an LRCK cycle.

simultaneously support several TDMCA devices, which can be of the same type or different types, including PCM devices. IN device. For the host controller to distinguish the devices, each device is assigned its own device ID by the daisy chain.

• • •
• • •
• • •
• • •
• • •

Figure 50. Daisy Chain Connection

Figure 51. IN Daisy Chain and OUT Daisy Chain Connection for a Multichip System

58 BCKs

Figure 52. Device ID Determination Sequence packets are not transferred, the analog outputs are unpredictable.

32 Bits

Figure 53. General TDMCA Frame

7 Packets × 32 Bits

Figure 54. TDMCA Frame Example of 6-Ch DAC and 2-Ch ADC With Command Read determination, and all remaining bits in the field are ignored. The DSD1796 operates to get its own device ID for TDMCA initialization if this bit is HIGH. data. This is for system initialization. The device ID is 5 bits length, and it can be defined.These bits identify the order of a device in the IN or OUT daisy chain. If this bit is HIGH, the command is a read operation. It is 8 bits in length. Any valid data can be chosen for each register. These bits are never transported when a read operation is performed. The extended command field is the same as the command field, except that it does not have a DID flag.

as shown in the following example. mode control register map (Table 3). delay caused by high impedance. Figure 55 shows the TDMCA write and read timing.

1 BCK Early

Figure 55. TDMCA Write and Read Operation Timing device. Therefore, DCI means the next audio channel is allocated. ac timing of the daisy chain signals.

9 Packets × 32 Bits

Figure 56. DCO Output Timing of TDMCA Mode Operation

14 BCK Delay

2 BCK Delay

5 Packets × 32 Bits

Figure 57. DCO Output Timing With Skip Operation

Figure 58. DCO Output Timing With Skip Operation (for Command Packet 1)

(1)Load capacitance is 10 pF. Figure 59. AC Timing of Daisy Chain Signals

Table 5 and Figure 60 show the relationship between the digital input code and analog output. Table 5. Analog Output Current and Voltage measurement circuit of Figure 32. Figure 60. The Relationship Between Digital Input and Analog Output

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DSD1796DB ACTIVE SSOP DB 28 47 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DSD1796DBG4 ACTIVE SSOP DB 28 47 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DSD1796DBR ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DSD1796DBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2007 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DSD1796DBR SSOP DB 28 2000 336.6 336.6 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 Pack Materials-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DSD1796DB Active Production SSOP (DB) | 28 47 | TUBE Yes Call TI | Nipdau Level-1-260C-UNLIM -25 to -40 DSD1796 DSD1796DB.B Active Production SSOP (DB) | 28 47 | TUBE Yes NIPDAU Level-1-260C-UNLIM -25 to -40 DSD1796 DSD1796DBR Active Production SSOP (DB) | 28 2000 | LARGE T&R Yes Call TI | Nipdau Level-1-260C-UNLIM -25 to -40 DSD1796 DSD1796DBR.B Active Production SSOP (DB) | 28 2000 | LARGE T&R Yes Call TI Level-1-260C-UNLIM -25 to -40 DSD1796 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DSD1796DBR SSOP DB 28 2000 356.0 356.0 35.0 DSD1796DBR SSOP DB 28 2000 336.6 336.6 28.6 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DSD1796DB DB SSOP 28 47 500 10.6 500 9.6 DSD1796DB DB SSOP 28 47 530 10.5 4000 4.1 DSD1796DB DB SSOP 28 47 530 10.5 4000 4.1 DSD1796DB.B DB SSOP 28 47 530 10.5 4000 4.1 DSD1796DB.B DB SSOP 28 47 500 10.6 500 9.6 DSD1796DB.B DB SSOP 28 47 530 10.5 4000 4.1 DSD1796DBR DB SSOP 28 2000 500 10.6 500 9.6 DSD1796DBR.B DB SSOP 28 2000 500 10.6 500 9.6 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 26X 0.65 8.45 28X 0.38 0.22 8.2

7.4 TYP

0.05 MIN

0.25 GAGE PLANE 0 -8

2 MAX

B 5.6 5.0 NOTE 4 A 10.5 9.9 NOTE 3 0.95 0.55 (0.15) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018

0.15 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. A 15 DETAIL A TYPICAL SCALE 1.500

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

28X (1.85) 28X (0.45) 26X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 14 15 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 28X (1.85) 28X (0.45) 26X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 14 15

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated