DSD1794ADBR

DSD1794A TI | Alldatasheet

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Technical content

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 /C0050/C0052/C0262/C0066/C0073/C0084/C0044 /C0049/C0057/C0050/C0262/C0107/C0072/C0122 /C0083/C0065/C0077/C0080/C0076/C0073/C0078/C0071/C0044 /C0065/C0068/C0086/C0065/C0078/C0067/C0069/C0068 /C0083/C0069/C0071/C0077/C0069/C0078/C0084/C0044 /C0065/C0085/C0068/C0073/C0079 /C0083/C0084/C0069/C0082/C0069/C0079 /C0068/C0073/C0071/C0073/C0084/C0065/C0076/C0262/C0084/C0079/C0262/C0065/C0078/C0065/C0076/C0079/C0071 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082

FEATURES

/C0068Supports Both DSD and PCM Formats /C006824-Bit Resolution /C0068Analog Performance: − Dynamic Range: − 132 dB (9 V RMS, Mono) − 129 dB (4.5 V RMS, Stereo) − 127 dB (2 V RMS, Stereo) − THD+N: 0.0004% /C0068Differential Current Output: 7.8 mA p-p /C00688× Oversampling Digital Filter: − Stop-Band Attenuation: –130 dB − Pass-Band Ripple: ±0.00001 dB /C0068Sampling Frequency: 10 kHz to 200 kHz /C0068System Clock: 128, 192, 256, 384, 512, or 768 fS With Autodetect /C0068Accepts 16-, 20-, and 24-Bit Audio Data /C0068PCM Data Formats: Standard, I2S, and Left-Justified /C0068Optional Interface to External Digital Filter or DSP Available /C0068I2C-Compatible Serial Port /C0068User-Programmable Mode Controls: − Digital Attenuation: 0 dB to –120 dB, 0.5 dB/Step − Digital De-Emphasis − Digital Filter Rolloff: Sharp or Slow − Soft Mute /C0068Dual-Supply Operation: − 5-V Analog, 3.3-V Digital /C00685-V Tolerant Digital Inputs /C0068Small 28-Lead SSOP Package

APPLICATIONS

/C0068A/V Receivers /C0068SACD Player /C0068DVD Players /C0068HDTV Receivers /C0068Car Audio Systems /C0068Digital Multitrack Recorders /C0068Other Applications Requiring 24-Bit Audio

DESCRIPTION

The DSD1794A is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI’s advanced-segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The DSD1794A provides balanced current outputs, allowing the user to optimize analog performance externally. The DSD1794A accepts the PCM and DSD audio data formats, providing easy interfacing to audio DSP and decoder chips. The DSD1794A also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through an I 2C-compatible serial port. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0066/C0117/C0114/C0114/C0262/C0066/C0114/C0111/C0119/C0110 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0102/C0114/C0111/C0109 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 Copyright  2006, Texas Instruments Incorporated

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 www.ti.com

ORDERING INFORMATION

DSD1794ADB 28-lead SSOP 28DB –25°C to 85°C DSD1794A DSD1794ADB Tube DSD1794ADB 28-lead SSOP 28DB –25°C to 85°C DSD1794A DSD1794ADBR Tape and reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) DSD1794A Supply voltage VCC 1, VCC 2L, VCC 2R –0.3 V to 6.5 V Supply voltage VDD –0.3 V to 4 V Supply voltage differences: VCC 1, VCC 2L, VCC 2R ±0.1 V Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, DGND ±0.1 V Digital input voltage PLRCK, PDATA, PBCK, SCK, RST, SCL, SDA(2), ADR0, ADR1, DSDL(2), DSDR(2), DBCK –0.3 V to 6.5 V Digital input voltage DSDL (3), DSDR(3), SDA(3) –0.3 V to (VDD + 0.3 V) < 4 V Analog input voltage –0.3 V to (VCC + 0.3 V) < 6.5 V Input current (any pins except supplies) ±10 mA Ambient temperature under bias –40°C to 125°C Storage temperature –55°C to 150°C Junction temperature 150°C Lead temperature (soldering) 260°C, 5 s Package temperature (IR reflow, peak) 250°C (1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2)Input mode (3)Output mode

ELECTRICAL CHARACTERISTICS

all specifications at TA = 25°C, VCC 1 = VCC 2L = VCC 2R = 5 V, VDD = 3.3. V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS DSD1794ADB UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION 24 Bits DATA FORMAT (PCM Mode) Audio data interface format Standard, I2S, left justified Audio data bit length 16-, 20-, 24-bit selectable Audio data format MSB first, 2s complement fS Sampling frequency 10 200 kHz System clock frequency 128, 192, 256, 384, 512, 768 fS DATA FORMAT (DSD Mode) Audio data interface format DSD (direct stream digital) Audio data bit length 1 bit fS Sampling frequency 2.8224 MHz System clock frequency 2.8224 11.2896 MHz

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 www.ti.com ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC 1 = VCC 2L = VCC 2R = 5 V, VDD = 3.3. V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS DSD1794ADB UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic family TTL compatible VIH Input logic level VDCVIL Input logic level 0.8 VDC IIH Input logic current VIN = VDD 10 µAIIL Input logic current VIN = 0 V –10 µA VOH Output logic level IOH = –2 mA 2.4 VDCVOL Output logic level IOL = 2 mA 0.4 VDC DYNAMIC PERFORMANCE (PCM MODE, 2-V RMS OUTPUT) (1)(2) fS = 44.1 kHz 0.0004% 0.0008% THD+N at VOUT = 0 dB fS = 96 kHz 0.0008%THD+N at VOUT = 0 dB fS = 192 kHz 0.0015% EIAJ, A-weighted, fS = 44.1 kHz 123 127 Dynamic range EIAJ, A-weighted, fS = 96 kHz 127 dBDynamic range EIAJ, A-weighted, fS = 192 kHz 127 dB EIAJ, A-weighted, fS = 44.1 kHz 123 127 Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz 127 dBSignal-to-noise ratio EIAJ, A-weighted, fS = 192 kHz 127 dB fS = 44.1 kHz 120 123 Channel separation fS = 96 kHz 122 dBChannel separation fS = 192 kHz 120 dB Level linearity error VOUT = –120 dB ±1 dB DYNAMIC PERFORMANCE (PCM Mode, 4.5-V RMS Output) (1)(3) fS = 44.1 kHz 0.0004% THD+N at VOUT = 0 dB fS = 96 kHz 0.0008%THD+N at VOUT = 0 dB fS = 192 kHz 0.0015% EIAJ, A-weighted, fS = 44.1 kHz 129 Dynamic range EIAJ, A-weighted, fS = 96 kHz 129 dBDynamic range EIAJ, A-weighted, fS = 192 kHz 129 dB EIAJ, A-weighted, fS = 44.1 kHz 129 Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz 129 dBSignal-to-noise ratio EIAJ, A-weighted, fS = 192 kHz 129 dB fS = 44.1 kHz 124 Channel separation fS = 96 kHz 123 dBChannel separation fS = 192 kHz 121 dB (1)Filter condition: THD+N: 20-Hz HPF, 20-kHz apogee LPF Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Channel separation: 20-Hz HPF, 20-kHz AES17 LPF Analog performance specifications are measured using the System Two/C0116 Cascade audio measurement system by Audio Precision in the averaging mode. (2)Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 33. (3)Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 34. Audio Precision and System Two are trademarks of Audio Precision, Inc. Other trademarks are the property of their respective owners.

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 www.ti.com ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC 1 = VCC 2L = VCC 2R = 5 V, VDD = 3.3. V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS DSD1794ADB UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE (MONO MODE) (1)(2) fS = 44.1 kHz 0.0004% THD+N at VOUT = 0 dB fS = 96 kHz 0.0008%THD+N at VOUT = 0 dB fS = 192 kHz 0.0015% EIAJ, A-weighted, fS = 44.1 kHz 132 Dynamic range EIAJ, A-weighted, fS = 96 kHz 132 dBDynamic range EIAJ, A-weighted, fS = 192 kHz 132 dB EIAJ, A-weighted, fS = 44.1 kHz 132 Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz 132 dBSignal-to-noise ratio EIAJ, A-weighted, fS = 192 kHz 132 dB DSD MODE DYNAMIC PERFORMANCE (1) (3) (44.1 kHz, 64 fS) THD+N at FS 4.5 V rms 0.0005% Dynamic range –60 dB, EIAJ, A-weighted 128 dB Signal-to-noise ratio EIAJ, A-weighted 128 dB ANALOG OUTPUT Gain error –6 ±2 6 % of FSR Gain mismatch, channel-to-channel –3 ±0.5 3 % of FSR Bipolar zero error At BPZ –2 ±0.5 2 % of FSR Output current Full scale (0 dB) 7.8 mA p-p Center current At BPZ –6.2 mA DIGITAL FILTER PERFORMANCE De-emphasis error ±0.004 dB FILTER CHARACTERISTICS-1: SHARP ROLLOFF Pass band ±0.00001 dB 0.454 fSPass band –3 dB 0.49 fS Stop band 0.546 fS Pass-band ripple ±0.00001 dB Stop-band attenuation Stop band = 0.546 fS –130 dB Delay time 55/fS s FILTER CHARACTERISTICS-2: SLOW ROLLOFF Pass band ±0.04 dB 0.254 fSPass band –3 dB 0.46 fS Stop band 0.732 fS Pass-band ripple ±0.001 dB Stop-band attenuation Stop band = 0.732 fS –100 dB Delay time 18/fS s (1)Filter condition: THD+N: 20-Hz HPF, 20-kHz apogee LPF Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF, A-weighted Channel separation: 20-Hz HPF, 20-kHz AES17 LPF Analog performance specifications are measured using the System Two Cascade audio measurement system by Audio Precision in the averaging mode. (2)Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 34. (3)Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 35.

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 www.ti.com Terminal Functions TERMINAL I/O DESCRIPTIONSNAME PIN I/O DESCRIPTIONS ADR0 10 I I2C address 0 (1) ADR1 11 I I2C address 1 (1) AGND1 19 – Analog ground (internal bias) AGND2 24 – Analog ground (internal bias) AGND3L 27 – Analog ground (L-channel DACFF) AGND3R 16 – Analog ground (R-channel DACFF) DBCK 3 I Bit clock input for DSD modes (1) DGND 8 – Digital ground DSDL 1 I/O L-channel audio data input when in DSD and external DF modes PCM-mode zero flag for L-channel when in zero-flag output mode (2) DSDR 2 I/O R-channel audio data input when in DSD and external DF modes (2) PCM-mode zero flag for R-channel when in zero-flag output mode IOUT L+ 25 O L-channel analog current output + IOUT L– 26 O L-channel analog current output – IOUT R+ 17 O R-channel analog current output + IOUT R– 18 O R-channel analog current output – IREF 20 – Output current reference bias pin PBCK 6 I Bit clock input. Connected to GND in DSD mode (1) PDATA 5 I Serial audio data input for PCM-format operation (1) PLRCK 4 I Left and right clock (fS) input for PCM-format operation. WDCK clock input for external DF mode. Connected to GND for DSD mode (1) RST 14 I Reset (1) SCL 12 I I2C clock (1) SCK 7 I System clock input (1) SDA 13 I/O I2C data (3) VCC 1 23 – Analog power supply, 5 V VCC 2L 28 – Analog power supply (L-channel DACFF), 5 V VCC 2R 15 – Analog power supply (R-channel DACFF), 5 V VCOM L 22 – L-channel internal bias decoupling pin VCOM R 21 – R-channel internal bias decoupling pin VDD 9 – Digital power supply, 3.3 V (1)Schmitt-trigger input, 5-V tolerant (2)Schmitt-trigger input and output. 5-V tolerant input, and CMOS output (3)Schmitt-trigger 5-V tolerant input and open-drain/3-state output

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 www.ti.com FUNCTIONAL BLOCK DIAGRAM System Clock Manager Power Supply DBCK DSDL DSDR RST SCK Advanced Segment DAC Modulator IOUT L+ IOUT L– IOUT R– Current Segment DAC IOUT R+ Bias and Vref VCOM L VCOM R AGND2 VDD VCC 1 VCC 2L VCC 2R AGND1 I/V and Filter/C00328 Oversampling Digital Filter and Function Control Audio Data Input I/FPLRCK PBCK PDATA SDA SCL ADR0 ADR1 AGND3L AGND3R DGND Current Segment DAC IREF VOUT L I/V and Filter VOUT R Function Control I/F

1024 System Clocks

2.4 V (Max)

2 V (Typ)

1.6 V (Min)

Figure 25. Power-On Reset Timing Figure 26. External Reset Timing

relation between PLRCK and the system clock. audio data. Figure 27 shows a detailed timing diagram for the serial audio interface. Figure 27. Timing of Audio Interface

Figure 28. Audio Data Input Formats

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 www.ti.com External Digital Filter Interface and Timing The DSD1794A supports an external digital filter interface with a 3- or 4-wire synchronous serial port, which allows the use of an external digital filter. External filters include the Texas Instruments DF1704 and DF1706, the Pacific Microsonics PMD200, or a programmable digital signal processor. In the external DF mode, PLRCK (pin 4), PBCK (pin 6) and PDATA (pin 5) are defined as WDCK, the word clock; BCK, the bit clock; and DATA, the monaural data, respectively. The external digital filter interface is selected by using the DFTH bit of control register 20, which functions to bypass the internal digital filter of the DSD1794A. When the DFMS bit of control register 19 is set, the DSD1794A can process stereo data. In this case, DSDL (pin 1) and DSDR (pin 2) are defined as L-channel data and R-channel data input, respectively. Detailed information for the external digital filter interface mode is provided in the APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACE section of this data sheet. Direct Stream Digital (DSD) Format Interface and Timing The DSD1794A supports the DSD-format interface operation, which includes out-of-band noise filtering using an internal analog FIR filter. The DSD-format interface consists of a 3-wire synchronous serial port, which includes DBCK (pin 3), DSDL (pin 1), and DSDR (pin 2). DBCK is the serial bit clock. DSDL and DSDR are the L-channel and R-channel DSD data inputs, respectively. They are clocked into the DSD1794A on the rising edge of DBCK. PLRCK (pin 4) and PBCK (pin 6) are connected to GND in the DSD mode. The DSD-format interface is activated by setting the DSD bit of control register 20. Detailed information for the DSD mode is provided in the APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE section of this data sheet. SERIAL CONTROL INTERFACE (I 2C) The DSD1794A supports the I2C serial bus and the data transmission protocol for standard and fast mode as a slave device. This protocol is explained in I2C specification 2.0. Slave Address MSB LSB 1 0 0 1 1 ADR1 ADR0 R/W The DSD1794A has 7 bits for its own slave address. The first five bits (MSBs) of the slave address are factory preset to 10011. The next two bits of the address byte are the device select bits which can be user-defined by the ADR1 and ADR0 terminals. A maximum of four DSD1794As can be connected on the same bus at one time. Each DSD1794A responds when it receives its own slave address. Packet Protocol A master device must control packet protocol, which consists of start condition, slave address, read/write bit, data if write or acknowledge if read, and stop condition. The DSD1794A supports only slave receivers and slave transmitters.

NOTE: The slave address after the repeat start condition must be the same as the previous slave address. Figure 31. Read Operation mode. However, it works incorrectly in the following conditions.

t(SCK) > 120 ns (t(SCK): period of SCK)
Spike noise exists on the first half of the SCL HIGH pulse.
Spike noise exists on the SDA HIGH pulse just before SDA goes LOW.

When these conditions occur at the same time, the data is recognized as LOW.

Spike noise exists on both SCL and SDA during the hold time.

When these conditions occur at the same time, the DSD1794A fails to detect a start condition.

Spike noise exists on SCL just after SCL goes LOW.
Spike noise exists on SDA just before SCL goes LOW.

When these conditions occur at the same time, the DSD1794A erroneously detects a start or stop condition.

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 www.ti.com TIMING DIAGRAM SDA SCL t(BUF) t(D-SU) t(D-HD) Start t(LOW) t(S-HD) t(SCL-F) t(SCL-R) t(HI) Repeated Start t(RS-SU) t(RS-HD) t(SDA-F) t(SDA-R) t(P-SU) Stop t(SP) TIMING CHARACTERISTICS PARAMETER CONDITIONS MIN MAX UNIT f(SCL) SCL clock frequency Standard 100 kHzf(SCL) SCL clock frequency Fast 400 kHz t(BUF) Bus free time between stop and start conditions Standard 4.7 µst(BUF) Bus free time between stop and start conditions Fast 1.3 µs t(LOW) Low period of the SCL clock Standard 4.7 µst(LOW) Low period of the SCL clock Fast 1.3 µs t(HI) High period of the SCL clock Standard 4 µs t(HI) High period of the SCL clock Fast 600 ns t(RS-SU) Setup time for (repeated) start condition Standard 4.7 µs t(RS-SU) Setup time for (repeated) start condition Fast 600 ns t(S-HD) Hold time for (repeated) start condition Standard 4 µs t(RS-HD) Hold time for (repeated) start condition Fast 600 ns t(D-SU) Data setup time Standard 250 nst(D-SU) Data setup time Fast 100 ns t(D-HD) Data hold time Standard 0 900 nst(D-HD) Data hold time Fast 0 900 ns t(SCL-R) Rise time of SCL signal Standard 20 + 0.1 CB 1000 nst(SCL-R) Rise time of SCL signal Fast 20 + 0.1 CB 300 ns t(SCL-R1) Rise time of SCL signal after a repeated start condition and after anStandard 20 + 0.1 CB 1000 nst(SCL-R1) Rise time of SCL signal after a repeated start condition and after an acknowledge bit Fast 20 + 0.1 CB 300 ns t(SCL-F) Fall time of SCL signal Standard 20 + 0.1 CB 1000 nst(SCL-F) Fall time of SCL signal Fast 20 + 0.1 CB 300 ns t(SDA-R) Rise time of SDA signal Standard 20 + 0.1 CB 1000 nst(SDA-R) Rise time of SDA signal Fast 20 + 0.1 CB 300 ns t(SDA-F) Fall time of SDA signal Standard 20 + 0.1 CB 1000 nst(SDA-F) Fall time of SDA signal Fast 20 + 0.1 CB 300 ns t(P-SU) Setup time for stop condition Standard 4 µs t(P-SU) Setup time for stop condition Fast 600 ns C (B) Capacitive load for SDA and SCL line 400 pF t(SP) Pulse duration of suppressed spike Fast 50 ns VNH Noise margin at high level for each connected device (including hysteresis) Standard VNH Noise margin at high level for each connected device (including hysteresis)Fast 0.2 VDD V

The DSD1794A includes a number of user-programmable functions which are accessed via mode control registers. conditions and associated register index. Table 2. User-Programmable Function Controls (1)When in DSD mode, DMF[1:0] is defined as DSD filter (analog FIR) performance selection. (2)When in DSD mode, OS[1:0] is defined as DSD filter (analog FIR) operation rate selection.

a register read (R/W = 1) or write (R/W = 0) operation is performed. Register 22 is read-only. Table 3. Mode Control Register Map When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. These bits are available for read and write. steps. Alternatively, the attenuator can be set to infinite attenuation (or mute). Table 4. Digital Attenuation Levels

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 www.ti.com B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 18 R/W 0 0 1 0 0 1 0 ATLD FMT2 FMT1 FMT0 DMF1 DMF0 DME MUTE R/W : Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 ATLD: Attenuation Load Control This bit is available for read and write. Default value: 0 ATLD = 0 Attenuation control disabled (default) ATLD = 1 Attenuation control enabled The ATLD bit is used to enable loading of the attenuation data contained in registers 16 and 17. When ATLD = 0, the attenuation settings remain at the previously programmed levels, ignoring new data loaded from registers 16 and 17. When ATLD = 1, attenuation data written to registers 16 and 17 is loaded normally. FMT[2:0]: Audio Interface Data Format These bits are available for read and write. Default value: 101 For the external digital filter interface mode (DFTH mode), this register is operated as shown in the Application for Interfacing With an External Digital Filter section of this data sheet. FMT[2:0] Audio Data Format Selection 000 16-bit standard format, right-justified data 001 20-bit standard format, right-justified data 010 24-bit standard format, right-justified data 011 24-bit MSB-first, left-justified format data 100 16-bit I2S-format data 101 24-bit I2S-format data (default)

110 Reserved

111 Reserved

The FMT[2:0] bits are used to select the data format for the serial audio interface. DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function These bits are available for read and write. Default value: 00 DMF[1:0] De-Emphasis Sampling Frequency Selection

00 Disabled (default)

10 44.1 kHz 11 32 kHz The DMF[1:0] bits are used to select the sampling frequency used by the digital de-emphasis function when it is enabled by setting the DME bit. The de-emphasis curves are shown in the TYPICAL PERFORMANCE CURVES section of this data sheet. For the DSD mode, analog FIR filter performance can be selected using this register. A register map and filter response plots are shown in the APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE section of this data sheet.

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 www.ti.com DME: Digital De-Emphasis Control This bit is available for read and write. Default value: 0 DME = 0 De-emphasis disabled (default) DME = 1 De-emphasis enabled The DME bit is used to enable or disable the de-emphasis function for both channels. MUTE: Soft Mute Control This bit is available for read and write. Default value: 0 MUTE = 0 MUTE disabled (default) MUTE = 1 MUTE enabled The MUTE bit is used to enable or disable the soft mute function for both channels. Soft mute is operated as a 256-step attenuator. The speed for each step to –∞ dB (mute) is determined by the attenuation rate selected in the ATS register. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 19R/W 0 0 1 0 0 1 1 REV ATS1 ATS0 OPE ZOE DFMS FLT INZD R/W : Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 REV: Output Phase Reversal This bit is available for read and write. Default value: 0 REV = 0 Normal output (default) REV = 1 Inverted output The REV bit is used to invert the output phase for both channels. ATS[1:0]: Attenuation Rate Select These bits are available for read and write. Default value: 00 ATS[1:0] Attenuation Rate Selection

00 Every PLRCK (default)

01 PLRCK/2

10 PLRCK/4

11 PLRCK/8

The ATS[1:0] bits are used to select the rate at which the attenuator is decremented/incremented during level transitions.

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 www.ti.com OPE: DAC Operation Control This bit is available for read and write. Default value: 0 OPE = 0 DAC operation enabled (default) OPE = 1 DAC operation disabled The OPE bit is used to enable or disable the analog output for both channels. Disabling the analog outputs forces them to the bipolar zero level (BPZ) even if digital audio data is present on the input. ZOE: Zero Flag Pin Operation Control This bit is available for read and write. Default value: 0 ZOE = 0 DSD data input (default) ZOE = 1 Zero flag output The ZOE bit is used to change the DSDL (pin 1) and DSDR (pin 2) pin assignments. When the ZOE bit is set to 0, DSDL and DSDR are inputs for L-channel and R-channel data. When the ZOE bit is set to 1, DSDL and DSDR become outputs for the L-channel and R-channel zero flags, respectively. See the PCMZ and DZ[1:0] bit descriptions of register 21. DFMS: Stereo DF Bypass Mode Select This bit is available for read and write. Default value: 0 DFMS = 0 Monaural (default) DFMS = 1 Stereo input enabled The DFMS bit is used to enable stereo operation in DF bypass mode. In the DF bypass mode, when DFMS is set to 0, the pin for the input data is PDATA (pin 5) only, therefore the DSD1794A operates as a monaural DAC. When DFMS is set to 1, the DSD1794A can operate as a stereo DAC with inputs of L-channel and R-channel data on DSDL (pin 1) and DSDR (pin 2), respectively. FLT: Digital Filter Rolloff Control This bit is available for read and write. Default value: 0 FLT = 0 Sharp rolloff (default) FLT = 1 Slow rolloff The FLT bit is used to select the digital filter rolloff characteristic. The filter responses for these selections are shown in the TYPICAL PERFORMANCE CURVES section of this data sheet. INZD: Infinite Zero Detect Mute Control This bit is available for read and write. Default value: 0 INZD = 0 Infinite zero detect mute disabled (default) INZD = 1 Infinite zero detect mute enabled The INZD bit is used to enable or disable the zero detect mute function. Setting INZD to 1 forces muted analog outputs to hold a bipolar zero level when the DSD1794A detects zero data in both channels continuously for 1024 sampling periods (1/f S). The infinite zero detect mute function does not work in the DSD mode.

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 www.ti.com B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 20R/W 0 0 1 0 1 0 0 RSV SRST DSD DFTH MONO CHSL OS1 OS0 R/W : Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 SRST: System Reset Control This bit is available for write only. Default value: 0 SRST = 0 Normal operation (default) SRST = 1 System reset operation (generate one reset pulse) The SRST bit is used to reset the DSD1794A to the initial system condition. DSD: DSD Interface Mode Control This bit is available for read and write. Default value: 0 DSD = 0 DSD interface mode disabled (default) DSD = 1 DSD interface mode enabled The DSD bit is used to enable or disable the DSD interface mode. DFTH: Digital Filter Bypass (or Through Mode) Control This bit is available for read and write. Default value: 0 DFTH = 0 Digital filter enabled (default) DFTH = 1 Digital filter bypassed for external digital filter The DFTH bit is used to enable or disable the external digital filter interface mode. MONO: Monaural Mode Selection This bit is available for read and write. Default value: 0 MONO = 0 Stereo mode (default) MONO = 1 Monaural mode The MONO function is used to change the operation mode from the normal stereo mode to the monaural mode. When the monaural mode is selected, both DACs operate in a balanced mode for one channel of audio input data. Channel selection is available for L-channel or R-channel data, determined by the CHSL bit as described immediately following. CHSL: Channel Selection for Monaural Mode This bit is available for read and write. Default value: 0 This bit is available when MONO = 1. CHSL = 0 L-channel selected (default) CHSL = 1 R-channel selected The CHSL bit selects L-channel or R-channel data to be used in monaural mode.

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 www.ti.com OS[1:0]: Delta-Sigma Oversampling Rate Selection These bits are available for read and write. Default value: 00 OS[1:0] Operation Speed Select 00 64 times fS (default) 01 32 times fS 10 128 times fS

11 Reserved

The OS bits are used to change the oversampling rate of delta-sigma modulation. Use of this function enables the designer to stabilize the conditions at the post low-pass filter for different sampling rates. As an application example, programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, and 32 times in 192-kHz operation allows the use of only a single type (cutoff frequency) of post low-pass filter. The 128-fS oversampling rate is not available at sampling rates above 100 kHz. If the 128-fS oversampling rate is selected, a system clock of more than 256 fS is required. In DSD mode, these bits are used to select the speed of the bit clock for DSD data coming into the analog FIR filter. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 21 R/W 0 0 1 0 1 0 1 RSV RSV RSV RSV RSV DZ1 DZ0 PCMZ R/W : Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 DZ[1:0]: DSD Zero Output Enable These bits are available for read and write. Default value: 00 DZ[1:0] Zero Output Enable

01 Even pattern detect

The DZ bits are used to enable or disable the output zero flags, and to select the zero pattern in the DSD mode. The DSD1794A sets zero flags when the number of 1s and 0s are equal in every 8 bits of DSD input data, or the DSD input data is 1001 0110 continuously for 200 ms. PCMZ: PCM Zero Output Enable These bits are available for read and write. Default value: 1 PCMZ = 0 PCM zero output disabled PCMZ = 1 PCM zero output enabled (default) The PCMZ bit is used to enable or disable the output zero flags in the PCM mode and the external DF mode. The DSD1794A sets the zero flags when the input data is continuously zero for 1024 LRCKs in the PCM mode or 1024 WDCKs in the external filter mode. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 22 R 0 0 1 0 1 1 0 RSV RSV RSV RSV RSV RSV ZFGR ZFGL

Value is always 1, specifying the readback mode. Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback. Figure 32. Typical Application Circuit

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 www.ti.com

APPLICATION INFORMATION

The design of the application circuit is very important in order to actually realize the high S/N ratio of which the DSD1794A is capable. This is because noise and distortion that are generated in an application circuit are not negligible. In the circuit of Figure 33, the output level is 2 V RMS and 127 dB S/N is achieved. The circuit of Figure 34 can realize the highest performance. In this case the output level is set to 4.5 V rms and 129 dB S/N is achieved (stereo mode). In monaural mode, if the output of the L-channel and R-channel is used as a balanced output, 132 dB S/N is achieved (see Figure 36). Figure 35 shows a circuit for the DSD mode, which is a 4 th-order LPF in order to reduce the out-of-band noise. I/V Section The current of the DSD1794A on each of the output pins (I OUT L+, IOUT L–, IOUT R+, IOUT R–) is 7.8 mA p-p at 0 dB (full scale). The voltage output level of the I/V converter (Vi) is given by following equation: Vi = 7.8 mA p-p × Rf (Rf: feedback resistance of I/V converter) An NE5534 operational amplifier is recommended for the I/V circuit to obtain the specified performance. Dynamic performance such as the gain bandwidth, settling time, and slew rate of the operational amplifier affects the audio dynamic performance of the I/V section. Differential Section The DSD1794A voltage outputs are followed by differential amplifier stages, which sum the differential signals for each channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-pass filter function. The operational amplifier recommended for the differential circuit is the Linear Technology LT1028, because its input noise is low.

Figure 33. Measurement Circuit for PCM, VOUT = 2 V RMS

Figure 34. Measurement Circuit for PCM, VOUT = 4.5 V RMS

Figure 35. Measurement Circuit for DSD

Figure 39. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) Application The external digital filter mode allows access to the majority of the DSD1794A mode control functions. descriptions of functions which are modified when using this mode selection. NOTE: 1 indicates that the bit is required for selection of external digital filter mode.

OS[1:0] = 00, then the delta-sigma modulator oversamples by 8×, resulting in an effective oversampling rate of 64×. is 16× WDCK, the system clock frequency must be over 256 fS. (1)The system clock is necessary for the initilaization sequence and the I2C interface operation. Figure 40. Connection Diagram in DSD Mode This mode is used for interfacing directly to a DSD decoder, which is found in Super Audio CD/C0116 (SACD) applications. The DSD mode is accessed by programming the following bit in the corresponding control register. selected by the DMF[1:0] bits of control register 18. and commands are not accepted through the serial control interface. Super Audio CD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation, Japan.

/C0068/C0083/C0068/C0049/C0055/C0057/C0052/C0065 SLES116A − AUGUST 2004 − REVISED NOVEMBER 2006 www.ti.com DSD MODE CONFIGURATION AND FUNCTION CONTROLS Configuration for the DSD Interface Mode DSD = 1 (Register 20, B5) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 16 R/W 0 0 1 0 0 0 0 – – – – – – – – Register 17 R/W 0 0 1 0 0 0 1 – – – – – – – – Register 18 R/W 0 0 1 0 0 1 0 – – – – DMF1 DMF0 – – Register 19 R/W 0 0 1 0 0 1 1 REV – – OPE – – – – Register 20 R/W 0 0 1 0 1 0 0 – SRST 1 – MONO CHSL OS1 OS0 Register 21 R 0 0 1 0 1 0 1 – – – – – DZ1 DZ0 – Register 22 R 0 0 1 0 1 1 0 – – – – – – ZFGR ZFGL NOTE: – indicates that function is disabled. No operation even if data bit is set DMF[1:0]: Analog FIR Performance Selection Default value: 00 DMF[1:0] Analog-FIR Performance Select

00 FIR-1 (default)

01 FIR-2

10 FIR-3

11 FIR-4

Plots for the four analog FIR filter responses are shown in the TYPICAL PERFORMANCE CURVES section of this data sheet. OS[1:0]: Analog-FIR Operation-Speed Selection Default value: 00 OS[1:0] Operation Speed Select 00 fDBCK (default) 01 fDBCK /2

10 Reserved

The OS bit in the DSD mode is used to select the operating rate of the analog FIR. The OS bits must be set before setting the DSD bit to 1. Requirements for System Clock The bit clock (DBCK) for the DSD mode is required at pin 3 of the DSD1794A. The frequency of the bit clock can be N times the sampling frequency. Generally, N is 64 in DSD applications. The interface timing between the bit clock and DSDL and DSDR is required to meet the same setup-and hold-time specifications as shown in Figure 42.

24 Bits

6 Bits ICOB

Figure 51. Advanced Segment DAC improved tolerance to clock jitter. The DSD1794A provides balanced current outputs. converted to an analog output in the differential-current segment section. excellent dynamic performance.

The following table and Figure 52 show the relationship between the digital input code and analog output. application circuit of Figure 33. Figure 52. The Relationship Between Digital Input and Analog Output

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) DSD1794ADB ACTIVE SSOP DB 28 47 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DSD1794ADBG4 ACTIVE SSOP DB 28 47 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DSD1794ADBR ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DSD1794ADBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 7-May-2007 Addendum-Page 1

TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant DSD1794ADBR DB 28 SITE 49 330 17 8.5 10.8 2.4 12 16 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Sep-2007 Pack Materials-Page 1

Device Package Pins Site Length (mm) Width (mm) Height (mm) DSD1794ADBR DB 28 SITE 49 0.0 0.0 0.0 PACKAGE MATERIALS INFORMATION www.ti.com 21-Sep-2007 Pack Materials-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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Summary

24-BIT,192-kHz SAMPLING, ADVANCED SEGMENT, AUDIO STEREO DIGITAL-TO-ANALOG CONVERTER

Description