DSD1608 BURR-BROWN | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 41
Technical content
SLES040 – JUNE 2002 8-CHANNEL, ENHANCED MULTIFORMAT, DELTA-SIGMA, DIGITAL-TO-ANALOG CONVERTER
FEATURES
/C0068Supports DSD and PCM Formats /C0068Supports TDMCA /C0068Accepts 16-, 18-, 20- and 24-Bit Audio Data for PCM Format /C0068Analog Performance (VCC = 5 V): – Dynamic Range: 108 dB, Typical – SNR: 108 dB, Typical – THD+N: 0.0012%, Typical – Full-Scale Output: 4 Vpp, Typical /C0068Includes 8× Oversampling Digital Filter for PCM Format: – Stopband Attenuation: –60 dB – Passband Ripple: ±0.02 dB /C0068Includes Digital DSD FILTER for DSD Format: – Passband: 50 kHz, 70 kHz, 60 kHz at –3 dB /C0068Sampling Frequency: – PCM Mode: 10 kHz to 200 kHz – DSD Mode: 64 × 44.1 kHz /C0068System Clock: – 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS /C0068Data Formats: – Standard, I2S, and Left-Justified for PCM Direct Stream Digital /C0068User-Programmable Mode Controls: – Digital Attenuation – Digital De-Emphasis – Digital Filter Rolloff: Sharp or Slow Soft Mute – Three Zero Flags /C0068Dual Supply Operation: – 5-V Analog, 3.3-V Digital /C0068Package: 52-Pin TQFP
APPLICATIONS
/C0068Universal A/V Players /C0068SACD Players /C0068Car Audio Systems /C0068Other Applications Requiring 24-Bit Audio
DESCRIPTION
The DSD1608 is a CMOS, monolithic, 8-channel digital-to-analog converter which supports both PCM audio data format and direct stream digital (DSD) audio data format. The device includes an 8× digital interpolation filter and a digital DSD filter with three selectable frequency-response curves, followed by Texas Instruments’ enhanced multilevel delta-sigma modulator, which employs 4th-order noise shaping and 8-level amplitude quantization to achieve excellent dynamic performance and improved tolerance to clock jitter. Sampling rates up to 192 kHz for the PCM mode and 64 × 44.1 kHz for the DSD mode are supported. A full set of user-programmable functions is accessible through a 4-wire serial control port, which supports register write and read functions. The DSD1608 supports the time-division-multiplexed command and audio data (TDMCA) format. The DSD1608 is available in a 52-pin TQFP package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
SLES040 – JUNE 2002 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
DSD1608P AH 52 l d TQFP PAH 25°Ct 8 5°C DSD1608 DSD1608P AH Tube DSD1608P AH 52-lead TQFP PAH –25°C to 85°C DSD1608 DSD1608P AHR Tape and reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) DSD1608 Supply voltage VCC 1–VCC 7 6.5 V Supply voltage VDD 1, VDD 2 4 V Supply voltage differences: VCC 1–VCC 7, VDD 1, VDD 2 ±0.1 V Ground voltage differences: AGND1–6, DGND1, DGND2 ±0.1 V Digital input voltage: PLRCK, PBCK, PDATA1–PDATA4, DSD1 –DSD8, DBCK, DSCK, PSCK, RST –0.3 V to 6.5 V Digital input voltage: MC, MS, MDI, ZERO1, ZERO2, ZERO38, MDO –0.3 V to (VDD + 0.3 V) Analog input voltage –0.3 V to (VCC + 0.3 V) Input current (any pins except supplies) ±10 mA Operating temperature –40°C to 85°C Storage temperature –55°C to 150°C Junction temperature 150°C Lead temperature (soldering) 260°C, 5 s Package temperature (IR reflow, peak) 235°C, 10 s (1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
at TA = 25°C, VDD = 3.3 V, VCC = 5 V; in PCM mode, fS = 44.1 kHz, system clock = 256 fS, 24-bit data; in DSD mode, fS = 2.8224 MHz (= 64 × 44.1 kHz), system clock = 256 × 44.1 kHz, 1-bit data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 24 Bits DATA FORMAT (PCM MODE) Audio data interface format Standard, I2S, left justified Audio data bit length 16-, 18-, 20-, 24-bit selectable Audio data format MSB first, 2s complement fS Sampling frequency fS = 44.1 kHz 10 200 kHz System clock frequency 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS DATA FORMAT (DSD MODE) Audio data interface format Direct stream digital (DSD) Audio data bit length 1 bit fS Sampling frequency fS = 44.1 kHz 64 fS Hz System clock frequency fS = 44.1 kHz 256 fS, 384 fS, 512 fS, 768 fS kHz (1)Pins 50, 51, 34, 33, 37, 38–45, 46–49: PBCK, PLRCK, DSCK, PSCK, DBCK, DSD1–DSD8, PDATA1 –PDATA4. (2)Pins 2, 3, 4, 36: MDI, MS, MC, RST. (3)Pins 5–8: MDO, ZERO1, ZERO2, ZERO38. (4)Analog performance specs are measured in the averaging mode using the System Two/C0116 audio measurement system by Audio Precision/C0116. (5)These specs are measured under the condition that the OVR1, OVR0 in mode registers are set to (0,1). (The oversampling rate of the modulator is 64 fS.) If the OVR1, OVR0 are (0,0) (32 fS oversampling: default), the specs are the same as at fS = 96 kHz.
SLES040 – JUNE 2002 www.ti.com ELECTRICAL CHARACTERISTICS(continued) at TA = 25°C, VDD = 3.3 V, VCC = 5 V; in PCM mode, fS = 44.1 kHz, system clock = 256 fS, 24-bit data; in DSD mode, fS = 2.8224 MHz (= 64 × 44.1 kHz), system clock = 256 × 44.1 kHz, 1-bit data (unless otherwise noted) PARAMETER UNITMAXTYPMINTEST CONDITIONS DIGITAL INPUT/OUTPUT Logic family TTL-compatible VIH Input logic level VdcVIL Input logic level 0.8 Vdc IIH(1) VIN = VDD 10 IIL(1) Input logic current VIN = 0 V –10 µAIIH(2) Input logic current VIN = VDD 65 100 µA IIL(2) VIN = 0 V –10 VOH (3) Output logic level IOH = –2 mA 2.4 VdcVOL (3) Output logic level IOL = +2 mA 1 Vdc DYNAMIC PERFORMANCE (4) (PCM MODE) fS = 44.1 kHz 0.0012% THD+N at VOUT = 0 dB fS = 96 kHz 0.0015%THD+N at VOUT 0 dB fS = 192 kHz(5) 0.002% fS = 44.1 kHz 0.0012% 0.0018% THD+N at VOUT = –3 dB fS = 96 kHz 0.0015%THD+N at VOUT 3 dB fS = 192 kHz(5) 0.002% EIAJ, A-weighted, fS = 44.1 kHz 104 108 Dynamic range EIAJ, A-weighted, fS = 96 kHz 108 dBDynamic range EIAJ, A-weighted, fS = 192 kHz(5) 107 dB EIAJ, A-weighted, fS = 44.1 kHz 104 108 Signal-to-noise ratio EIAJ, A-weighted, fS = 96 kHz 108 dBSignal to noise ratio EIAJ, A-weighted, fS = 192 kHz(5) 107 dB fS = 44.1 kHz 101 104 Channel separation fS = 96 kHz 104 dBChannel se aration fS = 192 kHz(5) 103 dB Level linearity error VOUT = –90 dB ±0.5 dB DYNAMIC PERFORMANCE (4) DSD MODE (at fS = 64 × 44.1 kHz) THD+N at VOUT = 0 dB 0.0012% Dynamic range EIAJ, A-weighted 108 dB Signal-to-noise ratio EIAJ, A-weighted 108 dB Channel separation 104 dB Level linearity error VOUT = –90 dB ±0.5 dB DC ACCURACY Gain error ±1 ±6 % FSR Gain mismatch, channel-to-channel ±1 ±3 % FSR Bipolar zero error V OUT = 0.5 VCC at BPZ ±30 ±60 mV ANALOG OUTPUT Output voltage Full scale (0 dB) 80% of VCC Vpp Center voltage 50% of VCC Vdc Load impedance AC load 4 kΩ (1)Pins 50, 51, 34, 33, 37, 38–45, 46–49: PBCK, PLRCK, DSCK, PSCK, DBCK, DSD1–DSD8, PDATA1 –PDATA4. (2)Pins 2, 3, 4, 36: MDI, MS, MC, RST. (3)Pins 5–8: MDO, ZERO1, ZERO2, ZERO38. (4)Analog performance specs are measured in the averaging mode using the System Two/C0116 audio measurement system by Audio Precision/C0116. (5)These specs are measured under the condition that the OVR1, OVR0 in mode registers are set to (0,1). (The oversampling rate of the modulator is 64 fS.) If the OVR1, OVR0 are (0,0) (32 fS oversampling: default), the specs are the same as at fS = 96 kHz.
SLES040 – JUNE 2002 www.ti.com ELECTRICAL CHARACTERISTICS(continued) at TA = 25°C, VDD = 3.3 V, VCC = 5 V; in PCM mode, fS = 44.1 kHz, system clock = 256 fS, 24-bit data; in DSD mode, fS = 2.8224 MHz (= 64 × 44.1 kHz), system clock = 256 × 44.1 kHz, 1-bit data (unless otherwise noted) PARAMETER UNITMAXTYPMINTEST CONDITIONS DIGITAL FILTER PERFORMANCE 8× INTERPOLATION FILTER (SHARP ROLL OFF FILTER) Pass band ±0.02 dB 0.454 fS Hz Pass band –3 dB 0.487 fS Hz Stop band 0.546 fS Hz Pass-band ripple ±0.02 dB Stop-band attenuation Stop band = 0.546 fS –60 dB Delay Time 23/fS s 8× INTERPOLATION FILTER (SLOW ROLL OFF FILTER) Pass band –0.5 dB 0.308 fS Hz Pass band –3 dB 0.432 fS Hz Stop band 0.832 fS Hz Pass-band ripple 0.308 fS ±0.5 dB Stop-band attenuation 0.832 fS –58 dB Delay time 23/fS s DE-EMPHASIS FILTER (PCM MODE ONLY) De-emphasis error At fS = 32 kHz, 44.1 kHz or 48 kHz ±0.1 dB DSD FILTER (FILTER-1) Pass band At –3 dB 50 kHz Stop-band attenuation At 100 kHz –18 dB DSD FILTER (FILTER-2) Pass band At –3 dB 70 kHz Stop-band attenuation At 100 kHz –9.8 dB DSD FILTER (FILTER-3) Pass band At –3 dB 60 kHz Stop-band attenuation At 100 kHz –17 dB INTERNAL ANALOG FILTER PERFORMANCE At 20 kHz –0.02 Frequency response At 44 kHz –0.1 dBFrequency response At 50 kHz –0.12 dB At 100 kHz –0.5 POWER SUPPLY REQUIREMENTS VDD Voltagerange 3 3.3 3.6 VdcVCC Voltage range 4.5 5.0 5.5 Vdc fS = 44.1 kHz 28 40 IDD fS = 192 kHz 74IDD Supply current DSD mode 45 mA ICC Su ly current fS = 44.1 kHz 36 50 mA ICC fS = 192 kHz 38 Powerdissipation fS = 44.1 kHz 270 380 mWPower dissipation fS = 192 kHz 430 mW (1)Pins 50, 51, 34, 33, 37, 38–45, 46–49: PBCK, PLRCK, DSCK, PSCK, DBCK, DSD1–DSD8, PDATA1 –PDATA4. (2)Pins 2, 3, 4, 36: MDI, MS, MC, RST. (3)Pins 5–8: MDO, ZERO1, ZERO2, ZERO38. (4)Analog performance specs are measured in the averaging mode using the System Two/C0116 audio measurement system by Audio Precision/C0116. (5)These specs are measured under the condition that the OVR1, OVR0 in mode registers are set to (0,1). (The oversampling rate of the modulator is 64 fS.) If the OVR1, OVR0 are (0,0) (32 fS oversampling: default), the specs are the same as at fS = 96 kHz.
SLES040 – JUNE 2002 www.ti.com ELECTRICAL CHARACTERISTICS(continued) at TA = 25°C, VDD = 3.3 V, VCC = 5 V; in PCM mode, fS = 44.1 kHz, system clock = 256 fS, 24-bit data; in DSD mode, fS = 2.8224 MHz (= 64 × 44.1 kHz), system clock = 256 × 44.1 kHz, 1-bit data (unless otherwise noted) PARAMETER UNITMAXTYPMINTEST CONDITIONS TEMPERATURE RANGE Operating temperature –25 85 °C θJA Thermal resistance 52 TQFP 70 °C/W (1)Pins 50, 51, 34, 33, 37, 38–45, 46–49: PBCK, PLRCK, DSCK, PSCK, DBCK, DSD1–DSD8, PDATA1 –PDATA4. (2)Pins 2, 3, 4, 36: MDI, MS, MC, RST. (3)Pins 5–8: MDO, ZERO1, ZERO2, ZERO38. (4)Analog performance specs are measured in the averaging mode using the System Two/C0116 audio measurement system by Audio Precision/C0116. (5)These specs are measured under the condition that the OVR1, OVR0 in mode registers are set to (0,1). (The oversampling rate of the modulator is 64 fS.) If the OVR1, OVR0 are (0,0) (32 fS oversampling: default), the specs are the same as at fS = 96 kHz. PIN ASSIGNMENTS VCOM 2 VCC 7 VCC 6 AGND5 VCC 5 AGND4 VCC 4 AGND3 V CC 3 AGND2 VCC 2 VCC 1 VCOM 1 DSD3 DSD4 DSD5 DSD6 DSD7 DSD8 PDATA1 PDATA2 PDATA3 PDATA4 PBCK PLRCK V DD 1 PAH PACKAGE (TOP VIEW) DGND1 MDI MS MC MDO ZERO1 ZERO2 ZERO38 VOUT 4 VOUT 3 VOUT 2 VOUT 1 AGND1 DSD2 DSD1 DBCK RST VDD 2 DSCK PSCK DGND2 V OUT 5 VOUT 6 VOUT 7 VOUT 8 AGND6 DSD1608 Audio Precision and System Two are trademarks of Audio Precision, Inc. Other trademarks are the property of their respective owners.
SLES040 – JUNE 2002 www.ti.com Terminal Functions TERMINAL I/O DESCRIPTIONNAME NO. I/O DESCRIPTION AGND1 13 — Analog ground AGND2 17 — Analog ground AGND3 19 — Analog ground AGND4 21 — Analog ground AGND5 23 — Analog ground AGND6 27 — Analog ground DBCK 37 I DSD audio data bit clock input (DSD) (3) DGND1 1 — Digital ground DGND2 32 — Digital ground DSCK 34 I System clock input (DSD). Input frequency is 256, 384, 512 or 768 fS (3) DSD1 38 I DSD audio data input for VOUT 1 (DSD) (3) DSD2 39 I DSD audio data input for VOUT 2 (DSD) (3) DSD3 40 I DSD audio data input for VOUT 3 (DSD) (3) DSD4 41 I DSD audio data input for VOUT 4 (DSD) (3) DSD5 42 I DSD audio data input for VOUT 5 (DSD) (3) DSD6 43 I DSD audio data input for VOUT 6 (DSD) (3) DSD7 44 I DSD audio data input for VOUT 7 (DSD) (3) DSD8 45 I DSD audio data input for VOUT 8 (DSD) (3) MC 4 I Mode control clock input (1) MDI 2 I Mode control data input (1) MDO 5 O Mode control read back data output (4) MS 3 I Chip select for mode control (1) PBCK 50 I Audio data bit clock input (PCM) (3) PDATA1 46 I Serial audio data input for VOUT 1 and VOUT 2 (PCM) (3) PDATA2 47 I Serial audio data input for VOUT 3 and VOUT 4 (PCM) (3) PDATA3 48 I Serial audio data input for VOUT 5 and VOUT 6 (PCM) (3) PDATA4 49 I Serial audio data input for VOUT 7 and VOUT 8 (PCM) (3) PLRCK 51 I Audio data L/R clock input (PCM) (3) PSCK 33 I System clock input (PCM). Input frequency is 128, 192, 256, 384, 512 or 768 fS (3) RST 36 I System reset, active LOW (2) VCC 1 15 — Analog power supply, 5 V VCC 2 16 — Analog power supply, 5 V VCC 3 18 — Analog power supply, 5 V VCC 4 20 — Analog power supply, 5 V VCC 5 22 — Analog power supply, 5 V VCC 6 24 — Analog power supply, 5 V VCC 7 25 — Analog power supply, 5 V VCOM 1 14 O Common voltage output 1. This pin should be bypassed with a 10-µF capacitor to AGND. (1)Schmitt-trigger input with internal pulldown. (2)Schmitt-trigger input with internal pulldown, 5-V tolerant. (3)Schmitt-trigger input, 5-V tolerant. (4)3-state output.
SLES040 – JUNE 2002 www.ti.com Terminal Functions (continued) TERMINAL DESCRIPTIONI/ONAME DESCRIPTIONI/ONO. VCOM 2 26 O Common voltage output 2. This pin should be bypassed with a 10-µF capacitor to AGND. VDD 1 52 — Digital power supply, 3.3 V VDD 2 35 — Digital power supply, 3.3 V VOUT 1 12 O Voltage output for audio signal corresponding to L-channel on PDATA1 or DSD1 VOUT 2 11 O Voltage output for audio signal corresponding to R-channel on PDATA1 or DSD2 VOUT 3 10 O Voltage output for audio signal corresponding to L-channel on PDATA2 or DSD3 VOUT 4 9 O Voltage output for audio signal corresponding to R-channel on PDATA2 or DSD4 VOUT 5 31 O Voltage output for audio signal corresponding to L-channel on PDATA3 or DSD5 VOUT 6 30 O Voltage output for audio signal corresponding to R-channel on PDATA3 or DSD6 VOUT 7 29 O Voltage output for audio signal corresponding to L-channel on PDATA4 or DSD7 VOUT 8 28 O Voltage output for audio signal corresponding to R-channel on PDATA4 or DSD8 ZERO1 6 O Zero data flag for VOUT 1 ZERO2 7 O Zero data flag for VOUT 2 ZERO38 8 O Zero data flag for VOUT 3–VOUT 8 (1)Schmitt-trigger input with internal pulldown. (2)Schmitt-trigger input with internal pulldown, 5-V tolerant. (3)Schmitt-trigger input, 5-V tolerant. (4)3-state output.
SLES040 – JUNE 2002 www.ti.com BLOCK DIAGRAM Output Amp and Low-Pass Filter System Clock Enhanced Multilevel Delta-Sigma Modulator DAC Zero Detect Power Supply DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter DAC Output Amp and Low-Pass Filter VOUT 3 ZERO2 VOUT 4 VOUT 5 VOUT 6 Output Amp and Low-Pass FilterDAC VOUT 2 Output Amp and Low-Pass FilterDAC VOUT 1 VOUT 8 VOUT 7 VDD 1, 2 VCC 1–7 DGND1, 2 AGND1 –6 ZERO1 ZERO38 System Clock DSCK PSCK PCM I/F PDATA3 PDATA4 PDATA2 PDATA1 PLRCK PBCK PCM Filter (x8 DF) DSD Filter DSD I/F DSD7 DSD8 DSD6 DSD5 DSD4 DSD3 DSD2 DSD1 DBCK Function ControlMDI MDO MC MS RST VCOM 2 VCOM 1
Figure 20. System Clock Input Timing 36). This allows an external controller or master reset circuit to force the DSD1608 to initialize to its reset state. the initialization sequence, which requires 1024 system clock periods.
1024 System Clocks
Figure 21. Power-On Reset Timing Figure 22. External Reset Timing
SLES040 – JUNE 2002 www.ti.com Audio Serial Interface The DSD1608 has two audio serial interface ports: PCM audio interface port and DSD audio interface port. In the PCM mode, the audio interface is a 3-wire serial port. It includes PLRCK (pin 51), PBCK (pin 50), and PDATA1 –PDATA4 (pins 46–49). PBCK is the serial audio bit clock, and it is used to clock the serial data present on PDATA1 –4 into the audio interface serial shift register. Serial data is clocked into the DSD1608 on the rising edge of PBCK. PLRCK is the serial audio left/right word clock. It is used to latch serial data into the serial audio interface internal registers. The DSD1608 requires the synchronization of PLRCK to the system clock, but does not require a specific phase relation between PLRCK and system clock. If the relationship between PLRCK and system clock changes more than ±6 PBCK, internal operation is initialized within 1/f S and analog outputs are forced to 0.5 VCC until re-synchronization between PLRCK and the system clock is completed. In the DSD mode, the audio interface is a 2-wire serial port. DBCK (pin 37) is the serial audio bit clock, and it is used to clock the individual direct stream digital (DSD) audio data on DSD1–DSD8 (pins 38–45). DSD data is clocked into the DSD1608 on the rising edge of DBCK. DBCK must be synchronous with the system clock, but does not require a specific phase relation to the system clock. DBCK is operated at the sampling frequency f S; the fS of DSD is 64 × 44.1 kHz, nominal. Audio Data Formats and Timing In the PCM mode, the DSD1608 supports industry-standard audio data formats, including standard, I2S, and left-justified. The data formats are shown in Figure 23. Data formats are selected using the format bits, FMT[2:0], in control register 10. The default data format is 24-bit standard format. All formats require binary 2s complement, MSB-first audio data. Figure 24 shows a detailed timing diagram for the serial audio interface. In the DSD mode, the DSD1608 supports a DSD audio data format. The data formats are shown in Figure 25. Figure 26 shows a detailed timing diagram for the DSD audio data interface. Serial Control Interface The serial control interface is a 4-wire serial port which operates completely asynchronously from the serial audio interface and the system clock. The serial control interface is used to access the on-chip mode registers. The control interface includes MDI (pin 2), MDO (pin 5), MC (pin 4), and MS (pin 3). MDI is the serial data input, used to program the mode registers. MDO is the serial data output, used to read back the values of the mode registers. MC is the serial bit clock, used to shift data into the control port, and MS is the chip select for the control port.
Figure 23. PCM Data Format
Table 2. User-Programmable Mode Controls
12 AZRO √
Table 3. Mode Control Register Map
SLES040 – JUNE 2002 www.ti.com Register Definitions B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 0 R/W 0 0 0 0 0 0 0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 Register 7 R/W 0 0 0 0 1 1 1 AT87 AT86 AT85 AT84 AT83 AT82 AT81 AT80 R/W Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. ATxy Digital Attenuation Level Setting :PCM/DSD Mode Where x = register number + 1 and y = 1 to 8, corresponding to the DAC output V OUT 1 to VOUT 8. In PCM mode, the default value, 1111 1111b, represents 0 dB. Each DAC channel (VOUT 1 to VOUT 8) includes a digital attenuation function. The attenuation level can be set from 0 dB to –119.5 dB in 0.5 dB steps or to –∞ in PCM mode, and from 6 dB to –113.5 dB or to –∞ in DSD mode. Alternatively, the attenuation level can be set to infinite attenuation (or mute). The following table shows attenuation levels for various settings. ATxy DECIMAL VALUE ATTENUATION LEVEL SETTING PCM Mode DSD Mode 1111 1111b 255 0 dB, no attenuation (default) 6 dB 1111 1110b 254 –0.5 dB 5.5 dB 1111 1101b 253 –1 dB 5 dB : : : : 1111 0011b 243 –6 dB 0 dB 1111 0010b 242 –6.5 dB –0.5 dB : : : : 1000 0011b 131 –62 dB –56 dB 1000 0010b 130 –62.5 dB –56.5 dB 1000 0001b 129 –63 dB –57 dB 1000 0000b 128 –63.5 dB –57.5 dB : : : : 0111 0101b 117 –69 dB –63 dB : : : : 0001 0000b 16 –119.5 dB –113.5 dB 0000 1111b 15 –∞ –∞ : : : : 0000 0000b 0 –∞ –∞ B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 8 R/W 0 0 0 1 0 0 0 MUT8 MUT7 MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 R/W Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. MUTx Soft Mute Control :PCM/DSD Mode Where x = 1 to 8, corresponding to the DAC output V OUT 1 to VOUT 8. Default value: 0 MUTx = 0 Mute disabled (default) MUTx = 1 Mute enabled The mute bits, MUT1 to MUT8, are used to enable or disable the soft mute function for the corresponding DAC outputs, VOUT 1 to VOUT 8. The soft mute function is incorporated into the digital attenuators. When mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation, one attenuator step (0.5 dB) at a time. This provides pop-free muting of the DAC output. By setting MUTx = 0, the attenuator is incremented one step at a time to the previously programmed attenuation level.
SLES040 – JUNE 2002 www.ti.com B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 9 R/W 0 0 0 1 0 0 1 DAC8 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 R/W Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. DACx DAC Operation Control :PCM/DSD Mode Where x = 1 to 8, corresponding to the DAC output V OUT 1 to VOUT 8. Default value: 0 DACx = 0 DAC operation enabled (default) DACx = 1 DAC operation disabled The DAC operation controls are used to enable and disable the DAC outputs, VOUT 1 to VOUT 8. When DACx = 0, the corresponding output generates the audio waveform dictated by the data present on the DATA pin. When DACx = 1, the corresponding output is set to the bipolar zero level, or VCC / 2. In the TDMCA mode, the DACx bits are affected after the next PLRCK when the write operation occurs. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 10 R/W 0 0 0 1 0 1 0 RSV FLT ATS RSV CKCE FMT2 FMT1 FMT0 R/W Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. RSV Reserved Bit The RSV bit must be set to 0. FLT Digital Filter Roll-Off Control :PCM Mode Default value: 0 FLT = 0 Sharp rolloff (default) FLT = 1 Slow rolloff The FLT bit allows the user to select the digital filter rolloff that is best suited to a particular application. Two filter rolloff selections are available: sharp and slow. The filter responses for these selections are shown in the Typical Performance Curves section of this data sheet. ATS Attenuation Rate Select :PCM/DSD Mode Default value: 0 ATS = 0 8/fS (default) ATS = 1 16/fS The ATS bit is used to select the rate at which the attenuator is decremented / incremented during level transitions. CKCE Clock Select Control :DSD Mode Default value: 0 CKCE = 0 System clock is applied to PSCK in the DSD mode (default). CKCE = 1 System clock is applied to DSCK in the DSD mode. The CKCE bit selects the system clock source in the DSD mode (PSCK or DSCK). The CKCE bit must be set before the DSD bit in register 12 can be set to 1. FMT[2:0] Audio Interface Data Format :PCM Mode Default value: 000. The FMT[2:0] bits are used to select the data format for the serial audio interface. The table below shows the available format options.
SLES040 – JUNE 2002 www.ti.com FMT[2:0] Audio Data Format Select 000 24-bit standard format, right-justified data (default) 001 20-bit standard format, right-justified data 010 18-bit standard format, right-justified data 011 16-bit standard format, right-justified data
100 I2S format, 24 bits
101 Left-justified format, 24 bits
110 Reserved
111 Reserved
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 11 R/W 0 0 0 1 0 1 1 OVR1 OVR0 DMF1 DMF0 DM78 DM56 DM34 DM12 R/W Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. OVR[1:0] Delta-Sigma Oversampling Rate Select Default value: 0 OVR[1:0] Oversampling Rate Select 00 64× fS (default) 01 128× fS 1x 32× fS The OVR[1:0] bits are used to change the oversampling rate of delta-sigma modulation. This function makes it easy to design a post-low-pass filter for any sampling rate. DMF[1:0] De-Emphasis Sampling Frequency Select Default value: 0 DMF[1:0] De-Emphasis Sampling Frequency Select 00 44.1 kHz (default) 01 48 kHz 10 32 kHz
11 Reserved
The DMF[1:0] bits are used to select the sampling frequency for the digital de-emphasis function when de-emphasis is enabled. DMxx De-Emphasis Function Control Default value: 0 DMxx = 0 De-emphasis function disabled (default) DMxx = 1 De-emphasis function enabled The DMxx bits are used to enable or disable the digital de-emphasis function of selected channel pairs. Suffix 12, 34, 56, 78 means Channel 1 and 2, 3 and 4, 5 and 6, and 7 and 8 respectively. See the plots shown in the Typical Performance Curves section of this data sheet. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 12 R/W 0 0 0 1 1 0 0 SRST DSD AZRO ZREV DRV78 DRV56 DRV34 DRV12
SLES040 – JUNE 2002 www.ti.com R/W Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. SRST System Reset :PCM/DSD Mode Default value: 0. This bit is available only in the write mode. SRST = 1 DAC system is reset once. The SRST bit allows the user to reset DAC system. This function is same as the power-on reset. When the SRST is set to 1, one reset pulse is generated internally. It is not necessary to set SRST to 0. DSD DSD Mode Control :PCM/DSD Mode Default value: 0 DSD = 0 PCM mode (default) DSD = 1 DSD mode The DSD bit allows the user to select the operation mode, PCM mode or DSD mode. AZRO Zero Flag Output Pin Select :PCM Mode Default value: 0 AZRO = 0 When ZREV = 0 and either the channel 1 or channel 2 data is continuously zero, the ZERO1 and ZERO2 pins go HIGH. When ZREV = 1 and either the channel 1 or channel 2 data is continuously zero, the ZERO1 and ZERO2 pins go LOW (default). AZRO = 1 When ZREV = 0 and both the channel 1 and channel 2 data is continuously zero, the ZERO1 and ZERO2 pins go HIGH. ZERO2 pin stay in LOW. When ZREV = 1 and both the channel 1 and channel 2 data is continuously zero, the ZERO1 and ZERO2 pins go LOW. The AZRO bit allows the user to select the output form of ZERO1 and ZERO2. ZREV Zero Flag Polarity Select :PCM Mode Default value: 0 ZREV = 0 Zero flag pins HIGH at a zero detect (default) ZREV = 1 Zero flag pins LOW at a zero detect The ZREV bit allows the user to select the polarity of zero flag pins. DRVxx Output Phase Select :PCM/DSD Mode Default value: 0 DRVxx = 0 Normal output (default) DRVxx = 1 Inverted output The DRVxx bits control output analog signal phase for channel pairs. The xx suffix in the register name designates the channel pair: -12 indicates channels 1 and 2; -34 indicates channels 3 and 4; -56 indicates channels 5 and 6; and -78 indicates channels 7 and 8. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 13 R/W 0 0 0 1 1 0 1 FS41 FS40 FS31 FS30 FS21 FS20 FS11 FS10 Register 14 R/W 0 0 0 1 1 1 0 FS81 FS80 FS71 FS70 FS61 FS60 FS51 FS50
SLES040 – JUNE 2002 www.ti.com R/W Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. FSxy DSD Filter Select :DSD Mode Default value: 00 FSxy DSD Filter Select
00 Filter 1 (default)
01 Filter 2
10 Filter 3
The FSxy bits allow selection of the DSD filter from three kind of filters for each channel. The x suffix in the register name designates the channel, from 1 to 8, for which the filter is being selected. The y suffix in the register name designates the high or low bit of the filter selection value. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 16 R 0 0 1 0 0 0 0 ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1 R Read Only ZEROx Zero Flag ZEROx = 0 Not zero detected on indexed channel ZEROx = 1 Zero detected on indexed channel The ZEROx bits indicate indexed the result of ZERO detection circuit of each channels. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 17 R 0 0 1 0 0 0 1 RSV RSV RSV ID4 ID3 ID2 ID1 ID0 R Read Only RSV Reserve Bit The RSV bit is read as 0. ID[4:0] Device ID The ID[4:0] bits show a device ID in TDMCA mode. ANALOG OUTPUTS The DSD1608 includes eight independent output channels: VOUT 1 to VOUT 8. These are unbalanced outputs, each capable of driving 4 Vp-p typical into a 10-kΩ ac-coupled load. The internal output amplifiers for VOUT 1 to VOUT 8 are biased to the dc common-mode (or bipolar zero) voltage, equal to VCC /2. The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy present at the DAC outputs due to the noise shaping characteristics of the DSD1608 delta-sigma D/A converters. The frequency response of this filter is shown in Figure 30. By itself, this filter is not enough to attenuate the out-of-band noise to an acceptable level for many applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the Applications Information section of this data sheet.
Figure 30. Analog Output Filter Performance (100 Hz–10 MHz) Zero detection for each channel or combination of channels is independent from any other. (or PLRCK clock periods), a zero-detect condition exists for that channel or combination of channels. In DSD mode, zero detection is not available. reset default is active-high output, or ZREV = 0.
SLES040 – JUNE 2002 www.ti.com
APPLICATION INFORMATION
A basic connection diagram is shown in Figure 31, with the necessary power supply bypass and decoupling components. The use of series resistors (22 Ω to 100 Ω ) is recommended for the xSCK, PLRCK, xBCK, PDATAX, and DSDx inputs. The series resistor combines with the stray PCB and device input capacitance to form a low-pass filter which reduces high-frequency noise emissions and helps to dampen glitches and ringing present on clock and data lines. POWER SUPPLIES AND GROUNDING The DSD1608 requires a 5-V analog supply and a 3.3-V digital supply. The 5-V supply is used to power the DAC analog and output filter circuitry, while the 3.3-V supply is used to power the digital filter and serial interface circuitry. For best performance, the 3.3-V digital supply should be derived from the 5-V supply by using a linear regulator. Texas Instruments’ REG1117-3.3 is an ideal choice for this application. Proper power supply bypassing is shown in Figure 31. The 10-µF capacitors should be tantalum or aluminum electrolytic, while the 0.1-µF capacitors are ceramic (the X7R type is recommended for surface-mount applications).
27 MHz Master Clock
Figure 31. Basic Connection Diagram
TDMCA requires six signals, of which four are for command and audio data interface and two are for the daisy chain. frame within a PLRCK clock cycle. ADC is an OUT device, a CODEC is an IN/OUT device, and a PLL is a NO device. The DSD1608 is an IN device. corresponding device IDs to be 1. Figure 34. Daisy Chain Connection
Figure 35. IN and OUT Daisy Chain Connection for Multichip System
58 BCKs
Figure 36. Device ID Determination Sequence
32 Bits
Figure 37. General TDMCA Frame
7 Packets x 32 Bits
Figure 38. TDMCA Frame Example of 6-Ch DAC and 2-Ch ADC With Command Read
SLES040 – JUNE 2002 www.ti.com Command Field The command field is defined as follows. The DID field (MSB) has another meaning, that this frame is for device ID determination. 31 30 29 28 24 23 22 21 20 16 15 8 7 0 command DID EMD DCS Device ID R/W Register ID Data Not used Bit 31: Device ID Enable Flag The DSD1608 operates to get its own device ID if this bit is HIGH. This is for TDMCA initialization. Bit 30: Extended Command Enable Flag An EMD packet is transferred if this bit is HIGH, otherwise skipped. When the bit is HIGH, this frame does not contain any audio data. This is for system initialization. Bit 29: Daisy Chain Selection Flag HIGH means OUT chain devices, LOW means IN chain devices. The DSD1608 is an IN device, so the DCS bit must be set to LOW. Bit [28:24]: Device ID The device ID is 5 bits in length, and it can be defined. IDs of devices follow the order of an IN or OUT daisy chain. The top device of the daisy chain has device ID 1 and the next device in the chain has device ID 2, etc. The ID for any device that has its DCI set HIGH is also 1. The maximum device ID each in the IN or OUT chain is 30. If a device ID is 0x1F, all devices are selected as broadcast when in the write mode. If any device ID is 0x00, no device is selected. Bit 23: Command Read/Write Flag If it is HIGH, the command is a read operation. Bit [22:16]: Register ID The register ID is 7 bits in length. See Table 3. Bit [15:18]: Command Data The command data is 8 bits in length. Any valid data can be chosen for each register. See Table 3. Bit [7:0]: Not used These bits are never transported when a read operation is performed. Extended Command Field The extended command field is almost the same as the command field. The only difference is that it does not have a DID flag. 31 30 29 28 24 23 22 21 20 16 15 8 7 0 Extended command RSVD EMD DCS Device ID R/W Register ID Data Not Used Audio Field The audio field is 32 bits in length and the audio data is transferred MSB first. When transferring audio data of less than 32 bits, the unused portion of the field must be padded with 0s, as the following figure shows. 31 16 12 8 7 0 Audio data MSB 24 bits LSB All 0s MSB 20 bits LSB All 0s MSB 16 bits LSB All 0s TDMCA Register Requirements The TDMCA mode requires device ID and audio channel information, previously described. Register 9 indicates the audio channels and register 17 indicates the device ID. Register 17 is used only in the TDMCA mode. See the Mode Control Register Map, Table 3.
1 PBCK Early
Figure 39. TDMCA Write and Read Operation Timing the last audio channel of each device. Therefore, DCI means that the next audio channel is allocated.
9 Packets x 32 Bits
Figure 40. DCO Output Timing in TDMCA-Mode Operation
17 Packets x 32 Bits
Figure 41. DCO Output Timing Example for 16-Ch Audio Data of Two DSD1608s
that the DCO will be passed through the next DCI. Figure 42 and Figure 43 show DCO timing with skip operation. Figure 44 shows the ac timing of daisy chain signals.
14 PBCK Delay
2 PBCK Delay
5 Packets x 32 Bits
Figure 42. DCO Output Timing With Skip Operation Figure 43. DCO Output Timing With Skip Operation (for Command Packet 1)
(1)Load capacitance is 10 pF. Figure 44. AC Timing of Daisy Chain Signals
- Decides daisy chain to initialize PLRCK and PBCK signals generator
- Generates TDMCA mode determination sequence
- Sets DID flag in command to fix device ID automatically
- Checks all device IDs if necessary
- Communicates audio data and commands
Figure 45. TDMCA Control Flow From Host
SLES040 – JUNE 2002 www.ti.com MECHANICAL DATA PAH (S-PQFP-G52) PLASTIC QUAD FLATPACK 0,13 NOM 0,25 0,45 0,75 0,05 MIN Seating Plane 4040281/C 11/96 Gage Plane 0,22 0,38 7,80 TYP SQ 9,80 1,05 0,95 11,80 12,20 1,20 MAX 10,20 SQ 0,10 0,65 M0,13 0°–/C02577° NOTES:A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third–party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments Incorporated