DSC557-03 MICREL | Alldatasheet
Document overview
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Technical content
Features
Meets PCIe Gen1, Gen2 & Gen3 specs. Available Output Formats: o HCSL, LVPECL, or LVDS o HCSL/LVPECL, HCSL/LVDS, LVPECL/LVDS Wide Temperature Range o Ext. Industrial: -40° to 105° C o Industrial: -40° to 85° C o Ext. commercial: -20° to 70° C Supply Range of 2.25 to 3.6 V Low Power Consumption o 30% lower than competing devices Excellent Shock & Vibration Immunity o Qualified to MIL-STD-883 Available Footprints: o 16 TSSOP o 14 QFN Lead Free & RoHS Compliant Short Lead Time: 2 Weeks
Applications
Communications/Networking o Ethernet o 1G, 10GBASE-T/KR/LR/SR, and FcoE o Routers and Switches o Gateways, VoIP, Wireless AP’s o Passive Optical Networks Storage o SAN, NAS, SSD, JBOD Embedded Applications o Industrial, Medical, and Avionics o Security Systems and Office Automation o Digital Sinage, POS and others Consumer Electronics o Smart TV, Bluray, STB
DSC557-03 Page 2 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator Specifications (Unless specified otherwise: T=25° C, VDD =3.3V) Notes: 1. VDD should be filtered with 0.01uf capacitor. 2. Output is enabled if OE pin is floated or not connected. 3. tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled. 4. Output Waveform and Connection Diagram define the parameters. 5. Period Jitter includes crosstalk from adjacent output. 6. Contact Sales@Discera.com for alternate output options (LVPECL, LVDS, LVCMOS). 7. Contact Sales@Discera.com for alternative frequency options Parameter Condition Min. Typ. Max. Unit Supply Voltage1 VDD 2.25 3.6 V Supply Current IDD EN pin low – outputs are disabled 21 23 mA Supply Current2 (Two HCSL Outputs) IDD EN pin high – outputs are enabled RL=50 Ω, FO1=FO2=100 MHz 60 mA Frequency Stability Δf Includes frequency variations due to initial tolerance, temp. and power supply voltage ±100 ppm ±50 Startup Time3 tSU 5 ms Input Logic Levels Input logic high Input logic low VIH VIL 0.75xVDD 0.25xVDD V Output Disable Time4 tDA 5 ns Output Enable Time tEN 20 ns Pull-Up Resistor2 Pull-up on OE pin 40 kΩ HCSL Outputs6 Parameter Condition Min. Typ. Max. Unit Output Logic Levels Output logic high Output logic low VOH VOL RL=50Ω 0.725 0.1 V Pk to Pk Output Swing Single-Ended 750 mV Output Transition time4 Rise Time Fall Time tR tF 20% to 80% RL=50Ω, CL= 2pF 200 400 ps Frequency f0 Single Frequency 2.3 1007 460 MHz Output Duty Cycle SYM Differential 48 52 % Period Jitter5 JPER FO1=FO2=100 MHz 2.5 psRMS Jitter, Phase (Common Clock Architecture) RJ PCIe Gen 1.1 TJ=DJ + 14.069 x RJ (BER 10-12) 0.540 PsRMS DJ TJ PCIe Gen 1.1 TJ=DJ + 14.069 x RJ (BER 10-12) 0.832 8.536 41.98 86.08 psp-p JRMS-CCHF PCIe Gen 2.1, 1.5 MHz to Nyquist 0.458 3.18 psRMS JRMS-CCLF PCIe Gen 2.1, 10 kHz to 1.5 MHz 0.030 3.08 psRMS JRMS-CC PCIe Gen 3.0 0.165 1.08 psRMS Integrated Phase Noise (Data Clock Architecture) JRMS-DCHF PCIe Gen 2.1, 1.5 MHz to Nyquist 0.561 4.08 psRMS JRMS-DCLF PCIe Gen 2.1, 10 kHz to 1.5 MHz 1.778 7.58 psRMS JRMS-DC PCIe Gen 3.0 0.147 1.08 psRMS
DSC557-03 Page 3 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator Absolute Maximum Ratings Item Min Max Unit Condition Supply Voltage -0.3 +4.0 V Input Voltage -0.3 VDD+0.3 V Junction Temp - +150 °C Storage Temp -55 +150 °C Soldering Temp - +260 °C 40sec max. ESD HBM MM CDM 4000 400 1500 V Solder Reflow Profile
14 QFN MSL 1 @ 260°C refer to JSTD-020C
16 TSSOP MSL 3 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp) 3°C/Sec Max. Preheat Time 150°C to 200°C 60-180 Sec Time maintained above 217°C 60-150 Sec Peak Temperature 255-260°C Time within 5°C of actual Peak 20-40 Sec Ramp-Down Rate 6°C/Sec Max. Time 25°C to Peak Temperature 8 min Max. 60-150 Sec 20-40 Sec 60-180 Sec 8 min max Pre heat Reflow Cool Time Temperature (°C) 3C/Sec Max. 6C/Sec Max. 200°C 217°C 150°C 25°C 260°C 3C/Sec Max. 60-150 Sec 20-40 Sec 60-180 Sec 8 min max Pre heat Reflow Cool Time Temperature (°C) 3C/Sec Max. 6C/Sec Max. 200°C 217°C 150°C 25°C 260°C 60-150 Sec 20-40 Sec 60-180 Sec 8 min max Pre heat Reflow Cool Time Temperature (°C) 3C/Sec Max. 6C/Sec Max. 200°C 217°C 150°C 25°C 260°C 3C/Sec Max.
DSC557-03 Page 4 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator Pin Diagram (16 TSSOP) Connection Diagram (16 TSSOP Two HCSL Outputs) 8 9 16NC NC NC NC NC OE VSS NC NC CLK1+ CLK1- NC NC CLK0- CLK0+ VDD 16-TSSOP (173 mil) (5.1 x 6.8 mm) 8 9 VDD Enable 0.01 uF
50 W 50 W
Pin Description (16 TSSOP) Pin No. Pin Name9 Pin Type Description
1 NC NA No connect
2 NC NA No connect
3 NC NA No connect
4 NC NA No connect
5 NC NA No connect
6 OE I Output Enable; active high
7 VSS Power Ground
8 NC NA No connect
9 NC NA No connect
10 CLK1+ O True output of differential pair
11 CLK1- O Complement output of differential pair
12 NC NA No connect
13 NC NA No connect
14 CLK0- O Complement output of differential pair
15 CLK0+ O True output of differential pair
16 VDD Power Power Supply
DSC557-03 Page 5 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator Pin Diagram (14 QFN) Connection Diagram (14 QFN Two HCSL Outputs) 5 6 7 121314 NC NC NC OE VSS NC CLK1+ CLK1- CLK0- CLK0+ VDD1 14 QFN 3.2x2.5mm NC NC VDD0 VDD Enable 0.01 uF 0.01 uF Ropt Ropt 22W - 33 W optional Pin Description (14 QFN) Pin No. Pin Name Pin Type Description
1 OE I Output Enable; active high
2 NC NA Ground recommended or leave as a NC
3 NC NA Ground recommended or leave as a NC
4 VSS Power Ground
5 NC NA Ground recommended or leave as a NC
6 NC NA Ground recommended or leave as a NC
7 NC NA Ground recommended or leave as a NC
8 CLK1+ O True output of differential pair
9 CLK1- O Complement output of differential pair
10 CLK0- O Complement output of differential pair
11 CLK0+ O True output of differential pair
12 VDD1 Power Power Supply for Core and Output 1 (CLK0+/-)
13 VDD0 Power Power Supply for Output 0 (CLK1+/-)
14 NC NA Ground recommended or leave as a NC
DSC557-03 Page 6 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator OE Function and Output Waveform: HCSL Ordering Information9 Note 9. CLK0 and CLK1 are configured at the factory to 100 MHz. (For other frequencies, contact the factory at sales@discera.com.) VIL 1/fo Output Enable tDA tEN tFtR VIH 80% 20% 50% Output 830 mv DSC557-03 Packing T: Tape & Reel F I 0 Package F: 14 QFN S: 16 TSSOP Temp Range E: -20 to 70 I: -40 to 85 L: -40 to 105 Stability 0: ±100ppm 1: ±50ppm T CLK 1 Output Format 1: LVCMOS 2: LVPECL 3: LVDS 4: HCSL 4 4 - CLK 0 Output Format 1: LVCMOS 2: LVPECL 3: LVDS 4: HCSL 675 mV
DSC557-03 Page 7 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator Package Dimensions F: 14 QFN, 3.2 x 2.5 mm
DSC557-03 Page 8 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator S: 16 TSSOP (173 mil body width) Recommended Solder Pad Layout Units mm [in] 0.65 [0.256] 0.3 [0.012] 1.1[0.043] 4.85 [0.191]
DSC557-03 Page 9 MK-QB-P-D-120917-01-2 DSC557-03 Crystal-less Two Output PCIe Gen1/2/3 Clock Generator Disclaimer: Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. MICREL, Inc. ● 2180 Fortune Drive, San Jose, California 95131 ● USA Phone: +1 (408) 944-0800 ● Fax: +1 (408) 474-1000 ● Email: hbwhelp@micrel.com ● www.micrel.com