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Technical content
Features
- AEC-Q100 Automotive Qualified
- Low RMS Phase Jitter: <1 ps (typ.)
- Complies with PCIe Gen1/2/3/4 Common Clock Spec
- High Stability: ±25 ppm, ±50 ppm
- Wide Temperature Range: - Automotive Grade 2: –40°C to +105°C - Automotive Grade 3: –40°C to +85°C
- High Supply Noise Rejection: –50 dBc
- Four Format-Configurable Outputs: - LVPECL, LVDS, HCSL, LVCMOS
- Available Pin-Selectable Frequency Table - 1 Pin per Bank for 2 Frequency Sets
- Wide Frequency Range: - 2.3 MHz – 460 MHz
- 20-Pin QFN Footprint (5.0 mm x 3.2 mm)
- Excellent Shock and Vibration Immunity
- High Reliability - 20x better MTF than quartz-based devices
- Wide Supply Range of 2.25V to 3.6V
- Lead Free and RoHS-Compliant
Applications
- Automotive Infotainment
- Automotive ADAS
- Autonomous Driving
- In-Vehicle Network General Description The DSA400 is a four output clock generator. It utilizes proven PureSilicon™ MEMS technology to provide excellent jitter and stability while incorporating additional device functionality. The nominal frequencies of the outputs can be identical or independently derived from common PLLs. The four output DSA400 MEMS oscillators are excellent choices for use as clock references in automotive applications in which small size, low power consumption, and long-term reliability are paramount. The DSA400 is AEC-Q100 qualified. Each output may be configured independently to support a single-ended L VCMOS interface or a differential interface. Differential options include LVPECL, LVDS, or HCSL. The DSA400 provides two independent select lines for choosing between two sets of pre-configured frequencies per bank. It also has two OE pins to allow for enabling and disabling outputs. The DSA400 is packaged in a 20-pin QFN (5 mm x 3.2 mm) and is available in extended commercial and industrial temperature grades. The DSA400 is a highly configurable device and is factory programmed to meet the customer’s needs. Microchip’s ClockWorks Configurator must be used to choose the necessary options, create the final part number , data sheet, and order samples. Block Diagram CLK0+ BANK 2 OUTPUT CONTROL AND DIVIDERS CONTROL CIRCUITRY MEMS PLL OE1 OE2 FSB1 FSB2 BANK 1 CLK0- CLK3+ CLK3- CLK1+ CLK1- CLK2+ CLK2- PLL Configurable Four Output, Low Jitter Clock Generator for Automotive
DS20006356A-page 2 2020 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may af fect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Charcteristics: VDD = 3.3V; TA = +25°C unless otherwise specified. Parameters Symbol Min. Typ. Max. Units Conditions Supply Voltage (Note 1) VDD 2.25 — 3.6 V — Core Supply Current (Note 2) IDDCORE — 40 44 mA OE(1:2) = 0. All outputs disabled. Frequency Stability Δf — — ±25 ppm All temperature and VDD ranges.— — ±50 Aging - First Year ΔfY1 — — ±5 ppm One year at +25°C Aging - After First Year ΔfY2+ — — <±1 ppm/yr Year two and beyond at +25°C Start-up Time (Note 3) t SU — — 5 ms T = +25°C Input Logic Levels VIH 0.75 x VDD — — V Input logic high VIL — — 0.25 x VDD Input logic low Output Disable Time (Note 4) tDA — — 5 ns OE(1:2) transition from 1 to 0 Output Enable Time (Note 4) tEN — — 20 ns OE(1:2) transition from 0 to 1 Pull-Up Resistor RPU — 40 — kΩ All input pins have an internal pull-up Note 1: VDD pins should be filtered with a 0.1 μF capacitor connected between VDD and VSS. 2: The addition of IDDCORE and IDDIO provides the total current consumption of the device. 3: tSU is time to 100 ppm stable output frequency after VDD is applied and outputs are enabled. 4: See the Output Waveform section for more information.
TEMPERATURE SPECIFICATIONS (Note 1) Parameters Symbol Min. Typ. Max. Units Conditions Temperature Ranges Operating Temperature Range (T) TA –40 — +105 °C Ordering Option L TA –40 — +85 °C Ordering Option I Junction Temperature TJ — — +150 °C — Storage Temperature Range TS –40 — +150 °C — Soldering Temperature — — — +260 °C 40 sec. max. Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature, and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above +150°C can impact the device reliability. 2020 Microchip Technology Inc. DS20006356A-page 3 DSA400
DS20006356A-page 4 2020 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
FIGURE 2-1: Pin Configuration, 20-Pin QFN (5.0 mm x 3.2 mm) The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number Pin Name Pin Type Description 1 OE1 I Output Enable for Bank1 (CLK0 and CLK3); Active-High. See Table 3-1. 2 NC N/A Leave unconnected or connect to ground. 3 VSS PWR Ground. 4 VSS PWR Ground. 5 CLK0– O Complement output of differential pair 0 (off when in LVCMOS format). 6 CLK0+ O True output of differential pair 0 or LVCMOS output 0. 7 CLK1– O Complement output of differential pair 1 (off when in LVCMOS format). 8 CLK1+ O True output of differential pair 1 or LVCMOS output 1. 9 VDD2 PWR Power Supply for Bank2 (CLK1 and CLK2).
10 FSB2 I Input for selecting pre-configured frequencies on Bank2 (CLK1 and
CLK2). 11 OE2 I Output Enable for Bank2 (CLK1 and CLK2); Active-High. See Table 3-1. 12 NC N/A Leave unconnected or connect to ground. 13 VSS PWR Ground. 14 VSS PWR Ground. 15 CLK2– O Complement output of differential pair 2 (off when in LVCMOS format). 16 CLK2+ O True output of differential pair 2 or LVCMOS output 2. 17 CLK3– O Complement output of differential pair 3 (off when in LVCMOS format). 18 CLK3+ O True output of differential pair 3 or LVCMOS output 3. 19 VDD1 PWR Power Supply for Bank1 (CLK0 and CLK3).
20 FSB1 I Input for selecting pre-configured frequencies on Bank1 (CLK0 and
CLK3).
2020 Microchip Technology Inc. DS20006356A-page 5 DSA400
3.0 OPERATIONAL DESCRIPTION
The DSA400 is a clock generator. Unlike older clock generators in the industry, it does not require an external crystal to operate; it relies on the integrated MEMS resonator that interfaces with internal PLLs. This technology enhances performance and reliability by allowing tighter frequency stability over a far wider temperature range. In addition, the higher resistance to shock and vibration decreases the aging rate to allow for much improved product life in the system.
3.1 Inputs
There are four input signals in the device. Each has an internal (40 kΩ) pull-up to default the selection to a high (1). Inputs can be controlled through hardware strapping method with a resistor to ground to assert the input low (0). Inputs may also be controlled by other components’ GPIOs In case more than one frequency set is desired, FSB1 and FSB2 are used to independently select one of two sets per bank. FSB1 selects the pre-configured set on Bank1 (CLK0 and CLK3) and FSB2 selects the pre-configured set on Bank2 (CLK1 and CLK2), as shown in Table 0-1 in the Product Identification System section. If there is a requirement to disable outputs, the inputs OE1 and OE2 are used in conjunction to disable the banks of outputs. Outputs are disabled in tri-state (Hi-Z) mode. See Table 3-1 for more information. TABLE 3-1: OUTPUT ENABLE SELECTION TABLE OE1 OE2 Bank 1 (CLK0 & CLK3) Bank 2 (CLK1 & CLK2) 0 0 Hi-Z Hi-Z 0 1 Hi-Z Running 1 0 Running Hi-Z 1 1 Running Running
3.2 Outputs
The four outputs are grouped into two banks. Each bank is supplied by an independent V DD to allow for optimized noise isolation between the two banks. Each bank provides two synchronous outputs generated by a common PLL:
- Bank1 is composed of outputs CLK0 and CLK3.
- Bank2 is composed of outputs CLK1 and CLK2. Each output may be pre-configured independently to be one of the following formats: L VCMOS, LVDS, LVPECL or HCSL. In case the output is configured to be single-ended LVCMOS, the frequency is generated on the true output (CLKx+) and the complement output (CLKx–) is shut off in a low state. Frequencies can be chosen from 2.3 MHz to 460 MHz for differential outputs and from 2.3 MHz to 170 MHz on LVCMOS outputs.
3.3 Power
VDD1 and V DD2 supply the power to banks 1 and 2 respectively. Each V DD may have a different supply voltage from the other as long as it is within the 2.25V to 3.6V range. Each V DD pin should have a 0.1 μF capacitor to filter high-frequency noise. VSS is common to the entire device.
DS20006356A-page 6 2020 Microchip Technology Inc.
4.0 TERMINATION SCHEMES
4.1 LVPECL
100 Ω 130 Ω 82 Ω 130 Ω 82 Ω FIGURE 4-1: Typical LVPECL Termination Scheme. TABLE 4-1: LVPECL OUTPUTS ( Note 1) Parameter Symbol Min. Typ. Max. Units Condition Output Logic Levels VOH VDD – 1.08 — — V Output Logic High, RL = 50Ω to VDD–2V VOL — — VDD – 1.55 Output Logic Low, RL = 50Ω to VDD–2V Peak-to-Peak Output Swing — — 800 — mV Single-Ended Output T ransition Time (Note 2) tR — 250 — ps Rise Time. 20% to 80%; RL = 50Ω to VDD–2V tF — 250 — Fall Time. 20% to 80%; RL = 50Ω to VDD– Frequency f0 2.3 — 460 MHz Single Frequency Output Duty Cycle SYM 48 — 52 % Differential IO Supply Current (Note 3) I DDIO — 35 38 mA Per Output at 125 MHz Period Jitter (Note 4) JPER — 2.5 — psRMS CLK(0:3) = 156.25 MHz Integrated Phase Noise JPH — 0.25 — psRMS 200 kHz to 20 MHz @ 156.25 MHz — 0.38 — 100 kHz to 20 MHz @ 156.25 MHz — 1.7 2 12 kHz to 20 MHz @ 156.25 MHz Note 1: L VPECL applicable to automotive Grade 3 temperature only. 2: See the Output Waveform section for more information. 3: The addition of IDDCORE and IDDIO provides the total current consumption of the device. 4: Period jitter includes crosstalk from adjacent output.
2020 Microchip Technology Inc. DS20006356A-page 7 DSA400
4.2 LVDS
100 Ω 100 Ω Load (receiver IC) FIGURE 4-2: Typical LVDS Termination Scheme. If the 100Ω clamping resistor does not exist inside the receiving device, it should be added externally on the PCB and placed as close as possible to the receiver. TABLE 4-2: LVDS OUTPUTS Parameter Symbol Min. Typ. Max. Units Condition Output Offset V oltage VOS 1.125 — 1.46 V R = 100Ω Dif ferential Delta Offset V oltage ∆VOS — — 100 mV — Peak-to-Peak Output Swing V PP — 350 — mV Single-Ended Output T ransition Time (Note 1) tR — 200 — ps Rise Time, 20% to 80%, RL= 50Ω, CL= 2 pF tF — 200 — Fall Time, 20% to 80%, RL= 50Ω, CL= 2 pF Frequency f0 2.3 — 460 MHz Single Frequency Output Duty Cycle SYM 48 — 52 % Differential IO Supply Current (Note 2) I DDIO — 9 12 mA Per Output at 125 MHz Period Jitter JPER — 2.5 — psRMS — Integrated Phase Noise JPH — 0.28 — psRMS 200 kHz to 20 MHz @ 156.25 MHz — 0.4 — 100 kHz to 20 MHz @ 156.25 MHz — 1.7 2.0 12 kHz to 20 MHz @156.25 MHz Note 1: See the Output Waveform section for more information. 2: The addition of IDDCORE and IDDIO provides the total current consumption of the device.
DS20006356A-page 8 2020 Microchip Technology Inc.
4.3 HCSL
33Ω 33Ω FIGURE 4-3: Typical HCSL Termination Scheme. The 33Ω series resistors are needed to avoid excessive ringing. TABLE 4-3: HCSL OUTPUTS Parameter Symbol Min. Typ. Max. Units Condition Output Logic Levels VOH 0.725 — — V Output Logic High, RL = 50Ω VOL — — 0.1 Output Logic Low, RL = 50Ω Peak-to-Peak Output Swing — — 750 — mV Single-Ended Output T ransition Time (Note 1) tR 200 — 400 ps Rise Time, 20% to 80%, RL= 50Ω, CL= 2 pF tF 200 — 400 Fall Time, 20% to 80%, RL= 50Ω, CL= 2 pF Frequency f0 2.3 — 460 MHz Single Frequency Output Duty Cycle SYM 48 — 52 % Differential IO Supply Current (Note 2) I DDIO — 20 22 mA Per Output at 125 MHz. Period Jitter JPER — 2.5 — psRMS — Integrated Phase Noise JPH — 0.25 — psRMS 200 kHz to 20 MHz @ 156.25 MHz — 0.37 — 100 kHz to 20 MHz @ 156.25 MHz — 1.7 2.0 12 kHz to 20 MHz @156.25 MHz Note 1: See the Output Waveform section for more information. 2: The addition of IDDCORE and IDDIO provides the total current consumption of the device.
2020 Microchip Technology Inc. DS20006356A-page 9 DSA400
4.4 LVCMOS
50 Ω 27Ω FIGURE 4-4: Typical LVCMOS Termination Scheme. The 27Ω Series resistor complements the output impedance of about 23 Ω to 50Ω impedance to match the line 50 Ω characteristic impedance to prevent reflections from the driver back to the receiver. TABLE 4-4: LVCMOS OUTPUTS Parameter Symbol Min. Typ. Max. Units Condition Output Logic Levels VOH 0.9 x VDD — — V Output Logic High, I = ±6 mA VOL — — 0.1 x VDD Output Logic Low, I = ±6 mA Output T ransition Time (Note 1) tR — 1.1 2.0 ns Rise Time, 20% to 80%, CL= 15 pF tF — 1.3 2.0 Fall Time, 20% to 80%, CL= 15 pF Frequency f0 — — 100 MHz — Output Duty Cycle SYM 44 — 55 % — IO Supply Current (Note 2) I DDIO — 11 14 mA Per Output at 125 MHz, CL = 15 pF Period Jitter JPER — 3 — psRMS CLK(0:3) = 125 MHz Integrated Phase Noise JPH — 0.3 — psRMS 200 kHz to 20 MHz @ 125 MHz — 0.38 — 100 kHz to 20 MHz @ 125 MHz — 1.7 2.0 12 kHz to 20 MHz @125 MHz Note 1: See the Output Waveform section for more information. 2: The addition of IDDCORE and IDDIO provides the total current consumption of the device.
DS20006356A-page 10 2020 Microchip Technology Inc.
5.0 OUTPUT WAVEFORM
50% 20% 80% FIGURE 5-1: Differential Output (LVDS, LVPECL, HCSL). OE tR tF 1/f0 tDA tEN Clk VIL VIH VOL VOH FIGURE 5-2: LVCMOS Output.
2020 Microchip Technology Inc. DS20006356A-page 11 DSA400
6.0 CONNECTION DIAGRAM
The connection diagram below includes recommended capacitors to be placed on each VDD for noise filtering. Frequency Select 1 OE2 NC VSS VSS VSS VSS NC OE1 CLK0‒ CLK0+ CLK1‒ CLK1+ VDD2 FSB2 CLK2 ‒ CLK2+ CLK3‒ CLK3+ VDD1 FSB1 Frequency Select 2 VDD Output Enable 1 Output Enable 2 VDD Clock 3 Output Clock 2 Output Clock 0 Output Clock 1 Output 0.1μF 0.1μF FIGURE 6-1: DSA400 Connection Diagram.
DS20006356A-page 12 2020 Microchip Technology Inc.
7.0 SOLDER REFLOW PROFILE
150°C 200°C 260°C Temperature 60-180 seconds 60-150 seconds CooldownReflowPreheat 20-40 seconds 8 minutes max. 25°C 6°C/sec max 3°C/sec max 3°C/sec max.217°C MSL 1 @ 260°C refer to JSTD-020C Ramp-Up Rate (200°C to Peak Temp) 3°C/sec. max. Preheat Time 150°C to 200°C 60-180 sec. Time Maintained above 217°C 60-150 sec. Peak Temperature 255°C to 260°C Time within 5°C of Actual Peak 20-40 sec. Ramp-Down Rate 6°C/sec. max. Time 25°C to Peak Temperature 8 minutes max.
2020 Microchip Technology Inc. DS20006356A-page 13 DSA400
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
20-Lead QFN* (5.0 mm x 3.2 mm) 0SSS DCP1907 1111Q0019 0K32 Legend: XX...X Product code or customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package.
- , ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle mark). Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. Underbar (_) and/or Overbar (‾) symbol may not be to scale.
DS20006356A-page 14 2020 Microchip Technology Inc. 20-Lead QFN 5.0 mm x 3.2 mm Package Outline and Recommended Land Pattern Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.
2020 Microchip Technology Inc. DS20006356A-page 15 DSA400 APPENDIX A: REVISION HISTORY Revision A (June 2020)
- Initial release of DSA400 as Microchip data sheet DS20006356A.
DS20006356A-page 16 2020 Microchip Technology Inc. NOTES:
2020 Microchip Technology Inc. DS20006356A-page 17 DSA400 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Examples: a) DSA400-2143QxxxxKI1VAO: Configurable Four Output, Low Jitter Clock Generator; LVPECL CLK3; LVCMOS CLK2; HCSL CLK1; LVDS CLK0; Frequency Code; 20-Pin QFN; –40°C to +85°C Temp. Range; ±50 ppm Stability; 72/Tube; Standard automotive b) DSA400-4132QxxxKI2TVAO: Configurable Four Output, Low Jitter Clock Generator; HCSL CLK3; LVCMOS CLK2; LVDS CLK1; LVPECL CLK0; Frequency Code; 20-Pin QFN; –40°C to +85°C Temp. Range; ±25 ppm Stability; 1,000/Reel; Standard automotive c) DSA400-0303QxxxxKL2VAO: Configurable Four Output, Low Jitter Clock Generator; OFF CLK3; LVDS CLK2; OFF CLK1; LVDS CLK0; Fre- quency Code; 20-Pin QFN; –40°C to +105°C Temp. Range; ±25 ppm Stability; 72/Tube; Standard automotive d) DSA400-1111QxxxxKL1TVAO: Configurable Four Output, Low Jitter Clock Generator; LVCMOS CLK3 through CLK0; Frequency Code; 20-Pin QFN; –40°C to +105°C Temp. Range; ±50 ppm Stability; 1,000/Reel; Standard automotive PART NO. XX Package StabilityDevice Device: DSA400: Configurable Four Output, Low Jitter Clock Generator CLK3 Output Format: 0 = OFF 1 = LVCMOS 2 = LVPECL 3 = LVDS 4 = HCSL CLK2 Output Format: 1 = LVCMOS 2 = LVPECL 3 = LVDS 4 = HCSL CLK1 Output Format: 0 = OFF 1 = LVCMOS 2 = LVPECL 3 = LVDS 4 = HCSL CLK0 Output Format: 1 = LVCMOS 2 = LVPECL 3 = LVDS 4 = HCSL Frequency Code: Qxxxx = This code is assigned by the factory. See Table 0-1 in this section for more information. Package: K = 20-Pin QFN Temperature Range: L = –40°C to +105°C (Automotive Grade 2) I = –40°C to +85°C (Automotive Grade 3) Stability: 1 = ±50 ppm 2 = ±25 ppm Packing: Blank = 72/Tube T = 1,000/Reel Automotive Suffix: VXX = Automotive Suffix in which “XX” is assigned by Microchip. Default value is “AO” for standard automo- tive part X CLK3 X Temp. Qxxxx Freq. Output Format X CLK2 Output Format X CLK1 Output Format X CLK0 Output Format Code Range X Packing XXX Automotive Suffix Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.
DS20006356A-page 18 2020 Microchip Technology Inc. Factory Configuration Code Assignment of Qxxxx The DSC400 is meant for customers to define their own frequency requirements at the four available outputs using ClockWorks Configurator. The Qxxxx number identifies these specific customer requirements and is assigned by the factory. TABLE 0-1: EXAMPLE OF HOW FSB1 & FSB2 ARE APPLIED & THE QXXXX ASSIGNMENT Bank1 Outputs FSB1 Qxxxx Number 1 (default) 0 Q1234 CLK0 125 MHz 150 MHz CLK3 50 MHz 25 MHz Bank2 Outputs FSB2 1 (default) 0 CLK1 156.25 MHz 100 MHz CLK2 156.25 MHz 100 MHz
2020 Microchip Technology Inc. DS20006356A-page 19 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2020, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-6182-1 Note the following details of the code protection feature on Microchip devices:
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- Microchip is willing to work with the customer who is concerned about the integrity of their code.
- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
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