DS99R421QSQX/NOPB

Texas Instruments

5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to FPD-Link II LVDS (Embedded Clock DC Balanced) Converter

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www.ti.com SNLS264D –JUNE 2007–REVISED APRIL 2013 5-43MHzFPD-LinkLVDS(3Data+1Clock)toFPD-LinkIILVDS(EmbeddedClockDC- Balanced)Converter Check forSamples: DS99R421 1FEATURES DESCRIPTION The DS99R421 convertsa FPD-Link inputwith 4 2• 5 MHz –43 MHz Embedded Clock & DC- non-DC Balanced LVDS (3 LVDS Data + LVDSBalanced Data Transmission(21TotalLVDS Clock)plus 3 over-sampledlow speed controlbitsData BitsPlus 3 Low Speed LVCMOS Data intoa singleLVDS DC-balanced serialstream withBits) embedded clockinformation.Thissingleserialstream

User AdjustablePre-Emphasis DrivingAbility simplifiestransferringthe 24-bitbus over a single Through ExternalResistoron LVDS Outputs differentialpair of PCB traces and cable by eliminatingtheskew problemsbetween the3 paralleland Capable toDriveup to10 Meters Shielded LVDS data inputsand LVDS clockpaths.ItsavesTwisted-PairCable system costby narrowing4 LVDS pairsto 1 LVDS• Supports AC-Coupling Data Transmission pairthatin turnreduce PCB layers,cable width,• 100Ω IntegratedTerminationResistoratLVDS connectorsize,and pins. Input The DS99R421 incorporatesa singleserializedLVDS• Power-Down Control signalon thehigh-speedI/O.Embedded clockLVDS
Available@SPEED BIST toDS90UR124 to providesa low power and low noiseenvironmentfor ValidateLinkIntegrity reliablytransferringdata over a serialtransmission path.By optimizingtheconverteroutputedge ratefor• AllLVCMOS Inputs& ControlPins Have theoperatingfrequencyrangeEMI isfurtherreduced.InternalPulldown Inadditionthedevicefeaturespre-emphasistoboost• SchmittTriggerInputson OS[2:0]toMinimize signalsover longerdistancesusing lossy cables.MetastableConditions InternalDC balanced encoding is used to support• Outputs Tri-StatedThrough DEN AC-Coupled interconnects.
On-Chip FiltersforPLLs
Power Supply Range 3.3V± 10%
Automotive Temperature Range −40°C to +105°C
GreaterThan 8kV ESD Tolerance
Meets ISO 10605 ESD and AEC-Q100 Compliance Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2007–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

100: Differential PCB Traces DOUT- R T = 100 RT = 100 RIN- Rx - DESERIALIZER DOUT+ RIN+ DS UR 124 DS 99R421 100: 100: 100: 100: LVDS DATA0 LVDS DATA1 LVDS DATA2 LVDS CLK (5 MHz to 43 MHz) GUI LVDS NON -DC Balanced OS [2:0] STP (Up to 10 meters) DEN Standard 4 LVDS - to - 1 LVDS Tx ± Converter PLL DOUT- DOUT+ DeSerializer Parallel to Serial DC Balance Encoder PRE

21 Bits

100: 100: 100: 100: RxIN0- (5 MHz to 43 MHz) LVDS NON -DC Balanced OS [2:0] VODSEL RxIN0+ RxIN1- RxIN1+ RxIN2- RxIN2+ RxCLKIN- RxCLKIN+ PWDNB DS99R421 SNLS264D –JUNE 2007–REVISED APRIL 2013 www.ti.com Block Diagram Figure1. Block Diagram ApplicationOverview Figure2. TypicalApplicationDiagram

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www.ti.com SNLS264D –JUNE 2007–REVISED APRIL 2013 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings (1)(2) SupplyVoltage(VDD ) −0.3Vto+4V LVCMOS InputVoltage −0.3Vto(VDD +0.3V) LVCMOS OutputVoltage −0.3Vto(VDD +0.3V) LVDS ReceiverInputVoltage −0.3Vto+3.9V LVDS DriverOutputVoltage −0.3Vto+3.9V LVDS OutputShortCircuitDuration 10 ms JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature(Soldering,4 seconds) +260°C Maximum Package Power Dissipation θJA 37.6(4L(3));83.7(2L(3))°C/WCapacity θJC 3.1(2/4L(3))°C/W HBM ≥±8 kV ESD Rating ISO10605 DS99R421 meets ISO10605 ContactDischarge,DOUT ± ±10 kV R D = 2 kΩ,C S = 150/330pF AirDischarge,DOUT ± ±25 kV (1) “AbsoluteMaximum Ratings”indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. (3) JEDEC Recommended OperatingConditions Min Nom Max Units SupplyVoltage(VDD ) 3.0 3.3 3.6 V OperatingFreeAirTemperature(TA) −40 +25 +105 °C InputClockRate,RxCLKIN ± 5 43 MHz SupplyNoise(VDDp-p) ±100 mV P-P ReceiverInputRange 0 VDD V ElectricalCharacteristics(1)(2)(3) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units LVCMOS & SCHMITT-TRIGGER INPUT DC SPECIFICATIONS VIH HighLevelInputVoltage PWDNB, DEN, VODSEL, 2.0 VDD V BISTENVIL Low LevelInputVoltage GND 0.8 V VCL InputClamp Voltage ICL = −18 mA −0.9 −1.5 V IIN InputCurrent VIN = 0V or3.6V −10 +10 µA VTH + HighLevelInputVoltage OS[2:0] 2.0 V (Schmitt-triggeredInputs)VTH − HighLevelInputVoltage 0.8 V VH HysteresisVoltage VTH + – VTH − 200 400 600 mV (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms at3.3V,Ta = +25 degC, and attheRecommended OperationConditionsatthe timeofproductcharacterizationand arenotensured. (3) Currentintodevicepinsisdefinedas positive.Currentoutofa devicepinisdefinedas negative.Voltagesarereferencedtoground exceptVOD ,ΔVOD ,VTH and VTL whicharedifferentialvoltages. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS99R421

SNLS264D –JUNE 2007–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics(1)(2)(3)(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units LVDS DC SPECIFICATIONS VTH DifferentialThresholdHigh VCM = 1.2V LVDS differentialInputs: +100 mVVoltage RxIN0±,RxIN1±,RxIN2±, RxCLKIN ±VTL DifferentialThresholdLow −100 mVVoltage |VID| DifferentialInputVoltage 100 600 mVSwing VCM Common Mode Voltage VDD −0.525 1.2 mV(VID/2) IIN InputCurrent VIN = +2.4V, −10 +10 µAVDD = 3.6V VIN = 0V, -10 +10 µAVDD = 3.6V VOD OutputDifferentialVoltage R T = 100Ω LVDS differentialOutputs: 380 500 630 mV(Figure10) VODSEL = L DOUT ± R T = 100Ω 650 900 1150 mVVODSEL = H ΔVOD OutputDifferentialVoltage R T = 100Ω 10 50 mVUnbalance VOS OutputVoltageOffset R T = 100Ω 1.0 1.2 1.5 VPRE = H (off) ΔVOS OutputVoltageOffset R T = 100Ω 5 50 mVDifference PRE = H (off) IOS OutputShortCircuitCurrent DOUT ± = 0V VODSEL = L −2 −8 mA PRE = H (off) DOUT ± = 0V VODSEL = H −7 −13 mA PRE = H (off) IOZ TRI-STATE OutputCurrent PWDNB = 0V, DOUT ± = 0V OR VDD −10 ±1 +10 µA (inputsnottoggling) R T InternalInputTermination RxIN: Resistance acrossRxIN(2:0)+& 90 105 130 ΩRxIN(2:0)−,and across RxCLKIN+ & RxCLKIN − CONVERTER SUPPLY CURRENT IDD TotalSupplyCurrent R T = 100Ω f= 43 MHz (includesloadcurrent) CHECKERBOARD pattern 95 130 mA PRE = 6 KΩ (Figure3) IDDTZ SupplyCurrentPower-down PWDNB = 0V 2 50 µA(inputsnottoggling) ReceiverInputTiming Requirements Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units tRCIH ReceiverClockInputHighTime Referencedtorisingedge ofRxCLKIN 0.35T 0.57T ns tRCIL ReceiverClockInputLow Time Referencedtorisingedge ofRxCLKIN 0.43T 0.65T ns

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www.ti.com SNLS264D –JUNE 2007–REVISED APRIL 2013 ReceiverInputSwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units RITOL-L ReceiverInputToleranceLeft 5 MHz –43 MHz 0.3 UI(Figure7 Figure8) (1)(2) RITOL-R ReceiverInputTolerance 5 MHz –43 MHz Right 0.3 UI (Figure7 Figure8) (1)(2) UI UnitInterval(1) 5 MHz –43 MHz 1/7thof nsRxCLKIN (1) UI – UnitInterval,equivalenttoone idealserializeddatabitwidth.The UI scaleswithfrequency.Fortheinput,itis1/7ththeinputclock (2) ReceiverInputToleranceisdefinedas thevaliddatasamplingregionatthereceiverinputs.Thismargintakesintoaccountthe transmitterpulsepositions(minand max) and thereceiverinputsetupand holdtime(internaldatasamplingwindow – RSPos).This marginallowsforLVDS interconnectskew,inter-symbolinterference(bothdependenton type/lengthofcable),and clockjitter. InputTiming Requirements forOS[2:0] Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units FOS [2:0] Maximum Frequency OS[2:0] FRxCLKIN /5 MHzLimitationofOS[2:0] InputtoOutput SwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units RCTCD RxCLK IN toDOUT Delay 5 MHz –43 MHz 4T + 1.0 4T + 5.0 4T + 10.0 ns(Figure5),(1) PDD Power Down Delay 5 MHz –43 MHz 1 µs (1) A ClockUnitSymbol (T)isdefinedas 1/(LinerateofRxCLKIN). SerializerOutput SwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units tLLHT LVDS Low-to-HighTransitionTime R T = 100Ω, 0.3 0.5 ns C L = 10 pF toGNDtLHLT LVDS High-to-LowTransitionTime 0.3 0.5 ns(Figure4) tPLT PLL Lock Time 5 MHz –43 MHz 10 ms TxOUT_E_O TxOUT_Eye_Opening (1)(2)(Figure9) 5 MHz –43 MHz 0.78 UI(respecttoideal) UI UnitInterval(1) 5 MHz –43 MHz 1/28thof nsDOUT (1) UI – UnitInterval,equivalenttoone idealserializeddatabitwidth.The UI scaleswithfrequency.Fortheinput,itis1/7ththeinputclock (2) TxOUT_E_O isaffectedby pre-emphasisvalue. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS99R421

|RxCLKIN RCTCD RxIN SYMBOL N+1SYMBOL N SYMBOL N+2 SYMBOL N+3 SYMBOL N+4 | | 80% 20% 80% 20% Vdiff = 0V tLLHT tLHLT Differential Signal Vdiff = (DOUT+) - (DOUT-) 100: DOUT+ DOUT- 10 pF 10 pF RxIN1 RxIN0 RxIN2 Previous Cycle Current Cycle Next Cycle RxCLKIN (Differential) Vdiff = 0V Vdiff = 0V Vdiff = 0V DS99R421 SNLS264D –JUNE 2007–REVISED APRIL 2013 www.ti.com AC TIMING DIAGRAMS AND TEST CIRCUITS Figure3. LVDS InputCheckerboard Pattern Figure4. SerializerLVDS Output Load and TransitionTimes Figure5. RxIN toDOUT Delay – RCTCD

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B3-1 B2-1 DE VSYNC HSYNC B5 B4 B3 B2 G2-1 G1-1 B1 B0 G5 G4 G3 G2 G1 R1-1 R0-1 G0 R5 R4 R3 R2 R1 R0 RxIN1 RxIN0 RxIN2 Previous Cycle Current Cycle Next Cycle RxCLKIN (Differential) Vdiff = 0V Vdiff = 0V Vdiff = 0V RITOL1 min RITOL1 max RITOL0 min RITOL0 max RITOL6 min RITOL6 max RITOL5 min RITOL5 max RITOL4 min RITOL4 max RITOL3 min RITOL3 max RITOL2 min RITOL2 max B3-1 B2-1 DE VSYNC HSYNC B5 B4 B3 B2 G2-1 G1-1 B1 B0 G5 G4 G3 G2 G1 R1-1 R0-1 G0 R5 R4 R3 R2 R1 R0 RxIN1 RxIN0 RxIN2 Previous Cycle Current Cycle Next Cycle RxCLKIN (Differential) Vdiff = 0V Vdiff = 0V Vdiff = 0V DS99R421 www.ti.com SNLS264D –JUNE 2007–REVISED APRIL 2013 Figure6. ReceiverLVDS InputMapping Figure7. ReceiverRITOL Min and Max Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS99R421

R T VDD = (DOUT+) - (DOUT-) Ideal Center Position (tBIT)/2 tBIT (1 UI) Ideal Data Bit End Ideal Data Bit Beginning DS99R421 Output Eye Opening Ideal Strobe Position (1/2 UI) (1 UI) Sampling WindowIdeal Bit Start RITOL (Left) RITOL (Right) Ideal Bit Stop DS99R421 SNLS264D –JUNE 2007–REVISED APRIL 2013 www.ti.com Figure8. ReceiverRITOL Leftand Right Figure9. SerializerOutput Eye Opening Figure10. SerializerVOD Diagram

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www.ti.com SNLS264D –JUNE 2007–REVISED APRIL 2013 PIN DESCRIPTIONS Pin # Pin Name I/O/PWR Description FPD-LINK LVDS RECEIVER INPUT PINS 28,30,32 RxIN[2:0]− LVDS_I LVDS ReceiverinvertedData Inputs(−) 29,31,33 RxIN[2:0]+ LVDS_I LVDS ReceivertrueData Inputs(+) 34 RxCLKIN − LVDS_I LVDS ReceiverinvertedreferenceClockInputs. Used tostrobedataattheRxIN inputsand todrivethereceiverPLL 35 RxCLKIN+ LVDS_I LVDS ReceivertruereferenceClockInputs. Used tostrobedataattheRxIN inputsand todrivethereceiverPLL OVER SAMPLED INPUT PINS 3-1 OS[2:0] LVCMOS_I Over Sampled ReceiverData InputswithSchmitttrigger CONTROL AND CONFIGURATION PINS

4 PWDNB LVCMOS_I Power Down Bar

PWDNB = H; DeviceisEnabledand ON PWDNB = L;Deviceisinpower down mode (Sleep),LVDS DriverD OUT (+/-)Outputsare inTRI-STATE stand-bymode, PLL isshutdowntominimizepower consumption.

15 DEN LVCMOS_I Data Enable

DEN = H; LVDS DriverOutputsareEnabled(ON). DEN = L;LVDS DriverOutputsareDisabled(OFF),SerializerLVDS DriverD OUT (+/-) OutputsareinTRI-STATE, PLL stilloperationaland lockedtoTCLK.

10 PRE LVCMOS_I Pre-emphasisLevelSelect

PRE = NC (No Connect);Pre-emphasisisDisabled(OFF). Pre-emphasisisactivewhen inputistiedtoVSS throughexternalresistorR PRE .Resistor valuedeterminespre-emphasislevel.Recommended valueR PRE ≥ 6 kΩ;Imax = [48/ R PRE ],R PREmin = 6 kΩ See ApplicationsInformationsectionformore details.

18 VODSEL LVCMOS_I VOD LevelSelect

VODSEL = L;LVDS DriverOutputis±500 mV (RT = 100Ω) VODSEL = H; LVDS DriverOutputis±900 mV (RT = 100Ω) Fornormalapplications,setthispinLOW. Forlongcableapplicationswhere a larger VOD isrequired,setthispinHIGH. See ApplicationsInformationsectionformore details. 36,24,21,9 RESRVD LVCMOS_I/O Reserved.ThispinMUST be tiedLOW. BIST MODE PINS

27 BISTEN LVCMOS_I ControlPinforBIST Mode Enable(ACTIVE H)

BISTEN = L;DefaultatLow, Normal Mode BISTEN = H; BIST mode active Note:Sequence orderforproperfunctionofBIST mode: 1)DS99R421 BISTEN = H. 2)DS99R421 PLL must be locked(10ms). 3)DS90UR124 PLL must be locked. 4)SelectBISTM errorreportingmode on DS90UR124. 5)DS90UR124 switchBISTEN fromL toH. LVDS SERIALIZER OUTPUT PINS 14 DOUT+ LVDS_O SerializerLVDS True(+)Output. Thisoutputisintendedtobe loadedwitha 100Ω loadtotheD OUT+ pin.The interconnect shouldbe AC Coupledtothispinwitha 100 nF capacitor.

13 DOUT − LVDS_O SerializerLVDS Inverted(-)Output

Thisoutputisintendedtobe loadedwitha 100Ω loadtotheD OUT- pin.The interconnect shouldbe AC Coupledtothispinwitha 100 nF capacitor. POWER /GROUND PINS

5 VDD P1 VDD AnalogPower supply,PLL POWER

6 VSS P1 GND AnalogGround,PLL GROUND

7 VDD P0 VDD AnalogPower supply,VCO POWER

8 VSS P0 GND AnalogGround,VCO GROUND

11 VDD DR VDD AnalogPower supply,LVDS OUTPUT POWER

12 VSS DR GND AnalogGround,LVDS OUTPUT GROUND

17 VDD SER VDD DigitalPower supply,SERIALIZER POWER

16 VSS SER GND DigitalGround,SERIALIZER GROUND

(No Pullback) DS99R421 SNLS264D –JUNE 2007–REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin # Pin Name I/O/PWR Description

19 VDD D VDD DigitalPower supply,LOGIC POWER

20 VSS D GND DigitalGround,LOGIC GROUND

22 VDD DES VDD DigitalPower supply,RECEIVER POWER

23 VSS DES GND DigitalGround,RECEIVER GROUND

25 VDD IN VDD AnalogPower supply,LVDS INPUT POWER

26 VSS IN GND AnalogGround,LVDS INPUT GROUND

PIN DIAGRAM — DS99R421 Figure11. TOP VIEW

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www.ti.com SNLS264D –JUNE 2007–REVISED APRIL 2013 FUNCTIONAL DESCRIPTION The DS99R421 isa Video Interfaceconverter.Itconvertsan FPD-Link interface(3 LVDS data channels+ 1 LVDS Clock,e.g.DS90C365A orequivalent)plusup tothree(3)LVCMOS additionalsignalsintoa singlehigh- speed LVDS serialInterface(seeFigure13). The 21 bitsof data from the FPD-Link Interfaceare serializedalongwiththe 3 additionalover-sampledbits (OS[2:0])intoa randomized,scrambledand DC BalanceddatastreamtosupportAC couplingand toenhance thesignaleye opening.Four (4)additionaloverheadbitsaresentperclockwhichprovidestheembedded clock and seriallinkcontrolinformation.The embedded clockLVDS serialstreamhas an effectivedatathroughputof 120 Mbps (5MHz X 24)to1.03Gbps (43MHz X 24).The DS99R421 LineDriverisdesignedtotransmitdataup to10 metersovershieldedtwistedpair(STP)atsignalingratesup to1.2Gbps (43MHz X 28). The DS90UR124 receiverconvertstheembedded clockLVDS streamback intoa 24-bitwide LVCMOS parallel bus and therecoveredlow-speedclock. Note:The DS90C124 isnotcompatiblewiththeDS99R421. LINK START UP The startup oftheDS99R421 involvesonlyone PLL Lock time.The FPD-LinkReceiversidemust locktoits incomingLVDS RxCLKIN. The SerializersidethenextractsitsreferenceclockfromtheincomingLVDS clock.At the farend of the link,the Deserializer(DS90UR124) alsoneeds to detectthe LVDS signalsand lockto the incomingserialstream,drivesthe LOCK pinHIGH, beforeoutputtingvaliddata.Note thatwhen usinga Bus Converter(FPD-LinktoSerial)additionaltimeisrequiredinthestartup toaccountfortheadditionalPLLs inthe path. TYPICAL START UP SEQUENCE 1. FPD-LinkStream isappliedtotheDS99R421 inputs. 2. With power appliedand the DS99R421 enabled,itwilllockto the incomingFPD-Link clock.Untilthe DS99R421 isready,itwillholditsoutputsinTRI-STATE. Once thelockingiscomplete,validserialpayloads aresentacrossthelinktotheDES (DS90UR124). 3. Withpower appliedand thedeviceenabled,theDS90UR124 willlocktotheincomingserialstream.Untilthe DS90UR124 islocked,outputsare in TRI-STATE and itsLOCK outputpin isheld Low. AfterLock,the DS90UR124 outputsareactiveand LOCK isHIGH. DATA TRANSFER Afterthelinkstartup,theDS99R421 providesa streamingvideointerface.Foreach PixelClock(PCLK) received fromtheFPD-LinkInterface21 bitsofinformationarerecoveredalongwiththePCLK. The 21 bitsofinformation includethe18-bitsofRGB informationand thethreevideocontrolsignals(HS, VS and DE). The over-sample controlbitsare alsosampled inthisPCLK domain and appended tothe21 bitsofinformationfora 24-bittotal payload.The Serializersidenow takesthisdataand performsfouroperationstoit.Firstthedataisrandomized, second thedataisscrambled,thirdthedataisbalanced,and finallytheseriallinkcontroland clockembedding is done.The Serializertransmits28 bitsofinformationperpayloadtotheDeserializerperPCLK. See DS90UR241 datasheetforadditionalinformationon theSerializer’s descriptionand operation. The chipsetsupportsPCLK frequencyrangesof5 MHz to43 MHz. At the43MHz PCLK rate,28 bitsare sent acrosstheseriallinkat1.2Gbps.The linkisveryefficient,sending25 bitsofinformation(18 RGB, 3 control,3 over-samplecontrol,and PCLK) with28 serialbits.Thisyields89% efficiency. DS99R421 LINE DRIVER The DS99R421 output(DOUT ±) isused to drivea point-to-pointconnectionas shown inFigure14. The Line drivertransmitsdatawhen thedataenablepin(DEN) isHIGH, thepower down bar(PWDNB) isHIGH, and the deviceislockedtotheincomingFPD-Linkstream.IftheDEN issetLOW, thedeviceremainslocked,butthe driveroutputsare placedinTRI-STATE. Thismaybe used to providea faststartup sincea locktimeisnot required. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS99R421

SNLS264D –JUNE 2007–REVISED APRIL 2013 www.ti.com PRE-EMPHASIS The DS99R421 featuresa Pre-Emphasisfunctionused to compensate forextralong or lossytransmission media. Cable driveisenhanced witha user selectablePre-Emphasisfeaturethatprovidesadditionaloutput currentduringtransitionstocounteractcableloadingeffects.The transmissiondistancewillbe limitedby theloss characteristicsand qualityofthemedia. To enablethePre-Emphasisfunction,the“PRE ” pinrequiresone externalresistor(Rpre)toVss inordertoset theadditionalcurrentlevel.Optionsinclude: Normal Output(nopre-emphasis)– Leave thePRE pinopen Enhanced Output (pre-emphasisenabled)– connecta resistoron the PRE pin to Vss. Values of the PRE Resistorshouldbe between 6K Ohm and 100M Ohm. Valueslessthan6K Ohm shouldnotbe used.The amount of Pre-Emphasisfora givenmedia willdepend on the transmissiondistanceand Fmax of the application.In general,too much Pre-Emphasiscan cause over or undershootat the receiverinputpins.Thiscan resultin excessivenoise,crosstalk,reducedFmax, and increasedpower dissipation.Forshortercablesordistances,Pre- Emphasis istypicallynotbe required.Signalqualitymeasurements shouldbe made attheend oftheapplication cabletoconfirmtheproperamount ofPre-Emphasisforthespecificapplication. The Pre-EmphasiscircuitincreasesthedrivecurrenttoI= 48 /(Rpre).For example ifRpre = 15K Ohm, thenthe Pre-Emphasiscurrentisincreasedby an additional3.2mA. The durationof the currentiscontrolledto preciselyone bitby anothercircuit.Ifmore than one bitvalueis repeatedinthenextcycle(s),thenextbit(s)is“de-emphasized”;Pre-Emphasisisturnedoff(backtothenormal outputcurrentlevel,hence outputlevelisalsoreduced).Thisisdone toreducepower,and toreduceISI(Inter- Symbol Interference). VOD SELECT The SerializerLineDriverDifferentialOutputVoltage(VOD) magnitudeisselectable.Two levelsare provided and are determinedby thestateoftheVODSEL pin.When thispinisLOW, normaloutputlevelsare obtained. For most applicationset the VODSEL pin LOW. When thispin isHIGH, the outputcurrentisincreasedto increasetheVOD level.Use thissettingonlyforextralongcableorhigh-lossinterconnects. OVER-SAMPLED BITS – OS[2:0] Up tothreeadditionalsignalsmaybe sentacrosstheseriallinkperPCLK. The over-sampledbitsarerestrictedto be low speed signalsand shouldbe lessthan 1/5 of the frequencyof the PCLK. The DS99R421 OS[2:0] LVCMOS Inputshave wide hysteresistohelppreventglitches.Signalsshouldconvey levelinformationonly,as pulsewidthdistortionwilloccurby the over samplingtechniqueand locationof the samplingclock.The three oversampled bitsaremapped toDS90UR124 bitsas:OS0 = bit21,OS1 = bit22,and OS2 = bit23.IftheOS bitsarenotrequired,internalpull-downwillbiastheinputtoa LOW. COLOR MAPPING Colormapping isapplicationspecific.Itisvery importantto properlymatch the Pixelbitto the correctdata channelon theDS90UR124 toproperlyrecoverthecolorand controlinformation.See Figure13.Inthisexample, theG0 colorbitisplacedintheRxIN0 channeland isthefirstbit.The SerializerintheDS99R421 willplacethis bitas bitnumber 6.Thus G0 willbe recoveredby theDS90UR124 on bit6.The threeoversampled bitsare mapped toDS90UR124 bitsas:OS0 = bit21,OS1 = bit22,and OS2 = bit23. POWERDOWN (SLEEP) MODE The Powerdown stateisa lowpower sleepmode thattheDS99R421 and DS90UR124 may use toreducepower when no dataisbeingtransferred.The PWDNB on theDS99R421 and RPWDNB on theDS90UR124 areused toseteach deviceintopower down mode, whichreducessupplycurrenttotheµA range.The DS99R421 enters powerdown when the PWDNB pinisdrivenLOW. In powerdown, the PLL stopsand the outputsgo intoTRI- STATE, disablingloadcurrentand reducingcurrentsupply.To powerup,theDS99R421, PWDNB must be driven HIGH. When the DS99R421 exitspowerdown, itsPLL must lock to RxCLKIN beforeitis ready forthe initializationstate.The systemmust thenallowtimeforinitializationbeforedatatransfercan begin.

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www.ti.com SNLS264D –JUNE 2007–REVISED APRIL 2013 SERIAL INTERFACE The seriallinkbetween theDS99R421 and theDS90UR124 isintendedfora balanced100 Ohm interconnect. The linkisexpectedtobe terminatedatbothends with100 Ohms and AC coupled. To establisha sourceterminationand thecorrectlevels,a Driversideterminationisrequired.Thisistypically locatedclosetothedevicepinsand is100 Ohm resistorconnectedacrossthedriveroutputs. The AC couplingcapacitorsshouldbe placecloseto the 100 Ohm terminationresistorat both ends of the interface.For thehigh-speedLVDS transmission,smallfootprintpackages shouldbe used fortheAC coupling capacitor.Thiswillhelpminimizedegradationofsignalqualitydue topackage parasitics.NPO class1 or X7R class2 typecapacitorsare recommended. 50 WVDC shouldbe theminimum used forbestsystem-levelESD performance.The most common used capacitorvaluefortheinterfaceis100 nF (0.1uF)capacitor. The DS90UR124 inputstageisdesignedforAC-couplingby providinga built-inAC biasnetworkwhichsetsthe internalVCM to+1.8V.Thereforemultipleterminationoptionsarepossible. ReceiverTerminationOption 1 A single100 Ohm terminationresistorisplacedacrosstheRIN± pins(seeFigure14).Thisprovidesthesignal terminationattheReceiverinputs.Otheroptionsmay be used toincreasenoisetolerance. ReceiverTerminationOption 2 For additionalEMI tolerance,two 50 Ohm resistorsmay be used inplaceofthesingle100 Ohm resistor.A small capacitoristiedfrom thecenterpointofthe50 Ohm resistorstoground (seeFigure16).Thisprovidesa high- frequencylow-impedancepath fornoise suppression.Value is not critical,4.7nF maybe used withgeneral applications. ReceiverTerminationOption 3 For highnoiseenvironmentsan additionalvoltagedividernetworkmay be connectedtothecenterpoint.This has the advantageof a providinga DC low-impedancepath fornoisesuppression.Use resistorvaluesinthe range of100Ω-1KΩ forthepullupand pulldown.Ratiotheresistorvaluestobiasthecenterpointat1.8V.For example (see Figure17):VDD =3.3V, Rpullup=1KΩ, Rpulldown=1.2KΩ; or Rpullup=100Ω, Rpulldown=120Ω (strongest).The smallervalueswillconsume more biascurrent,butwillprovideenhanced noisesuppression. FPD LINK INTERFACE The FPD-LinkInterfacesupportsa 3 Data + Clock(21bit)interface.The interconnectshouldemploy a 100 Ohm differentialpair,as terminationisprovidedinternalto the DS99R421. Note thatcolormapping isextremely importanttoreview.Colorplacementofthebitson theFPD-LinkInterfacewilldeterminewhichoutputstheywill be recoveredon. The DS99R421 isexpectedto resideon the same board as the FPD-Link Serializer(e.g. DS90C365A or GUI withIntegratedFPD-Link Serializer).The DS99R421 supportsa limitedcommon mode rangeof525mV to(VDD – VID/2).Typicallythisiswideenough tosupportshortinterconnects. @SPEED-BIST (BUILT IN SELF TEST) The DS99R421/ DS90UR124 seriallinkisequipped witha built-inself-test(BIST)capabilityto supportboth systemmanufacturingand fielddiagnostics. BIST mode isintendedtocheck theentirehigh-speedseriallinkatfulllink-speed,withouttheuse ofspecialized and expensivetestequipment.Thisfeatureprovidesa simplemethod fora system hosttoperformdiagnostic testingofbothDS99R421 and DS90UR124. The BIST functioniseasilyconfiguredthroughthe2 controlpins (BISTEN and BISTM) on theDS90UR124 and one controlpin(BISTEN)oftheDS99R421. When theBIST mode isactivated,theDS99R421 has theabilitytotransferan internallygeneratedPRBS datapattern.Thispattern traversesacrossinterconnectinglinkstotheDS90UR124. The DS90UR124 includesan on-chipPRBS pattern verificationcircuitthatchecksthedatapatternforbiterrorsand reportsany errorson thedataoutputpinson the DS90UR124. The @SPEED-BIST featureuses 2 controlpins(BISTEN and BISTM) on the DS90UR124 Deserializer.The BISTEN and BISTM pins togetherdeterminethe functionsof the BIST mode. The BISTEN signal(HIGH) activatesthetestfeatureon theDS90UR124. AftertheBIST mode isenabledon theDS90UR124, togglethe BISTEN pinHIGH on the DS99R421 forthe DS90UR124 Deserializerto startacceptingdata.An inputclock signal(RxCLKIN) fortheDS99R421 must alsobe appliedduringtheentireBIST operation.Data on RxIN[2:0] Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS99R421

SNLS264D –JUNE 2007–REVISED APRIL 2013 www.ti.com and OS[2:0]are ignoredduringoperationof the BIST. The BISTM pinon the DS90UR124 selectsthe error reportingstatusmode oftheBIST function.When BIST isconfiguredintheerrorstatusmode (BISTM = LOW), each oftheROUT[23:0] outputsoftheDS90UR124 willcorrespondtobiterrorson a cycle-by-cyclebasis.The resultofbitmismatchesareindicatedon therespectiveparallelinputson theROUT[23:0]dataoutputpins.Inthe BIST errorcountaccumulatormode (BISTM = HIGH), an 8-bitcounteron ROUT[7:0] isused torepresentthe number oferrorsdetected(0to255 max).The successfulcompletionoftheBIST testisreportedon thePASS pin on the DS90UR124 Deserializer.The DS90UR124 Deserializer'sPLL must firstbe lockedto ensure the PASS statusisvalid.The PASS statuspinwillstayLOW and thentransitiontoHIGH once a BER of1x10-9 is achievedacrossthetransmissionlink.

14 SubmitDocumentationFeedback Copyright© 2007–2013,Texas InstrumentsIncorporated

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www.ti.com SNLS264D –JUNE 2007–REVISED APRIL 2013 APPLICATIONS INFORMATION USING THE DS99R421 AND DS90UR124 The DS99R421 allowsa FPD-Linkbased bus toconnecttoa single-channelserialLVDS interfaceina Display using the latestgenerationLVDS Deserializer(DS90UR124). This allowsforexistinghosts withFPD-Link interfacestobe furtherserializedintoa singlepairand connectwiththecurrentgenerationDisplayDeserializer. Systems benefitby thesmallerinterconnect(reducedpins,lesssize,lowercost). DISPLAY APPLICATION 18-bitcolordepth(RGB666) and up to1280 X 480 displayformatscan be supported.Ina RGB666 configuration 18 colorbits(R[5:0],G [5:0],B[5:0]),PixelClock(PCLK) and threecontrolbits(VS,HS and DE) alongwiththree lowspeed sparebitsOS[2:0]aresupportedacrosstheseriallinkwithPCLK ratesfrom5 to43MHz. TYPICAL APPLICATION CONNECTION Figure15 shows a typicalconnectiontotheDS99R421. The 4 pairsof FPD-Link LVDS interfaceare the inputinterfacealongwiththe optionalover-sampledcontrol signals.TerminationoftheLVDS signalsisprovidedinternallyby theDS99R421 device. The singlechannelLVDS serialoutputrequiresan externalterminationand alsoAC couplingcapacitors. Configurationpinsforthetypicalapplicationareshown:

DEN – tieHIGH ifunused.
PWDNB – Sleep/EnableControlInput– ConnecttohostortieHIGH
BISTEN – tieLOW ifnotused,orconnectorhost
VODSEL – tieLOW fornormalVOD magnitude(applicationdependant)
PRE – Leave open ifnotrequired(havea R pad optionon PCB)
RESRVD – tieLOW (4pins) There are4 power railsforthedevice.These may be bussed togetheron a common 3.3V plane.At a minimum, four0.1uFcapacitorsshouldbe used forlocalbypassing. Withtheabove configurationa FPD-Linkinterfacealongwiththreeadditionallow-speedsignalsareconvertedto a singleserialLVDS channel. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuitboardlayoutand stack-upfortheLVDS SERDES devicesshouldbe designedtoprovidelow-noisepower feed to the device.Good layoutpracticewillalsoseparatehighfrequencyor high-levelinputsand outputsto minimizeunwanted straynoisepickup,feedbackand interference.Power system performancemay be greatly improvedby usingthindielectrics(2to4 mils)forpower /groundsandwiches.Thisarrangementprovidesplane capacitanceforthePCB power system withlow-inductanceparasitics,which has provenespeciallyeffectiveat highfrequencies,and makes thevalueand placementofexternalbypasscapacitorslesscritical.Externalbypass capacitorsshouldincludebothRF ceramicand tantalumelectrolytictypes.RF capacitorsmay use valuesinthe tantalumcapacitorsshouldbe atleast5X thepower supplyvoltagebeingused. Surfacemount capacitorsarerecommended due totheirsmallerparasitics.When usingmultiplecapacitorsper supplypin,locatethesmallervalueclosertothepin.A largebulkcapacitorisrecommend atthepointofpower entry.This is typicallyin the 50uF to 100uF range and willsmooth low frequencyswitchingnoise.Itis recommended toconnectpower and groundpinsdirectlytothepower and groundplaneswithbypass capacitors connectedtotheplanewithviason bothends ofthecapacitor.Connectingpower orgroundpinstoan external bypasscapacitorwillincreasetheinductanceofthepath. A smallbody sizeX7R chipcapacitor,such as 0603,isrecommended forexternalbypass.Itssmallbody size reducesthe parasiticinductanceof the capacitor.The user must pay attentionto the resonancefrequencyof these externalbypass capacitors,usuallyin the range of 20-30 MHz range.To provideeffectivebypassing, multiplecapacitorsare oftenused to achievelow impedance between the supplyrailsover the frequencyof interest.At highfrequency,itisalsoa common practiceto use two viasfrom power and ground pinsto the planes,reducingtheimpedance athighfrequency. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS99R421

(bit20) VSYNC (bit19) HSYNC (bit18) (bit17) (bit16) (bit15) (bit14) G2-1 G1-1 B1 (bit13) (bit12) (bit11) (bit10) (bit9) (bit8) (bit7) R1-1 R0-1 G0 (bit 6) (bit5) (bit4) (bit3) (bit2) (bit1) (bit0) RxIN1 RxIN0 RxIN2 Previous Cycle Current Cycle Next Cycle RxCLKIN (Differential) Vdiff = 0V Vdiff = 0V Vdiff = 0V DS99R421 SNLS264D –JUNE 2007–REVISED APRIL 2013 www.ti.com Some devicesprovideseparatepower and groundpinsfordifferentportionsofthecircuit.Thisisdone toisolate switchingnoiseeffectsbetween differentsectionsof the circuit.Separateplaneson the PCB are typicallynot required.PinDescriptiontablestypicallyprovideguidanceon whichcircuitblocksareconnectedtowhichpower pinpairs.Insome cases,an externalfiltermany be used toprovidecleanpower tosensitivecircuitssuch as PLLs. Use atleasta fourlayerboard witha power and ground plane.LocateLVCMOS signalsaway from theLVDS linesto preventcouplingfrom the LVCMOS linesto the LVDS lines.Closely-coupleddifferentiallinesof 100 Ohms aretypicallyrecommended forLVDS interconnect.The closelycoupledlineshelptoensurethatcoupled noisewillappear as common-mode and thusisrejectedby the receivers.The tightlycoupledlineswillalso radiateless. TerminationoftheLVDS interconnectisrequired.Forpoint-to-pointapplications,terminationshouldbe locatedat both ends of the devices.Nominal valueis100 Ohms to match the line’s differentialimpedance.Place the resistoras closetothetransmitterDOUT ± outputsand receiverRIN± inputsas possibletominimizetheresulting stubbetween theterminationresistorand device. LVDS INTERCONNECT GUIDELINES See AN-1108 (SNLA008 )and AN-905 (SNLA035 )forfulldetails.

Use 100Ω coupleddifferentialpairs
Use theS/2S/3Sruleinseparation – S = space between thepair – 2S = space between pairs – 3S = space toLVCMOS signal
Minimizethenumber ofvias
Use differentialconnectorswhen operatingabove 500Mbps linespeed
Maintainbalanceofthetraces
Minimizeskew withinthepair
Terminateas closetotheTX outputsand RX inputsas possible Additionalgeneralguidancecan be foundintheLVDS Owner ’s Manual - availableinPDF formatfrom theTI web siteat:http://www.ti.com/ww/en/analog/interface/lvds.shtml FunctionalOverview Figure12. FPD-Link LVDS InputMapping (3LVDS Data + 1 LVDS Clock)

ProductFolderLinks:DS99R421

100: 100 nF 100 nF 100: 100 nF 100 nF DOUT- DOUT+ RIN- RIN+ DS99R421 DS90UR124 CLK R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 DCA DCB B0 B1 B2 B3 B4 B5 HSYNCVSYNC DE OS OS OS CLK0 bit0bit1bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit

1 CLK cycle

R T = 100 DOUT+ DS99 R421 100: 100: 100: 100: LVDS DATA0 LVDS DATA1 LVDS DATA2 LVDS CLK (5 MHz to 43 MHz) LVDS NON -DC Balanced OS [2:0] DS99R421 www.ti.com SNLS264D –JUNE 2007–REVISED APRIL 2013 *Note:bits[0-23]arenotphysicallylocatedinpositionsshown above sincebits[0-23]arescrambledand DC Balanced SingleSerializedLVDS Bitstream* Figure13. LVDS Data Mapping Diagram Figure14. AC Coupled Application Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS99R421

0.1 PF 0.1 PF 50: 50: 4.7 nF DS90UR124100: 0.1 PF 0.1 PF DS99R421 PWDNB DEN VODSEL PRE RESRVD(4) DOUT+ DOUT- VSSIN VDDDR VSSDES VSSD VSSSER VSSDR VSSP0 VDDD VDDDES VDDIN Serial LVDS InterfaceVODSEL = L (350 mV) RESRVD = L PRE = open (OFF) or R2 > 6 k:(ON) (cable specific) 3.3V DS99R421 C1 C5 C2 C6 C3 C7 C10 C1 to C4 = 0.1 PF C5 to C8 = 0.01 PF C9, C10 = 100 nF, 50WVDC, NPO or X7R R1 = 100: Serial LVDS Interface BISTEN RxIN0- RxIN0+ RxIN1- RxIN1+ RxIN2- RxIN2+ RxCLKIN- RxCLKIN+ OS0 OS1 OS2 LVCMOS Parallel Interface GPOs if used, or tie Low (OFF) GPOs if used, or tie High (ON) VSSP1 VDDP1 VDDP0 C4 C8 VDDSER 100:100:100:100: DS99R421 SNLS264D –JUNE 2007–REVISED APRIL 2013 www.ti.com Figure15. DS99R421 TypicalApplicationConnection Figure16. ReceiverTerminationOption 2

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0.1 PF 0.1 PF 50: 50: 4.7 nF DS90UR124100: 0.1 PF 0.1 PF DS99R421 R PU VDD R PD DS99R421 www.ti.com SNLS264D –JUNE 2007–REVISED APRIL 2013 Figure17. ReceiverTerminationOption 3 Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DS99R421

SNLS264D –JUNE 2007–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionC (April2013)toRevisionD Page

ProductFolderLinks:DS99R421

www.ti.com 16-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples DS99R421ISQ/NOPB NRND WQFN NJK 36 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 99R421I DS99R421ISQX/NOPB NRND WQFN NJK 36 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 99R421I DS99R421QSQ/NOPB ACTIVE WQFN NJK 36 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 99R421Q DS99R421QSQX/NOPB ACTIVE WQFN NJK 36 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 99R421Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 16-Apr-2013 Addendum-Page 2 OTHER QUALIFIED VERSIONS OF DS99R421, DS99R421-Q1 :

Catalog: DS99R421
Automotive: DS99R421-Q1 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2014 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS99R421ISQ/NOPB WQFN NJK 36 250 213.0 191.0 55.0 DS99R421ISQX/NOPB WQFN NJK 36 2500 367.0 367.0 38.0 DS99R421QSQ/NOPB WQFN NJK 36 250 213.0 191.0 55.0 DS99R421QSQX/NOPB WQFN NJK 36 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2014 Pack Materials-Page 2

www.ti.com SQA36A (Rev A)

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