DS99R124QSQX

DS99R124Q NSC | Alldatasheet

Document overview

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Technical content

Features

■ 5 – 43 MHz support (140 Mbps to 1.2 Gbps Serial Link) ■ 4-channel (3 data + 1 clock) FPD-Link LVDS outputs ■ 3 low-speed over-sampled LVCMOS outputs ■ AC Coupled STP Interconnect up to 10 meters in length ■ Integrated input termination ■ @ Speed link BIST mode and reporting pin ■ Optional I2C compatible Serial Control Bus ■ RGB666 + VS, HS, DE converted from 1 pair ■ Power down mode minimizes power dissipation ■ FAST random data lock; no reference clock required ■ Adjustable input receive equalization ■ LOCK (real time link status) reporting pin ■ Low EMI FPD-Link output ■ SSCG option for lower EMI ■ 1.8V or 3.3V compatible I/O interface ■ Automotive grade product: AEC-Q100 Grade 2 qualified ■ >8 kV HBM and ISO 10605 ESD Rating

Applications

■ Automotive Display for Navigation ■ Automotive Display for Entertainment Applications Diagram 30105227 TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2010 National Semiconductor Corporation 301052 www.national.com DS99R124Q 5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

FPD-Link II to FPD-Link Convertor - DS99R124Q Pin Descriptions Pin Name Pin # I/O, Type Description FPD-Link II Input Interface RIN+ 40 I, LVDS True input The input must be AC coupled with a 100 nF capacitor. Internal termination. RIN- 41 I, LVDS Inverting input The input must be AC coupled with a 100 nF capacitor. Internal termination. CMF 42 I, Analog Common-Mode Filter VCM center-tap is a virtual ground which maybe ac-coupled to ground to increase receiver common mode noise immunity. Recommended value is 4.7 μF or higher. FPD-Link Output Interface TxOUT[2:0]+ 19, 21, 23 O, LVDS True LVDS Data Output This pair should have a 100 Ω termination for standard LVDS levels. TxOUT[2:0]- 20, 22, 24 O, LVDS Inverting LVDS Data Output This pair should have a 100 Ω termination for standard LVDS levels. TxCLKOUT+ 17 O, LVDS True LVDS Clock Output This pair should have a 100 Ω termination for standard LVDS levels. TxCLKOUT- 18 O, LVDS Inverting LVDS Clock Output This pair should have a 100 Ω termination for standard LVDS levels. www.national.com 2 DS99R124Q

Pin Name Pin # I/O, Type Description LVCMOS Outputs OS[2:0] 10, 11, 12 O, LVMOS Over-Sampled Low Frequency Outputs These bits map to the DS99R421's OS[2:0] over-sampled low-frequency inputs. Signals must be slower the TxCLK/5. On the DS90UR241 these map to the DIN[23:21] inputs. OS0 = DIN21, OS1 = DIN22, OS2 = DIN23. LOCK 27 O, LVMOS LOCK Status Output LOCK = 1, PLL is locked, outputs are active. LOCK = 0, PLL is unlocked, output states determined by OSS_SEL. Maybe used as a Link Status or to flag when the Video Data is active (ON/OFF). Control and Configuration PDB 1 I, LVCMOS w/ pull-down Power Down Mode Input PDB = 1, Device is enabled (normal operation) PDB = 0, Device is in power-down, the output are controlled by the settings. Control registers are RESET. VODSEL 33 I, LVCMOS w/ pull-down Differential Driver Output Voltage Select VODSEL = 1, LVDS VOD is ±400 mV, 800 mVp-p (typ) — Long Cable / De-E Applications VODSEL = 0, LVDS VOD is ±250 mV, 500 mVp-p (typ) SeeTable 2 OEN 34 I, LVCMOS w/ pull-down Output Enable Input OEN = 1, FPD-Link outputs are enabled (active). OEN = 0, FPD-Link outputs are TRI-STATE. OSS_SEL 35 I, LVCMOS w/ pull-down Output Sleep State Select Input See Table 1 LFMODE 36 I, LVCMOS w/ pull-down Low Frequency Mode — Pin or Register Control LF_MODE = 1, low frequency mode (TxCLKOUT = 5-20 MHz) LF_MODE = 0, high frequency mode (TxCLKOUT = 20-43 MHz) SSC[2:0] 7, 2, 3 I, LVCMOS w/ pull-down Spread Spectrum Clock Generation (SSCG) Range Select SeeTable 3 and Table 4 RES[1:0] 37, 15 I, LVCMOS w/ pull-down Reserved Tie Low Control and Configuration — STRAP PIN For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pin is read upon power-up and set device configuration. Pin number listed along with shared LVCMOS Output name in square bracket. EQ 28 [PASS] STRAP I, LVCMOS w/ pull-down EQ Gain Control of FPD-Link II Input EQ = 1, EQ gain is enabled (~13 dB) EQ = 0, EQ gain is disabled (~1.625 dB) Optional BIST Mode BISTEN 29 I, LVCMOS w/ pull-down BIST Enable Input – Optional BISTEN = 1, BIST Mode is enabled. BISTEN = 0, normal mode. BISTM 30 I, LVCMOS w/ pull-down BIST Mode Input – Optional BISTM = 1, selects Payload Error Mode BISTM = 0, selects Pass / Fail Result-Only Mode PASS 28 O, LVCMOS PASS Output (BIST Mode) – Optional PASS = 1, no errors detected PASS = 0, errors detected Leave open if unused. Route to a test point (pad) recommended. Optional Serial Bus Control Interface SCL 5 I, LVCMOS Serial Control Bus Clock Input - Optional SCL requires an external pull-up resistor to VDDIO. SDA 4 I/O, LVCMOS Open Drain Serial Control Bus Data Input / Output - Optional SDA requires an external pull-up resistor to VDDIO. 3 www.national.com DS99R124Q

Pin Name Pin # I/O, Type Description ID[x] 16 I, Analog Serial Control Bus Device ID Address Select — Optional Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 5. Power and Ground VDDL 6, 31 Power Logic Power, 1.8 V ±5% VDDA 38, 43 Power Analog Power, 1.8 V ±5% VDDP 8, 46, 47 Power SSC Generator Power, 1.8 V ±5% VDDTX 13 Power FPD-Link Power, 3.3 V ±10% VDDIO 25 Power LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% GND 9, 14, 26, 32, 39, 44, 45, 48 Ground Ground DAP DAP Ground DAP is the large metal contact at the bottom side, located at the center of the LLP package. Connected to the ground plane (GND) with at least 9 vias. NOTE: 1 = HIGH, 0 = LOW

Ordering Information

DS99R124QSQE 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch 250 NOPB SQA48A DS99R124QSQ 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch 1000 NOPB SQA48A DS99R124QSQX 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch 2500 NOPB SQA48A Note: Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades defined in the AEC Q100 standard. Automotive Grade products are identified with the letter Q. For more information go to http://www.national.com/automotive. Block Diagram 30105229 FPD-Link II to FPD-Link Convertor www.national.com 4 DS99R124Q

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – VDDn (1.8V) −0.3V to +2.5V Supply Voltage – VDDTX (3.3V) −0.3V to +4.0V Supply Voltage – VDDIO −0.3V to +4.0V LVCMOS I/O Voltage −0.3V to +(VDDIO + 0.3V) Receiver Input Voltage −0.3V to (VDD + 0.3V) LVDS Output Voltage −0.3V to (VDDTX + 0.3V) Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4s) +260°C Maximum Power Dissipation Capacity at 25°C Derate above 25°C 1/ θJA°C/W θJA 27.7 °C/W θJC 3.0 °C/W ESD Rating (IEC, powered-up only), RD = 330Ω, CS = 150pF Air Discharge (RIN+, RIN−) ≥±30 kV Contact Discharge (RIN+, RIN−) ≥±6 kV ESD Rating (ISO10605), RD = 330Ω, CS = 150 & 330pF Air Discharge (RIN+, RIN−) ≥±15 kV Contact Discharge (RIN+, RIN−) ≥±8 kV ESD Rating (ISO10605), RD = 2kΩ, CS = 150 & 330pF Air Discharge (RIN+, RIN−) ≥±15 kV Contact Discharge (RIN+, RIN−) ≥±8 kV ESD Rating (HBM) ≥±8 kV ESD Rating (CDM) ≥±1.25 kV ESD Rating (MM) ≥±250 V Recommended Operating Conditions Min Nom Max Units Supply Voltage (VDDn) 1.71 1.8 1.89 V LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 V LVCMOS Supply Voltage (VDDIO) 3.0 3.3 3.6 V Operating Free Air Temperature (T A) −40 +25 +105 °C TxCLK Clock Frequency 5 43 MHz Supply Noise (Note 7) 100 mVP-P Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 3) and (Note 4) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units FPD-Link LVDS Output |VOD| Differential Output Voltage RL = 100Ω VODSEL = L TxCLKOUT+, TxCLKOUT-, TxOUT[2:0]+, TxOUT[2:0]- 100 250 400 mV VODSEL = H 200 400 600 mV VODp-p Differential Output Voltage A-B VODSEL = L 500 mVp-p VODSEL = H 800 mVp-p ΔVOD Output Voltage Unbalance 1 50 mV VOS Offset Voltage VODSEL = L 1.0 1.2 1.5 V VODSEL = H 1.2 V ΔVOS Offset Voltage Unbalance 1 50 mV IOS Output Short Circuit Current Vout = GND -5 mA IOZ Output TRI-STATE® Current OEN = GND, Vout =VDDTX, or GND -10 +10 µA 3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V VIH High Level Input Voltage PDB, VODSEL, OEN, OSS_SEL, LFMODE, SSC[2:0], BISTEN, BISTM

2.2 VDDIO V

VIL Low Level Input Voltage GND 0.8 V IIN Input Current VIN = 0V or VDDIO −15 ±1 +15 μA 5 www.national.com DS99R124Q

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units VOH High Level Output Voltage IOH = −0.5 mA LOCK, PASS, OS [2:0] VDDIO-

0.2 VDDIO V

VOL Low Level Output Voltage IOL = +0.5 mA GND 0.2 V IOS Output Short Circuit Current VOUT = 0V -10 mA IOZ TRI-STATE® Output Current PDB = 0V, OSS_SEL = 0V, VOUT = 0V or VDDIO −10 +10 µA 1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V VIH High Level Input Voltage PDB, VODSEL, OEN, OSS_SEL, LFMODE, SSC[2:0], BISTEN, BISTM 0.7 VDDIO VDDIO V VIL Low Level Input Voltage GND 0.35* VDDIO V IIN Input Current VIN = 0V or VDDIO −10 ±1 +10 μA VOH High Level Output Voltage IOH = −0.1 mA LOCK, PASS, OS [2:0] VDDIO - 0.2 VDDIO V VOL Low Level Output Voltage IOL = +0.1 mA GND 0.2 V IOS Output Short Circuit Current VOUT = 0V -3 mA IOZ TRI-STATE Output Current VOUT = 0V or VDDIO -15 +15 µA FPD-Link II LVDS RECEIVER DC SPECIFICATIONS VTH Differential Input Threshold High Voltage VCM = +1.2V (Internal VBIAS) RIN+, RIN- +50 mV VTL Differential Input Threshold Low Voltage −50 mV VCM Common Mode Voltage, Internal VBIAS 1.2 V RT Input Termination 75 80 92 Ω SUPPLY CURRENT IDD1 Supply Current (includes load current)

43 MHz Clock

Pattern, VODSEL = H, SSCG = On Figure 1 VDDn= 1.89V All VDD(1.8) pins 70 80 mA IDDTX1 VDDTX = 3.6V VDDTX 30 40 mA IDDIO1 VDDIO=1.89V VDDIO 0.35 1 mA VDDIO = 3.6V 1 1.5 mA IDDZ Supply Current Power Down PDB = 0V, All other LVCMOS Inputs = 0V VDD= 1.89V All VDD(1.8) pins 0.15 4 mA IDDTXZ VDDTX = 3.6V VDDTX 0.01 0.05 mA IDDIOZ VDDIO=1.89V VDDIO 0.1 0.4 mA VDDIO = 3.6V 0.4 0.8 mA www.national.com 6 DS99R124Q

TABLE 1. Output State Table controlled by the VODSEL input. TABLE 2. VODSEL Configuration Table outputs are modulated. This will aid to lower system EMI.

1. This feature may be controlled by pins or by register. The

TABLE 3. SSCG Configuration (LFMODE = L) — Des Output TABLE 4. SSCG Configuration (LFMODE = H) — Des Output FIGURE 16. SSCG Waveform PCLK output states are determined by the OSS_SEL status. to flag any payloads that are received with 1 to 24 bit errors. The BISTM pin selects the operational mode of the PASS pin.

TABLE 6. DS99R124Q — Serial Bus Control Registers

6 R/W 0 OSS_SEL Output Sleep State Select

5 R/W 0 Reserved Reserved

4 R/W 0 Reserved Reserved

1 R/W 0 SLEEP Note – not the same function as PowerDown (PDB)

1: Sleep Mode – Register settings retained.

0 R/W 0 REG Control 0: Configurations set from control pins

All other addresses are Reserved.

6 R/W 0 Reserved Reserved

3 R/W 0 VODSEL Differential Driver Output Voltage Select

(dec) ADD (hex) Register Name Bit(s) R/W Defa ult (bin) Function Description 3 3 Des Features 2 7:5 R/W 000 EQ Gain 000: ~1.625 dB 001: ~3.25 dB 010: ~4.87 dB 011: ~6.5 dB 100: ~8.125 dB 101: ~9.75 dB 110: ~11.375 dB 111: ~13 dB

4 R/W 0 EQ Enable 0: EQ = disabled

1: EQ = enabled

3 R/W 0 Reserved Reserved

2:0 R/W 000 SSC IF LFMODE = 0, then: 000: SSCG OFF 001: fdev = ±0.9%, fmod = CLK/2168 010: fdev = ±1.2%, fmod = CLK/2168 011: fdev = ±1.9%, fmod = CLK/2168 100: fdev = ±2.3%, fmod = CLK/2168 101: fdev = ±0.7%, fmod = CLK/1300 110: fdev = ±1.3%, fmod = CLK/1300 111: fdev = ±1.57%, fmod = CLK/1300 IF LFMODE = 1, then: 000: SSCG OFF 001: fdev = ±0.7%, fmod = CLK/625 010: fdev = ±1.3%, fmod = CLK/625 011: fdev = ±1.8%, fmod = CLK/625 100: fdev = ±2.2%, fmod = CLK/625 101: fdev = ±0.7%, fmod = CLK/385 110: fdev = ±1.2%, fmod = CLK/385 111: fdev = ±1.7%, fmod = CLK/385 www.national.com 20 DS99R124Q

Power Up Requirements and PDB Pin The VDD (V DDn), VDDTX and V DDIO supply ramps should be faster than 1.5 ms with a monotonic rise. Supplies may power up in any order, however device operation should be initiated only after all supplies are in their valid operating ranges. The optional serial bus address selection is done upon power up also. Thus, if using this optional feature, the PDB signal must be delayed to allow time for the ID setting to occur. The delay maybe done by simply holding the PDB pin at a Low, or with an external RC delay based off the VDDIO rail which would then need to lag the others in time. If the PDB pin is pulled to VDDIO, it is recommended to use a 10 kΩ pull-up and a 22 uF cap to GND to delay the PDB input signal. TRANSMISSION MEDIA The Ser/Des chipset is intended to be used in a point-to-point configuration, through a PCB trace, or through twisted pair cable. The Ser and Des provide internal terminations provid- ing a clean signaling environment. The interconnect for LVDS should present a differential impedance of 100 Ohms. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Shielded or un-shielded cables may be used depending upon the noise environment and application requirements. LIVE LINK INSERTION The Ser and Des devices support live pluggable applications. The automatic receiver lock to random data “plug & go” hot insertion capability allows the DS99R124Q to attain lock to the active data stream during a live insertion event. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the LVDS Ser/Des de- vices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high fre- quency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin di- electrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven es- pecially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. Ex- ternal bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used. Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50uF to 100uF range and will smooth low fre- quency switching noise. It is recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor will increase the inductance of the path. A small body size X7R chip capacitor, such as 0603, is rec- ommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20-30 MHz. To provide ef- fective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the fre- quency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switch- ing noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cas- es, an external filter many be used to provide clean power to sensitive circuits such as PLLs. Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely- coupled differential lines of 100 Ohms are typically recom- mended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise will appear as common- mode and thus is rejected by the receivers. The tightly cou- pled lines will also radiate less. Information on the LLP style package is provided in National Application Note: AN-1187. LVDS INTERCONNECT GUIDELINES See AN-1108 and AN-905 for full details.

• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings – S = space between the pair – 2S = space between pairs – 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the National web site at: www.national.com/lvds www.national.com 22 DS99R124Q

Physical Dimensions inches (millimeters) unless otherwise noted 48–pin LLP Package (7.0 mm x 7.0 mm x 0.8 mm, 0.5 mm pitch) 23 www.national.com DS99R124Q

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