DS99R124QSQ/NOPB

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5 - 43 MHz 18-bit Color FPD-Link II to FPD-Link Converter

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www.ti.com SNLS318D –JANUARY 2010–REVISED APRIL 2013 DS99R124Q5-43MHz18-bitColorFPD-LinkIItoFPD-LinkConverter Check forSamples: DS99R124Q 1FEATURES DESCRIPTION The DS99R124Q convertsFPD-LinkIItoFPD-Link.It 2• 5 – 43 MHz Support (140Mbps to1.2Gbps translatesa high-speedserializedinterfacewithanSerialLink) embedded clockover a singlepair(FPD-LinkII)to• 4-Channel(3data+ 1 Clock)FPD-Link LVDS threeLVDS data/controlstreamsand one LVDS clock Outputs pair(FPD-Link).Thisserialbus scheme greatlyeases system designby eliminatingskew problemsbetween• 3 Low-Speed Over-Sampled LVCMOS Outputs clockand data,reduces the number of connector• AC Coupled STP Interconnectup to10 Meters pins,reducestheinterconnectsize,weight,and cost,inLength and overalleases PCB layout.In addition,internal

IntegratedInputTermination DC balanceddecodingisused tosupportAC-coupled interconnects.• @ Speed LinkBIST Mode and ReportingPin
OptionalI2C Compatible SerialControlBus The DS99R124Q converterrecoversthedata(RGB) and controlsignalsand extractsthe clockfrom a• RGB666 + VS, HS, DE Converted from 1 Pair serialstream (FPD-LinkII).Itisable to lockto the• Power Down Mode MinimizesPower incomingdata stream withoutthe use of a trainingDissipation sequence or specialSYNC patternsand does not
FAST Random Data Lock; no ReferenceClock requirea referenceclock.A linkstatus(LOCK) output Required signalisprovided.
AdjustableInputReceive Equalization Adjustableinput equalizationof the serialinput stream provides compensation for transmission• LOCK (RealTime LinkStatus)ReportingPin medium lossesofthecableand reducesthemedium-• Low EMI FPD-Link Output induceddeterministicjitter.EMI isminimizedby the• SSCG Option forLower EMI use of low voltagedifferentialsignaling,outputstate
1.8Vor 3.3VCompatible I/OInterface selectfeature,and additionaloutputspreadspectrum generation.• Automotive Grade Product:AEC-Q100 Grade 2 Qualified With fewer wires to the physicalinterfaceof the display,FPD-Link outputwith LVDS technologyis• >8 kV HBM and ISO 10605 ESD Rating idealforhigh speed, low power and low EMI data transfer.APPLICATIONS The DS99R124Q is offeredin a 48-pin WQFN• Automotive DisplayforNavigation package and isspecifiedover the automotiveAEC-• Automotive DisplayforEntertainment Q100 Grade 2 temperaturerangeof-40˚C to+105˚C. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2010–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

DAP = GND GND VDDP GND GND RIN- RIN+ VDDA RES[1] VDDTX GND ID[x] TxCLKOUT+ TxOUT2- TxOUT1+ TxOUT0+ TxOUT0- GND CMF VDDA VDDP RES[0] TxCLKOUT- TxOUT2+ TxOUT1- PDB SSC[0] OS[2] OS[0] SSC[1] OSS_SEL OEN VODSEL GND VDDL BISTM BISTEN PASS/ EQ LOCK GND LFMODE SSC[2] VDDP OS[1] VDDIO GND SDA SCL VDDL PWDNB 100 ohm STP Cable PASS PDB LFMODE BISTEN LOCK RGB Style Display Interface RGB Display QVGA to WVGA 18-bit Color Depth DS99R421Q Converter DS99R124Q Converter High-Speed Serial Link

1 Pair/AC Coupled

SSC[2:0] OEN VODSEL BISTM OSSEL 3.3V FPD-Link II FPD-Link CMF FPD-Link RxIN1+/- RxCLKIN+/- RxIN2+/- RxIN0+/- TxOUT1+/- TxCLKOUT+/- TxOUT2+/- TxOUT0+/- 3.3V VDDIO (1.8V or 3.3V) 1.8V SDA ID[x] SCL Optional HOST Graphics Processor DOUT+ DOUT- RIN+ RIN- OS[2:0] VODSEL DEN BISTEN PRE OS[2:0] DS99R124Q SNLS318D –JANUARY 2010–REVISED APRIL 2013 www.ti.com ApplicationsDiagram Figure1. DS99R124Q Pin Diagram Figure2. FPD-Link IItoFPD-Link Convertor-DS99R124Q

48 Pin WQFN Package

See Package Number RHS0048A

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www.ti.com SNLS318D –JANUARY 2010–REVISED APRIL 2013 PIN DESCRIPTIONS Pin Name Pin # I/O,Type Description FPD-Link IIInputInterface RIN+ 40 I,LVDS Trueinput The inputmust be AC coupledwitha 100 nF capacitor.Internaltermination. RIN- 41 I,LVDS Invertinginput The inputmust be AC coupledwitha 100 nF capacitor.Internaltermination. CMF 42 I,Analog Common-Mode Filter VCM center-tapisa virtualgroundwhichmaybe ac-coupledtogroundtoincreasereceiver common mode noiseimmunity.Recommended valueis4.7μF orhigher. FPD-Link Output Interface TxOUT[2:0]+ 19,21,23 O, LVDS TrueLVDS Data Output Thispairshouldhave a 100 Ω terminationforstandardLVDS levels. TxOUT[2:0]- 20,22,24 O, LVDS InvertingLVDS Data Output Thispairshouldhave a 100 Ω terminationforstandardLVDS levels. TxCLKOUT+ 17 O, LVDS TrueLVDS ClockOutput Thispairshouldhave a 100 Ω terminationforstandardLVDS levels. TxCLKOUT- 18 O, LVDS InvertingLVDS ClockOutput Thispairshouldhave a 100 Ω terminationforstandardLVDS levels. LVCMOS Outputs OS[2:0] 10,11,12 O, LVMOS Over-SampledLow FrequencyOutputs These bitsmap totheDS99R421's OS[2:0]over-sampledlow-frequencyinputs.Signalsmust be slowertheTxCLK/5.On theDS90UR241 thesemap totheDIN[23:21]inputs.OS0 = DIN21,OS1 = DIN22,OS2 = DIN23. LOCK 27 O, LVMOS LOCK StatusOutput LOCK = 1,PLL islocked,outputsareactive. LOCK = 0,PLL isunlocked,outputstatesdeterminedby OSS_SEL. Maybe used as a LinkStatusortoflagwhen theVideoData isactive(ON/OFF). Controland Configuration PDB 1 I,LVCMOS Power Down Mode Input w/ pull-down PDB = 1,Deviceisenabled(normaloperation) PDB = 0,Deviceisinpower-down,theoutputarecontrolledby thesettings.Controlregisters areRESET . VODSEL 33 I,LVCMOS DifferentialDriverOutputVoltageSelect w/ pull-down VODSEL = 1,LVDS VOD is±400 mV, 800 mVp-p (typ)— Long Cable/De-E Applications VODSEL = 0,LVDS VOD is±250 mV, 500 mVp-p (typ) See Table2 OEN 34 I,LVCMOS OutputEnableInput w/ pull-down OEN = 1,FPD-Linkoutputsareenabled(active). OEN = 0,FPD-LinkoutputsareTRI-STATE. OSS_SEL 35 I,LVCMOS OutputSleepStateSelectInput w/ pull-down See Table1 LFMODE 36 I,LVCMOS Low FrequencyMode — PinorRegisterControl w/ pull-down LF_MODE = 1,lowfrequencymode (TxCLKOUT = 5-20MHz) LF_MODE = 0,highfrequencymode (TxCLKOUT = 20-43MHz) SSC[2:0] 7,2,3 I,LVCMOS Spread SpectrumClockGeneration(SSCG) Range Select w/ pull-down See Table3 and Table4 RES[1:0] 37,15 I,LVCMOS Reserved w/ pull-down TieLow Controland Configuration— STRAP PIN Fora HighState,use a 10 kΩ pullup toVDDIO; fora Low State,theIO includesan internalpulldown. The STRAP pinisreadupon power- up and setdeviceconfiguration.Pinnumber listedalongwithsharedLVCMOS Outputname insquarebracket. EQ 28 [PASS] STRAP EQ Gain ControlofFPD-LinkIIInput I,LVCMOS EQ = 1,EQ gainisenabled(~13dB) w/ pull-down EQ = 0,EQ gainisdisabled(~1.625dB) OptionalBIST Mode BISTEN 29 I,LVCMOS BIST EnableInput– Optional w/ pull-down BISTEN = 1,BIST Mode isenabled. BISTEN = 0,normalmode. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS99R124Q

DS99R124Q ± CONVERTER RIN+ PLLTiming and Control LOCK OS[2:0] SSCG Serializer Serial to Parallel DC Balance Decoder PASS SSC[2:0] OEN VODSEL TxOUT[2] Error Detector PDB BISTEN CMF SCL SCA ID[x] TxOUT[1] TxOUT[0] TxCLKOUT BISTM OSS_SEL LFMODE DS99R124Q SNLS318D –JANUARY 2010–REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Name Pin # I/O,Type Description BISTM 30 I,LVCMOS BIST Mode Input– Optional w/ pull-down BISTM = 1,selectsPayloadErrorMode BISTM = 0,selectsPass /FailResult-OnlyMode PASS 28 O, LVCMOS PASS Output(BISTMode) – Optional PASS = 1,no errorsdetected PASS = 0,errorsdetected Leave open ifunused.Route toa testpoint(pad)recommended. OptionalSerialBus ControlInterface SCL 5 I,LVCMOS SerialControlBus ClockInput-Optional SCL requiresan externalpull-upresistortoVDDIO . SDA 4 I/O,LVCMOS SerialControlBus Data Input/Output-Optional Open Drain SDA requiresan externalpull-upresistortoVDDIO . ID[x] 16 I,Analog SerialControlBus DeviceID AddressSelect— Optional ResistortoGround and 10 kΩ pull-upto1.8Vrail.See Table5. Power and Ground VDDL 6,31 Power LogicPower,1.8V ±5% VDDA 38,43 Power AnalogPower,1.8V ±5% VDDP 8,46,47 Power SSC GeneratorPower,1.8V ±5% VDDTX 13 Power FPD-LinkPower,3.3V ±10% VDDIO 25 Power LVCMOS I/OPower,1.8V ±5% OR 3.3V ±10% GND 9,14,26, Ground Ground 32,39,44, 45,48 DAP DAP Ground DAP isthelargemetalcontactatthebottomside,locatedatthecenteroftheWQFN package.Connected totheground plane(GND) withatleast9 vias. Block Diagram Figure3. FPD-Link IItoFPD-Link Convertor These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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www.ti.com SNLS318D –JANUARY 2010–REVISED APRIL 2013 AbsoluteMaximum Ratings(1)(2) SupplyVoltage– VDDn (1.8V) −0.3Vto+2.5V SupplyVoltage– VDDTX (3.3V) −0.3Vto+4.0V SupplyVoltage– VDDIO −0.3Vto+4.0V LVCMOS I/OVoltage −0.3Vto+(VDDIO + 0.3V) ReceiverInputVoltage −0.3Vto(VDD + 0.3V) LVDS OutputVoltage −0.3Vto(VDDTX + 0.3V) JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature (Soldering,4s) +260°C Maximum Power DissipationCapacityat Derateabove 25°C 1/θJA°C/W 25°C θJA 27.7°C/W θJC 3.0°C/W ESD Rating(IEC,powered-uponly),R D = AirDischarge(RIN+,R IN−) ≥±30 kV 330Ω,C S = 150pF ContactDischarge(RIN+,R IN−) ≥±6 kV ESD Rating(ISO10605),R D = 330Ω,C S = AirDischarge(RIN+,R IN−) ≥±15 kV 150 & 330pF ContactDischarge(RIN+,R IN−) ≥±8 kV ESD Rating(ISO10605),R D = 2kΩ,C S = 150 AirDischarge(RIN+,R IN−) ≥±15 kV & 330pF ContactDischarge(RIN+,R IN−) ≥±8 kV ESD Rating(HBM) ≥±8 kV ESD Rating(CDM) ≥±1.25kV ESD Rating(MM) ≥±250 V (1) “AbsoluteMaximum Ratings”indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingConditions Min Nom Max Units SupplyVoltage(VDDn ) 1.71 1.8 1.89 V LVCMOS SupplyVoltage(VDDIO ) 1.71 1.8 1.89 V LVCMOS SupplyVoltage(VDDIO ) 3.0 3.3 3.6 V OperatingFreeAirTemperature(TA) −40 +25 +105 °C TxCLK ClockFrequency 5 43 MHz SupplyNoise(1) 100 mV P-P (1) Supplynoisetestingwas done withminimum capacitorson thePCB. A sinusoidalsignalisAC coupledtotheVDDn (1.8V)supplywith amplitude= 100 mVp-p measured atthedeviceVDDn pins.BiterrorratetestingofinputtotheSer and outputoftheDes with10 meter cableshows no errorwhen thenoisefrequencyon theSer islessthan750 kHz.The Des on theotherhand shows no errorwhen the noisefrequencyislessthan400 kHz. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS99R124Q

SNLS318D –JANUARY 2010–REVISED APRIL 2013 www.ti.com DC ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2)(3) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units FPD-Link LVDS Output VODSEL = L 100 250 400 mVDifferential|VOD | OutputVoltage VODSEL = H 200 400 600 mV Differential VODSEL = L 500 mVp-p VODp-p OutputVoltage VODSEL = H 800 mVp-pA-B TxCLKOUT+,OutputVoltage R L = 100ΩΔVOD 1 50 mVTxCLKOUT-,Unbalance TxOUT[2:0]+, VODSEL = L 1.0 1.2 1.5 VTxOUT[2:0]-VOS OffsetVoltage VODSEL = H 1.2 V OffsetVoltageΔVOS 1 50 mVUnbalance OutputShortIOS Vout= GND -5 mACircuitCurrent OutputTRI- OEN = GND,IOZ STATE -10 +10 µAVout=VDDTX ,orGNDCurrent 3.3V I/OLVCMOS DC SPECIFICATIONS – VDDIO = 3.0to3.6V HighLevel PDB,VIH 2.2 VDDIO VInputVoltage VODSEL, OEN,Low LevelVIL GND 0.8 VOSS_SEL,InputVoltage LFMODE, SSC[2:0], IIN InputCurrent VIN = 0V orVDDIO −15 ±1 +15 μABISTEN, BISTM HighLevelVOH IOH = −0.5mA VDDIO -0.2 VDDIO VOutputVoltage Low LevelVOL IOL = +0.5mA GND 0.2 VOutputVoltage LOCK, PASS, OS[2:0]OutputShortIOS VOUT = 0V -10 mACircuitCurrent TRI-STATE PDB = 0V,OSS_SEL = 0V,IOZ −10 +10 µAOutputCurrent VOUT = 0V orVDDIO 1.8V I/OLVCMOS DC SPECIFICATIONS – VDDIO = 1.71to1.89V HighLevel PDB, 0.7VIH VDDIO VInputVoltage VODSEL, VDDIO OEN,Low Level 0.35*VIL GND VOSS_SEL,InputVoltage VDDIOLFMODE, SSC[2:0], IIN InputCurrent VIN = 0V orVDDIO −10 ±1 +10 μABISTEN, BISTM (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms atVDDn = 1.8V,VDDTX = 3.3V,VDDIO = 1.8Vor3.3V,Ta = +25 °C, and atthe Recommended OperationConditionsatthetimeofproductcharacterizationand arenotensured. (3) Currentintodevicepinsisdefinedas positive.Currentoutofa devicepinisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages.

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www.ti.com SNLS318D –JANUARY 2010–REVISED APRIL 2013 DC ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2)(3) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units HighLevel VDDIOVOH IOH = −0.1mA VDDIO VOutputVoltage -0.2 Low LevelVOL IOL = +0.1mA GND 0.2 VOutputVoltage LOCK, PASS, OS[2:0]OutputShortIOS VOUT = 0V -3 mACircuitCurrent TRI-STATEIOZ VOUT = 0V orVDDIO -15 +15 µAOutputCurrent FPD-Link IILVDS RECEIVER DC SPECIFICATIONS Differential InputVTH +50 mVThresholdHigh Voltage VCM = +1.2V (InternalVBIAS) Differential InputVTL −50 mVThresholdLow RIN+,RIN- Voltage Common VCM Mode Voltage, 1.2 V InternalVBIAS InputR T 75 80 92 ΩTermination SUPPLY CURRENT IDDIOZ VDDIO VDDIO = 3.6V 0.4 0.8 mA SwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units FPD-Link II tDDLT Lock Time(3) SSCG = Off 5 MHz 6 ms SSCG = On 5 MHz 14 ms SSCG = Off 43 MHz 5 ms SSCG = On 43 MHz 8 ms tDJIT InputJitterTolerance EQ = Off JitterFrequency> 10 MHz >0.45 UI Figure14 FPD-Link Output (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms atVDDn = 1.8V,VDDTX = 3.3V,VDDIO = 1.8Vor3.3V,Ta = +25 °C, and atthe Recommended OperationConditionsatthetimeofproductcharacterizationand arenotensured. (3) tDDLT isthetimerequiredby thedeserializertoobtainlockwhen exitingpower-down statewithan activePCLK. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS99R124Q

SNLS318D –JANUARY 2010–REVISED APRIL 2013 www.ti.com SwitchingCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tTLHT Low toHighTransitionTime R L = 100Ω TxCLKOUT ±, 0.3 0.6 ns TxOUT[2:0]±tTHLT HightoLow TransitionTime 0.3 0.6 ns tDCCJ Cycle-to-CycleOutputJitter(4)(5) TxCLKOUT = 5 MHz TxCLKOUT ± 900 2100 ps TxCLKOUT = 43 MHz 75 125 ps tTTP1 TransmitterPulsePositionfor TxOUT[2:0]± 0 UIbit1 tTTP0 TransmitterPulsePositionfor 1 UIbit0 tTPP6 TransmitterPulsePositionfor 2 UIbit6 tTTP5 TransmitterPulsePositionfor 3 UIbit5 tTTP4 TransmitterPulsePositionfor 4 UIbit4 tTTP3 TransmitterPulsePositionfor 5 UIbit3 tTTP2 TransmitterPulsePositionfor 6 UIbit2 tTPDD Power Down Delayactiveto TxCLKOUT = 43 MHz OFF 6 10 ns Figure6 tTXZR EnableDelayOFF toactive TxCLKOUT = 43 MHz 40 55 nsFigure7 LVCMOS Outputs tCLH Low toHighTransitionTime C L = 8 pF LOCK, PASS, OS[2:0] 10 15 ns Figure5tCHL HightoLow TransitionTime 10 15 ns tPASS BIST PASS ValidTime, TxCLKOUT = 5 MHz PASS 560 570 ns BISTEN = 1,Figure12 TxCLKOUT = 43 MHz 70 75 ns SSCG Mode fDEV Spread Spectrum See (6) TxCLKOUT = 5 to43 ClockingDeviation MHz, ±0.5 ±2 % Frequency SSC[3:0]= ON fMOD Spread Spectrum See (6) TxCLKOUT = 5 to43 ClockingModulation MHz, 8 100 kHz Frequency SSC[3:0]= ON (4) tDCCJ isthemaximum amount ofjitterbetween adjacentclockcycles. (5) Specificationisensuredby characterizationand isnottestedinproduction. (6) Specificationisensuredby designand isnottestedinproduction. Recommended Timing fortheSerialControlBus Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units fSCL SCL ClockFrequency StandardMode 0 100 kHz FastMode 0 400 kHz tLOW SCL Low Period StandardMode 4.7 us FastMode 1.3 us tHIGH SCL HighPeriod StandardMode 4.0 us FastMode 0.6 us tHD;STA Holdtimefora startora StandardMode 4.0 us repeatedstartcondition, FastMode 0.6 usFigure13

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TxOUT[odd] TxCLKOUT TxOUT[even] +VOD -VOD +VOD -VOD +VOD -VOD Cycle N Cycle N+1 DS99R124Q www.ti.com SNLS318D –JANUARY 2010–REVISED APRIL 2013 Recommended Timing fortheSerialControlBus (continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units tSU:STA SetUp timefora startora StandardMode 4.7 us repeatedstartcondition, FastMode 0.6 usFigure13 tHD;DAT Data HoldTime, StandardMode 0 3.45 us Figure13 FastMode 0 0.9 us tSU;DAT Data SetUp Time, StandardMode 250 ns Figure13 FastMode 100 ns tSU;STO SetUp Time forSTOP StandardMode 4.0 us Condition,Figure13 FastMode 0.6 us tBUF Bus FreeTime StandardMode 4.7 us Between STOP and START, FastMode 1.3 usFigure13 tr SCL & SDA RiseTime, StandardMode 1000 ns Figure13 FastMode 300 ns tf SCL & SDA FallTime, StandardMode 300 ns Figure13 Fastmode 300 ns DC and AC SerialControlBus Characteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units VIH InputHighLevel SDA and SCL 0.7* VDDIO VVDDIO VIL InputLow LevelVoltage SDA and SCL 0.3*GND VVDDIO VHY InputHysteresis >50 mV VOL SDA, IOL = +0.5mA 0 0.36 V Iin SDA orSCL, Vin= VDDIO orGND -10 +10 µA tR SDA RiseTime– READ SDA, RPU = X,Cb ≤ 400pF 850 ns tF SDA FallTime – READ 120 ns tSU;DAT SetUp Time — READ 500 ns tHD;DAT HoldUp Time — READ 580 ns tSP InputFilter 50 ns C in InputCapacitance SDA orSCL <5 pF AC Timing Diagrams and TestCircuits Figure4. Checkerboard Data Pattern Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS99R124Q

R IN± TRI-STATELOCK PDB VIH(min) tDDLT VIH(min) tTXZR OEN LOCK TxCLKOUT TxOUT[2:0] Z Z VIHmin PDB tTPDD X PDB RIN LOCK PASS OS[2:0] TxCLKOUT TxOUT[2:0] Z Z Z Z Z VILmax 80% VDDIO 20% tCLH tCHL GND DS99R124Q SNLS318D –JANUARY 2010–REVISED APRIL 2013 www.ti.com Figure5. LVCMOS TransitionTimes Figure6. FPD-Link & LVCMOS Powerdown Delay Figure7. FPD-Link Outputs Enable Delay Figure8. DeserializerPLL Lock Times

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(w/ errors) tPASS 1/2 VDDIO Prior BIST Result Current BIST Test - Toggle on Error Result Held tBIT (1 UI) Sampling Window Ideal Data Bit End Ideal Data Bit Beginning RxIN_TOL -L RxIN_TOL -R Ideal Center Position (tBIT/2) TxCLKOUT± tTTP1 bit 1TxOUT[2:0]± bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tTTP2 tTTP3 tTTP4 tTTP5 tTTP6 1UI Cycle N tTTP7 2UI 3UI 4UI 5UI 6UI 7UI +VOD -VOD VOS GND tTLHT tTHLT |VOD| VODp-p DIFFERENTIAL SINGLE-ENDED DS99R124Q www.ti.com SNLS318D –JANUARY 2010–REVISED APRIL 2013 Figure9. FPD-Link (LVDS) Single-endedand DifferentialWaveforms Figure10. FPD-Link TransmitterPulse Positions Figure11. ReceiverInputJitterTolerance Figure12. BIST PASS Waveform Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS99R124Q

tHD;STA tLOW tr tHD;DAT tHIGH tf tSU;DAT tSU;STA tSU;STO tf START REPEATED START STOP tHD;STA START tSP tr BUFt DS99R124Q SNLS318D –JANUARY 2010–REVISED APRIL 2013 www.ti.com Figure13. SerialControlBus Timing Diagram

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0 5 10 15 20 25 30 35 40 45 PCLK (MHz) VODSEL = H SSCG = ON or OFF IDDTX @ 3.3V (mA) VODSEL = L SSCG = ON or OFF 0.46 0.48 0.51 0.53 0.56 0.58 0.61 0.63 JITTER FREQUENCY (kHz) JITTER AMPLITUDE (UI) 0 5 10 15 20 25 30 35 40 45 PCLK (MHz) SSCG = ON VODSEL = H or L TOTAL IDD @ 1.8V (mA) SSCG = OFF VODSEL = H or L DS99R124Q www.ti.com SNLS318D –JANUARY 2010–REVISED APRIL 2013 TypicalPerformance Characteristics Figure14.TypicalInputJitterToleranceCurve at43 MHz Figure15.TypicalTotalIDD Current(1.8VSupply)as a FunctionofPCLK Figure16.TypicalIDDTX Current(3.3VSupply)as a FunctionofPCLK Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS99R124Q

C C D C A D C B b b b b b b b b b b b b b b b b b b b b b b b b DS99R124Q SNLS318D –JANUARY 2010–REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION The DS99R124Q receives24-bitsofdataovera singleserialFPD-LinkIIpairoperatingat140Mbps to1.2Gbps. The serialstream alsocontainsan embedded clock,and the DC-balance informationwhich enhances signal qualityand supportsAC coupling.The receivercopnvertstheserialstreamintoa 4-channel(3dataand 1 clock) FPD-LinkLVDS Interface.The deviceisintendedtobe used withtheDS90UR241or theDS99R421 FPD-LinkII serializers. The Des convertsa singleinputserialdatastreamtoa FPD-Linkoutputbus,and alsoprovidesa signalcheck forthe chipsetBuiltIn SelfTest (BIST)mode. The devicecan be configuredviaexternalpinsor throughthe optionalserialcontrolbus.The Des featuresenhance signalqualityon the linkby supportingthe FPD-Link II datacodingthatprovidesrandomization,scrambling,and DC balancingofthedata.The Des includesmultiple featuresto reduce EMI associatedwith displaydata transmission.This includesthe randomizationand scramblingofthedata,FPD-LinkLVDS Outputinterface,and alsotheoutputspreadspectrumclockgeneration (SSCG) support.The Des' power savingfeaturesincludea power down mode, and optionalLVCMOS (1.8V) interfacecompatibility. The Des can attainlocktoa datastreamwithouttheuse ofa separatereferenceclocksource,which greatly simplifiessystem complexityand overallcost.The Des alsosynchronizesto the Ser regardlessof the data pattern,deliveringtrueautomatic“plugand lock” performance.Itcan locktotheincomingserialstreamwithout theneed ofspecialtrainingpatternsorsync characters.The Des recoverstheclockand databy extractingthe embedded clockinformation,validatingand thendeserializingtheincomingdatastream. The DS99R421Q /DS99R124Q chipsetsupports18-bitcolordepth,HS, VS and DE videocontrolsignalsand up tothreeover-sampledlow-speed(generalpurpose)databits. DATA TRANSFER The DS99R124 willreceivea pixelofdatainthefollowingformat:C1 and C0 representtheembedded clockin theserialstream.C1 isalwaysHIGH and C0 isalwaysLOW. b[23:0]containthescrambleddata.DCB isthe DC-Balanced controlbit.DCB isused tominimizetheshortand long-termDC biason thesignallines.Thisbit determinesifthe data isunmodifiedor inverted.DCA isused to validatedata integrityinthe embedded data stream.Both DCA and DCB codingschemes are generatedby theSer and decoded by theDes automatically. Figure17 illustratestheserialstreamperPCLK cycle. Figure17. FPD-Link IISerialStream (DS99R421/DS99R124) The devicesupportsclocksinthe range of 5 MHz to 43 MHz. With everyclockcycle24 bitsof payloadare receivedalongwiththefouroverheadbits.Thus,thelinerateis1.2Gbps maximum (140 Mbps minimum) with an effectivedatarateof1.03Gbps maximum. The linkisextremelyefficientat86% (24/28). The FPD-Linkoutputwillpass alongthedatatotheDisplayintheformatshown inFigure18. Figure18. FPD-Link Output Format

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www.ti.com SNLS318D –JANUARY 2010–REVISED APRIL 2013 FPD-LINK IIINPUT Common Mode FilterPin (CMF) — Optional The Des providesaccesstothecentertapoftheinternaltermination.A capacitormay be placedon thispinfor additionalcommon-mode filteringof the differentialpair.This can be usefulin high noiseenvironmentsfor additionalnoiserejectioncapability.A 4.7µF capacitormay be connectedtothispintoGround. OUTPUT INTERFACES (LVCMOS & FPD-LINK) OS[2:0]LVCMOS Outputs Additionalsignalsmaybe receivedacrosstheseriallinkperPCLK. The over-sampledbitsarerestrictedtobe low speed signalsand shouldbe lessthan1/5ofthefrequencyofthePCLK. Signalsshouldconvey levelinformation only,as pulsewidthdistrotionwilloccurby theoversamplingtechniqueand locationofthesamplingclock.The threeoversampled bitsareexactlymapped toDS99R421's;and toDS90UR421 bitsare:OS0 = DIN21,OS1 = DIN22,and OS2 = DIN23. CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and OUTPUT STATE SELECT (OSS_SEL) When PDB isdrivenHIGH, the CDR PLL beginslockingto the serialinput,LOCK isLow and the FPD-Link interfacestateisdeterminedby thestateoftheOSS_SEL pin. Afterthe DS99R124Q completesitslocksequence to the inputserialdata,the LOCK outputisdrivenHIGH, indicatingvaliddataand clockrecoveredfromtheserialinputisavailableon theFPD-Linkoutputs.The TxCLK outputisheldatitscurrentstateatthechange fromOSC_CLK (ifthisisenabledviaOSC_SEL) totherecovered clock(orviceversa).Note thattheFPD-Linkoutputsmay be heldinan inactivestate(TRI-STATE)throughthe use oftheOutputEnablepin(OEN). Ifthereisa lossofclockfromtheinputserialstream,LOCK isdrivenLow and thestateoftheoutputsarebased on theOSS_SEL setting(configurationpinorregister). Table1.Output StateTable INPUTS OUTPUTS PDB OEN OSS_SEL LOCK OTHER OUTPUTS L X L Z TxCLKOUT isTRI-STATE TxOUT[2:0]areTRI-STATE OS[2:0]areTRI-STATE PASS isTRI-STATE L X H L TxCLKOUT isTRI-STATE TxOUT[2:0]areTRI-STATE OS[2:0]areLOW PASS isTRI-STATE H L L L TxCLKOUT isTRI-STATE TxOUT[2:0]areTRI-STATE OS[2:0]areLOW PASS isHIGH H L H L TxCLKOUT isTRI-STATE TxOUT[2:0]areTRI-STATE OS[2:0]areLOW PASS isLOW H H L L TxCLKOUT isTRI-STATE TxOUT[2:0]areTRI-STATE OS[2:0]areTRI-STATE PASS isHIGH H H H L TxCLKOUT isTRI-STATE TxOUT[2:0]areLOW OS[2:0]areLOW PASS isLOW Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS99R124Q

SNLS318D –JANUARY 2010–REVISED APRIL 2013 www.ti.com Table1.Output StateTable(continued) INPUTS OUTPUTS PDB OEN OSS_SEL LOCK OTHER OUTPUTS H L X H TxCLKOUT isTRI-STATE TxOUT[2:0]areTRI-STATE OS[2:0]areActive PASS isActive (ThissettingallowsthesystemtorunBIST oruse theOS[2:0] bitswhilethepanelisoff) H H X H TxCLKOUT isActive TxOUT[2:0]areActive OS[2:0]areActive PASS isActive (Normaloperatingmode) LVCMOS 1.8V/3.3VVDDIO Operation The LVCMOS inputsand outputscan operatewith1.8V or3.3V levels(VDDIO )fortarget(Display)compatibility. The 1.8V levelswilloffera lowernoise(EMI)and alsoa systempower savings. FPD-LINK OUTPUT VODSEL The differentialoutputvoltageoftheFPD-Linkinterfaceiscontrolledby theVODSEL input. Table2.VODSEL ConfigurationTable VODSEL Result L VOD is250mV TYP (500mVp-p) H VOD is400mV TYP (800mVp-p) SSCG Generation— Optional The Des providesan internallygeneratedspreadspectrumclock(SSCG) tomodulateitsoutputs.Both clockand dataoutputsaremodulated.ThiswillaidtolowersystemEMI.OutputSSCG deviationsto±2.0% (4% total)atup to35kHz modulationsnominallyareavailable.See Table3 and Table4.Thisfeaturemay be controlledby pins or by register.The LFMODE shouldbe setappropriatelyiftheSSCG isbeingused.Set LFMODE High ifthe clockfrequencyisbetween 5 MHz and 20 MHz, setLFMODE Low iftheclockfrequencyisbetween 20 MHz and 43 MHz. Table3. SSCG Configuration(LFMODE = L)— Des Output SSC[2:0]Inputs Result LFMODE = L (20-43 MHz) SSC2 SSC1 SSC0 fdev(%) fmod (kHz) L L L OFF OFF L L H ±0.9 L H L ±1.2 CLK/2168 L H H ±1.9 H L L ±2.3 H L H ±0.7 H H L ±1.3 CLK/1300 H H H ±1.7

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fdev(max)FPCLK+ Frequency Time FPCLK- FPCLK fdev(min) 1/fmod DS99R124Q www.ti.com SNLS318D –JANUARY 2010–REVISED APRIL 2013 Table4. SSCG Configuration(LFMODE = H) — Des Output SSC[2:0]Inputs Result LFMODE = H (5-20 MHz) SSC2 SSC1 SSC0 fdev(%) fmod (kHz) L L L OFF OFF L L H ±0.7 L H L ±1.3 CLK/625 L H H ±1.8 H L L ±2.2 H L H ±0.7 H H L ±1.2 CLK/385 H H H ±1.7 Figure19. SSCG Waveform POWER SAVING FEATURES PowerDown Feature(PDB) The Des has a PDB inputpinto ENABLE or POWER DOWN the device.Thispincan be controlledby the system tosave power,disablingtheDes when thedisplayisnotneeded.An autodetectmode isalsoavailable. In thismode, the PDB pinistiedHigh and the Des willenterPOWER DOWN when the serialstream stops. When theserialstreamstartsup again,theDes willlocktotheinputstreamand asserttheLOCK pinand output validdata.InPOWER DOWN mode, theData and PCLK outputstatesaredeterminedby theOSS_SEL status. Note – inPOWER DOWN, theoptionalSerialBus ControlRegistersareRESET . Stop Stream SLEEP Feature The Des willentera low power SLEEP statewhen the inputserialstream isstopped.A STOP conditionis detectedwhen theembedded clockbitsarenotpresent.When theserialstreamstartsagain,theDes willthen lockto the incomingsignaland recoverthe data.Note – inSTOP STREAM SLEEP, the optionalSerialBus ControlRegistersvaluesareRETAINED . BuiltInSelfTest(BIST)— Optional An optionalAt-SpeedBuiltInSelfTest(BIST)featuresupportsthetestingofthehigh-speedseriallink.Thisis usefulintheprototypestage,equipmentproduction,in-systemtestand alsoforsystem diagnostics.IntheBIST mode onlyan inputclockisrequiredalongwithcontroltotheSer and Des BISTEN inputpins.The Ser outputsa testpattern(PRBS7) and drivesthelinkatspeed.The Des detectsthePRBS7 patternand monitorsitforerrors. The PASS outputpintogglesto flagany payloadsthatare receivedwith1 to 24 biterrors.The BISTM pin selectstheoperationalmode ofthePASS pin.IfBISTM = L,thePASS pinsreportsthefinalresultonly.IfBISTM = H, thePASS pinscountspayloaderrorsand alsoresultstheresult.The resultofthetestisheldon thePASS outputuntilreset(new BIST testorPower Down).A highon PASS indicatesNO ERRORS were detected.A Low on PASS indicatesone or more errorswere detected.The durationofthetestiscontrolledby thepulsewidth appliedtotheDes BISTEN pin. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS99R124Q

Step 1: SER in BIST Step 2: Wait, DES in BIST Step 3: DES in Normal Mode - check PASS Step 4: SER in Normal BIST Wait BIST Start BIST Stop DS99R124Q SNLS318D –JANUARY 2010–REVISED APRIL 2013 www.ti.com Figure20. BIST Mode Flow Diagram Sample BIST Sequence See Figure20 fortheBIST mode flowdiagram. 1. For the DS99R421 FPD-Link IISer BIST Mode isenabledviathe BISTEN pin.For the DS90UR241 Ser, BIST mode iseneteredby settingalltheinputdataofthedevicetoLow state.A PCLK isrequiredforallthe Ser options.When theDes detectstheBIST mode patternand command (DCA and DCB code)theRGB and controlsignaloutputsareshutoff. 2. PlacetheDS99R124Q Des inBIST mode by settingtheBISTEN = H. The Des isnow intheBIST mode. If BISTM = H, theDes willcheck theincomingserialpayloadsforerrors.Ifan errorinthepayload(1to24)is detected,thePASS pinwillswitchlowforone halfoftheclockperiod.DuringtheBIST test,thePASS output can be monitoredand countedtodeterminethepayloaderrorrate. 3. To Stop theBIST mode, theDes BISTEN pinissetLow. The Des stopscheckingthedata.The finaltest resultisheldon thePASS pin.Ifthetestran errorfree,thePASS outputwillbe High.Iftherewas one or more errorsdetected,thePASS outputwillbe Low. The PASS outputstateishelduntila new BIST isrun, thedeviceisRESET, orPowered Down. The BIST durationisusercontrolledby thedurationoftheBISTEN signal. 4. To returnthe linkto normal operation,the Ser BISTEN inputis set Low. The Link returnsto normal operation. Figure21 shows thewaveform diagramofa typicalBIST testfortwo cases.Case 1 iserrorfree,and Case 2 shows one withmultipleerrors.Inmost cases itisdifficulttogenerateerrorsdue totherobustnessofthelink (differentialdatatransmissionetc.),thustheymay be introducedby greatlyextendingthecablelength,faulting theinterconnect,reducingsignalconditionenhancements (De-Emphasis,VODSEL, orRx Equalization).

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4.7k 10k R ID SCL SDA To Other Devices ID[X] 1.8V VDDIO 4.7k X XX PCLK (RFB = L) BISTEN (DES) PASS DATA (internal) Prior Result PASS FAIL X = bit error(s) BISTEN (SER) RGB[7:0] HS, VS, DE DATA (internal) Case 1 - Pass Case 2a - Fail Prior Result DES OutputsSER X XX PASS w/ BISTM = H BIST Duration BIST Result Held FAIL X = bit error(s) DATA (internal) Case 2b - Fail Prior Result Normal PRBS BIST Test Normal PASS w/ BISTM = L DS99R124Q www.ti.com SNLS318D –JANUARY 2010–REVISED APRIL 2013 Figure21. BIST Waveforms SerialBus Control— Optional The DS99R124 may alsobe configuredby the use of a serialcontrolbus thatisI2C protocolcompatible.By default,the I2C reg_0x00'hissetto 00'hand allconfigurationissetby control/strappins.A writeof 01'hto reg_0x00'hwillenable/allowconfigurationby registers;thiswilloverridethecontrol/strappins.Multipledevices may sharetheserialcontrolbus sincemultipleaddressesaresupported.See Figure22. The serialbus iscomprisedofthreepins.The SCL isa SerialBus ClockInput.The SDA istheSerialBus Data Input/ Output signal.Both SCL and SDA signalsrequirean externalpullup resistorto VDDIO . For most applicationsa 4.7 k pullup resistorto VDDIO may be used.The resistorvaluemay be adjustedforcapacitive loadingand dataraterequirements.The signalsareeitherpulledHigh,ordrivenLow. Figure22. SerialControlBus Connection The thirdpinistheID[X]pin.Thispinsetsone offourpossibledeviceaddresses.Two differentconnectionsare possible.The pinmay be pulledtoVDD (1.8V,NOT VDDIO ))witha 10 kΩ resistor.Or a 10 kΩ pullup resistor(to VDD 1.8V,NOT VDDIO ))and a pulldown resistoroftherecommended valuetosetotherthreepossibleaddresses may be used.See Table5 fortheDes. The SerialBus protocoliscontrolledby START, START-Repeated, and STOP phases.A START occurswhen SCL transitionsLow whileSDA isHigh.A STOP occurswhen SDA transitionHigh whileSCL isalsoHIGH. See Figure23 Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DS99R124Q

Slave Address Register Address Data S 0 ac k ac k ac k P A A A Slave Address Register Address Slave Address Data S 0 1 ac k ac k ac k ac kS P A A A A A A SDA SCL S P START condition, or START repeat condition STO P condition DS99R124Q SNLS318D –JANUARY 2010–REVISED APRIL 2013 www.ti.com Figure23. START and STOP Conditions To communicate witha remote device,the hostcontroller(master)sends the slaveaddressand listensfora responsefrom the slave.Thisresponseisreferredto as an acknowledge bit(ACK).Ifa slaveon the bus is addressedcorrectly,itAcknowledges (ACKs) the master by drivingthe SDA bus low.Ifthe addressdoesn't match a device'sslaveaddress,itNot-acknowledges(NACKs) themasterby lettingSDA be pulledHigh.ACKs alsooccuron the bus when data isbeingtransmitted.When the master iswritingdata,the slaveACKs after everydata byteissuccessfullyreceived.When the master isreadingdata,the master ACKs aftereverydata byteisreceivedto letthe slaveknow itwants to receiveanotherdata byte.When the master wants to stop reading,itNACKs afterthelastdatabyteand createsa stopconditionon thebus.Allcommunicationon thebus beginswitheithera Startconditionora Repeated Startcondition.Allcommunicationon thebus ends witha Stop condition.A READ isshown inFigure24 and a WRITE isshown inFigure25. IftheSerialBus isnotrequired,thethreepinsmay be leftopen (NC). Table5. ID[x]ResistorValue – DS99R124Q Des Resistor Address Address RID kΩ 7'b 8'b (5%tol) 0 appended (WRITE) 0.47 7b'111 0001 (h'71) 8b'1110 0010 (h'E2) 2.7 7b'111 0010 (h'72) 8b'1110 0100 (h'E4) 8.2 7b'111 0011 (h'73) 8b'1110 0110 (h'E6) Open 7b'111 0110 (h'76) 8b'1110 1100 (h'EC) Figure24. SerialControlBus — READ Figure25. SerialControlBus — WRITE

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www.ti.com SNLS318D –JANUARY 2010–REVISED APRIL 2013 Table6.DS99R124Q — SerialBus ControlRegisters ADD ADD RegisterName Bit(s) R/W Defau Function Description (dec) (hex) lt (bin) 0 0 Des Config1 7 R/W 0 LFMODE SSCG Mode – lowfrequencysupport 0:20 to43 MHz Operation 1:5 to20 MHz Operation

6 R/W 0 OSS_SEL OutputSleepStateSelect

5 R/W 0 Reserved Reserved

4 R/W 0 Reserved Reserved

3:2 R/W 00 Reserved Reserved

1 R/W 0 SLEEP Note – notthesame functionas PowerDown (PDB)

0:normalmode 1:SleepMode – Registersettingsretained.

0 R/W 0 REG Control 0:Configurationssetfromcontrolpins

1:Configurationssetfromregisters(exceptI2C_ID) 1 1 SlaveID 7 R/W 0 ADD_SEL 0:AddressfromID[X]Pin 1:AddressfromRegister 6:0 R/W 11100 ID[X] SerialBus DeviceID,FourIDsare: 00 7b '1110001 (h'71);8b '1110 0010 (h'E2) 7b '1110010 (h'72);8b '1110 0100 (h'E4) 7b '1110011 (h'73);8b '1110 0110 (h'E6) 7b '1110110 (h'76);8b '1110 1100 (h'EC) AllotheraddressesareReserved. 2 2 Des Features1 7 R/W 0 OEN OutputEnableInput 0:FPD-LinkoutputareTRI-STATE 1:FPD-Linkoutputsareenabled(active)

6 R/W 0 Reserved Reserved

5:4 R/W 00 Reserved Reserved

3 R/W 0 VODSEL DifferentialDriverOutputVoltageSelect

0:LVDS VOD is±250 mV, 500 mVp-p (typ) 1:LVDS VOD is±400 mV, 800 mVp-p (typ) 2:0 R/W 00 OSC_SEL 000:OFF 001:Reserved 010:25 MHz ±40% 011:16.7MHz ±40% 100:12.5MHz ±40% 101:10 MHz ±40% 110:8.3MHz ±40% 111:6.3MHz ±40% Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:DS99R124Q

SNLS318D –JANUARY 2010–REVISED APRIL 2013 www.ti.com Table6.DS99R124Q — SerialBus ControlRegisters(continued) ADD ADD RegisterName Bit(s) R/W Defau Function Description (dec) (hex) lt (bin) 3 3 Des Features2 7:5 R/W 000 EQ Gain 000:~1.625dB 001:~3.25dB 010:~4.87dB 011:~6.5dB 100:~8.125dB 101:~9.75dB 110:~11.375dB 111:~13 dB

4 R/W 0 EQ Enable 0:EQ = disabled

1:EQ = enabled

3 R/W 0 Reserved Reserved

2:0 R/W 000 SSC IFLFMODE = 0,then: 000:SSCG OFF 001:fdev= ±0.9%,fmod = CLK/2168 010:fdev= ±1.2%,fmod = CLK/2168 011:fdev= ±1.9%,fmod = CLK/2168 100:fdev= ±2.3%,fmod = CLK/2168 101:fdev= ±0.7%,fmod = CLK/1300 110:fdev= ±1.3%,fmod = CLK/1300 111:fdev= ±1.57%,fmod = CLK/1300 IFLFMODE = 1,then: 000:SSCG OFF 001:fdev= ±0.7%,fmod = CLK/625 010:fdev= ±1.3%,fmod = CLK/625 011:fdev= ±1.8%,fmod = CLK/625 100:fdev= ±2.2%,fmod = CLK/625 101:fdev= ±0.7%,fmod = CLK/385 110:fdev= ±1.2%,fmod = CLK/385 111:fdev= ±1.7%,fmod = CLK/385

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OS[2] PDB NC DAP (GND) ID[X] SDA SCL RIN+ RIN- VDDA VDDIO VDDTX VDDIO 3.3VDS99R124Q (CON) VDDL BISTEN GND OS[1] OS[0] 1.8V C1 - C2 = 0.1 PF (50 WV) C3 - C9 = 0.1 PF C10 - C12 = 4.7 PF C13 = > 10 PF R = 10 k: FB1 - FB5: Impedance = 1 k: Low DC resistance (< 1:) Serial FPD-Link II Interface PASS CMF VDDP VDDP VDDP VDDA C10 Host Control C13 FPD-Link Interface LVDS

100 Ohm

OSS_SEL LFMODE SSC[2] SSC[1] SSC[0] Tie to desired setting VDDL VDDIO R FB1 FB3 DS99R124Q www.ti.com SNLS318D –JANUARY 2010–REVISED APRIL 2013 APPLICATIONS INFORMATION DISPLAY APPLICATION The DS99R124Q, inconjunctionwiththeDS99R421Q or DS90UR241Q, isintendedforinterfacingbetween a host(graphicsprocessor)and a Display.Itsupportsan 18-bitcolordepth(RGB666) and up toWVGA display formats.Ina RGB666 application,18 colorbits(R[5:0],G[5:0],B[5:0]),PixelClock(PCLK) and threecontrolbits (VS,HS and DE) aresupportedacrosstheseriallinkwithPCLK ratesfrom5 to43MHz. TYPICAL APPLICATION CONNECTION Figure26 shows a typicalapplicationof the DS99R124QQ Des in pin mode fora 43 MHz WVGA Display Application.The LVDS inputsutilize100 nF couplingcapacitorstothelineand theReceiverprovidesinternal termination.Bypass capacitorsare placednear thepower supplypins.Ferritebeads are placedon thepower linesforeffectivenoisesuppression. Figure26. DS99R124Q TypicalConnection Diagram — Pin Control Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:DS99R124Q

SNLS318D –JANUARY 2010–REVISED APRIL 2013 www.ti.com POWER UP REQUIREMENTS AND PDB PIN The VDD (VDDn ),VDDTX and VDDIO supplyramps shouldbe fasterthan1.5ms witha monotonicrise.Supplies may power up inany order,however deviceoperationshouldbe initiatedonlyafterallsuppliesareintheirvalid operatingranges.The optionalserialbus addressselectionisdone upon power up also.Thus, ifusingthis optionalfeature,thePDB signalmust be delayedtoallowtimefortheID settingtooccur.The delaymaybe done by simplyholdingthePDB pinata Low, orwithan externalRC delaybased offtheVDDIO railwhichwould then need tolagtheothersintime.IfthePDB pinispulledtoVDDIO ,itisrecommended touse a 10 kΩ pull-upand a 10 uF cap toGND todelaythePDB inputsignal. TRANSMISSION MEDIA The Ser/Des chipsetisintendedto be used ina point-to-pointconfiguration,througha PCB trace,or through twistedpaircable.The Ser and Des provideinternalterminationsprovidinga cleansignalingenvironment.The interconnectforLVDS shouldpresenta differentialimpedance of 100 Ohms. Use cablesand connectorsthat have matched differentialimpedance tominimizeimpedance discontinuities.Shieldedorun-shieldedcablesmay be used dependingupon thenoiseenvironmentand applicationrequirements. LIVE LINK INSERTION The Ser and Des devicessupportlivepluggableapplications.The automaticreceiverlocktorandom data“plug& go”hotinsertioncapabilityallowstheDS99R124Q toattainlocktotheactivedatastreamduringa liveinsertion event. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuitboardlayoutand stack-upfortheLVDS Ser/Desdevicesshouldbe designedtoprovidelow-noisepower feed to the device.Good layoutpracticewillalsoseparatehighfrequencyor high-levelinputsand outputsto minimizeunwanted straynoisepickup,feedbackand interference.Power system performancemay be greatly improvedby usingthindielectrics(2to4 mils)forpower /groundsandwiches.Thisarrangementprovidesplane capacitanceforthePCB power system withlow-inductanceparasitics,which has provenespeciallyeffectiveat highfrequencies,and makes thevalueand placementofexternalbypasscapacitorslesscritical.Externalbypass capacitorsshouldincludebothRF ceramicand tantalumelectrolytictypes.RF capacitorsmay use valuesinthe tantalumcapacitorsshouldbe atleast5X thepower supplyvoltagebeingused. Surfacemount capacitorsarerecommended due totheirsmallerparasitics.When usingmultiplecapacitorsper supplypin,locatethesmallervalueclosertothepin.A largebulkcapacitorisrecommend atthepointofpower entry.This is typicallyin the 50uF to 100uF range and willsmooth low frequencyswitchingnoise.Itis recommended toconnectpower and groundpinsdirectlytothepower and groundplaneswithbypass capacitors connectedtotheplanewithviaon bothends ofthecapacitor.Connectingpower or ground pinstoan external bypasscapacitorwillincreasetheinductanceofthepath. A smallbody sizeX7R chipcapacitor,such as 0603,isrecommended forexternalbypass.Itssmallbody size reducesthe parasiticinductanceof the capacitor.The user must pay attentionto the resonancefrequencyof theseexternalbypass capacitors,usuallyinthe range of 20-30 MHz. To provideeffectivebypassing,multiple capacitorsare oftenused toachievelow impedance between thesupplyrailsoverthefrequencyofinterest.At highfrequency,itisalsoa common practicetouse two viasfrompower and groundpinstotheplanes,reducing theimpedance athighfrequency. Some devicesprovideseparatepower and groundpinsfordifferentportionsofthecircuit.Thisisdone toisolate switchingnoiseeffectsbetween differentsectionsof the circuit.Separateplaneson the PCB are typicallynot required.PinDescriptiontablestypicallyprovideguidanceon whichcircuitblocksareconnectedtowhichpower pinpairs.Insome cases,an externalfiltermany be used toprovidecleanpower tosensitivecircuitssuch as PLLs. Use atleasta fourlayerboard witha power and ground plane.LocateLVCMOS signalsaway from theLVDS linesto preventcouplingfrom the LVCMOS linesto the LVDS lines.Closely-coupleddifferentiallinesof 100 Ohms aretypicallyrecommended forLVDS interconnect.The closelycoupledlineshelptoensurethatcoupled noisewillappear as common-mode and thusisrejectedby the receivers.The tightlycoupledlineswillalso radiateless. Informationon theWQFN stylepackage isprovidedinTexas InstrumentsNote:AN-1187 (SNOA401 ).

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www.ti.com SNLS318D –JANUARY 2010–REVISED APRIL 2013 LVDS INTERCONNECT GUIDELINES See AN-1108 (SNLA008 )and AN-905 (SNLA035 )forfulldetails.

Use 100Ω coupleddifferentialpairs
Use theS/2S/3Sruleinspacings – S = space between thepair – 2S = space between pairs – 3S = space toLVCMOS signal
Minimizethenumber ofVias
Use differentialconnectorswhen operatingabove 500Mbps linespeed
Maintainbalanceofthetraces
Minimizeskew withinthepair
Terminateas closetotheTX outputsand RX inputsas possible Additionalgeneralguidancecan be foundintheLVDS Owner ’s Manual - availableinPDF formatfrom theTI web siteat:http://www.ti.com/ww/en/analog/interface/lvds.shtml Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:DS99R124Q

SNLS318D –JANUARY 2010–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionC (April2013)toRevisionD Page

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www.ti.com 16-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples DS99R124QSQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 DS99R124Q DS99R124QSQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 DS99R124Q DS99R124QSQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 DS99R124Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS99R124QSQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS99R124QSQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS99R124QSQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 2

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