DS99R106VS

DS99R105 NSC | Alldatasheet

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Technical content

Features

■ 3 MHz–40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions ■ Capable to drive shielded twisted-pair cable ■ User selectable clock edge for parallel data on both Transmitter and Receiver ■ Internal DC Balancing encode/decode – Supports AC- coupling interface with no external coding required ■ Individual power-down controls for both Transmitter and Receiver ■ Embedded clock CDR (clock and data recovery) on Receiver and no external source of reference clock needed ■ All codes RDL (random data lock) to support live- pluggable applications ■ LOCK output flag to ensure data integrity at Receiver side ■ Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side ■ PTO (progressive turn-on) LVCMOS outputs to reduce EMI and minimize SSO effects ■ All LVCMOS inputs and control pins have internal pulldown ■ On-chip filters for PLLs on Transmitter and Receiver ■ Integrated 100Ω input termination on Receiver ■ 4 mA Receiver output drive ■ 48-pin TQFP and 48-pin LLP packages ■ Pure CMOS .35 μm process ■ Power supply range 3.3V ± 10% ■ Temperature range 0°C to +70°C ■ 8 kV HBM ESD tolerance Block Diagram 20208101 TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 202081 www.national.com DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD) −0.3V to +4V LVCMOS/LVTTL Input Voltage −0.3V to (VDD +0.3V) LVCMOS/LVTTL Output Voltage −0.3V to (VDD +0.3V) LVDS Receiver Input Voltage −0.3V to 3.9V LVDS Driver Output Voltage −0.3V to 3.9V LVDS Output Short Circuit Duration 10 ms Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4 seconds) +260°C Maximum Package Power Dissipation Capacity Package De-rating: 48L TQFP 1/θJA °C/W above +25°C DS99R105 θJC 21.0°C/W DS99R106 θJC 21.1°C/W 48L LLP 1/θJA °C/W above +25°C DS99R105 θJC 3.7°C/W DS99R106 θJA 28 (4L*); 79.1 (2L*)°C/W θJC 3.71°C/W *JEDEC ESD Rating (HBM) ≥±8 kV Recommended Operating Conditions Min Nom Max Units Supply Voltage (VDD) 3.0 3.3 3.6 V Operating Free Air Temperature (T A) 0 +25 +70 °C Clock Rate 3 40 MHz Supply Noise ±100 mVP-P

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units LVCMOS/LVTTL DC SPECIFICATIONS VIH High Level Voltage Tx: DIN[23:0], TCLK, TPWDNB, DEN, TRFB, DCAOFF, DCBOFF, VODSEL Rx: RPWDNB, RRFB, REN 2.0 1.5 VDD V VIL Low Level Input Voltage GND 1.5 0.8 V VCL Input Clamp Voltage ICL = −18 mA (Note 8) −0.8 −1.5 V IIN Input Current VIN = 0V or 3.6V Tx: DIN[23:0], TCLK, TPWDNB, DEN, TRFB, DCAOFF, DCBOFF, VODSEL −10 ±1 +10 µA Rx: RPWDNB, RRFB, REN −20 ±5 +20 µA VOH High Level Output Voltage IOH = −4 mA Rx: ROUT[23:0], RCLK, LOCK 2.3 3.0 VDD V VOL Low Level Output Voltage IOL = +4 mA GND 0.33 0.5 V IOS Output Short Circuit Current VOUT = 0V (Note 8) −40 −70 −110 mA IOZ TRI-STATE® Output Current RPWDNB, REN = 0V VOUT = 0V or 2.4V Rx: ROUT[23:0], RCLK, LOCK −30 ±0.4 +30 µA www.national.com 2 DS99R105/DS99R106

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units LVDS DC SPECIFICATIONS VTH Differential Threshold High Voltage VCM = +1.2V Rx: RIN+, RIN− +50 mV VTL Differential Threshold Low Voltage −50 mV IIN Input Current VIN = +2.4V, VDD = 3.6V ±300 µA VIN = 0V, VDD = 3.6V ±300 µA RT Differential Internal Termination Resistance 90 100 130 Ω VOD Output Differential Voltage (DOUT+)–(DOUT−) RL = 100Ω, w/o Pre-emphasis VODSEL = L (Figure 10) Tx: DOUT+, DOUT− 250 400 600 mV RL = 100Ω, w/o Pre-emphasis VODSEL = H (Figure 10) 450 750 1200 mV ΔVOD Output Differential Voltage Unbalance RL = 100Ω, w/o Pre-emphasis 4 50 mV VOS Offset Voltage RL = 100Ω, w/o Pre-emphasis 1.00 1.25 1.50 V ΔVOS Offset Voltage Unbalance RL = 100Ω, w/o Pre-emphasis 1 50 mV IOS Output Short Circuit Current DOUT = 0V, DIN = H, TPWDNB, DEN = 2.4V, VODSEL = L −2 −5 −8 mA DOUT = 0V, DIN = H, TPWDNB, DEN = 2.4V, VODSEL = H −7 −10 −13 mA IOZ TRI-STATE Output Current TPWDNB, DEN = 0V, DOUT = 0V or 2.4V −15 ±1 +15 µA SER/DES SUPPLY CURRENT (DVDD*, PVDD* and AVDD* pins) *Digital, PLL, and Analog VDDs IDDT Serializer (Tx) Total Supply Current (includes load current) RL = 100Ω Pre-emphasis = OFF VODSEL = L Checker-board pattern (Figure 1) f = 40 MHz 40 80 mA RL = 100Ω Pre-emphasis = ON VODSEL = L Checker-board pattern (Figure 1) f = 40 MHz 45 85 mA Serializer (Tx) Total Supply Current (includes load current) RL = 100Ω Pre-emphasis = OFF VODSEL = H Checker-board pattern (Figure 1) f = 40 MHz 40 85 mA RL = 100Ω Pre-emphasis = ON VODSEL = H Checker-board pattern (Figure 1) f = 40 MHz 45 90 mA IDDTZ Serializer (Tx) Supply Current Power-down TPWDNB = 0V (All other LVCMOS Inputs = 0V) 1 100 µA 3 www.national.com DS99R105/DS99R106

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units IDDR Deserializer (Rx) Total Supply Current (includes load current) CL = 8 pF LVCMOS Output Checker-board pattern (Figure 2) f = 40 MHz 95 mA Deserializer (Rx) Total Supply Current (includes load current) CL = 8 pF LVCMOS Output Random pattern f = 40 MHz 90 mA IDDRZ Deserializer (Rx) Supply Current Power-down RPWDNB = 0V (All other LVCMOS Inputs = 0V, RIN+/ RIN- = 0V) 1 50 µA Serializer Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tTCP Transmit Clock Period (Figure 5) 25 T 333 ns tTCIH Transmit Clock High Time 0.4T 0.5T 0.6T ns tTCIL Transmit Clock Low Time 0.4T 0.5T 0.6T ns tCLKT TCLK Input Transition Time (Figure 4) 3 6 ns tJIT TCLK Input Jitter (Note 9) 33 ps (RMS) Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tLLHT LVDS Low-to-High Transition Time RL = 100Ω, (Figure 3) CL = 10 pF to GND VODSEL = L 0.6 ns tLHLT LVDS High-to-Low Transition Time 0.6 ns tDIS DIN (23:0) Setup to TCLK RL = 100Ω, CL = 10 pF to GND (Note 8) 5 ns tDIH DIN (23:0) Hold from TCLK 5 ns tHZD DOUT ± HIGH to TRI-STATE Delay RL = 100Ω, CL = 10 pF to GND (Figure 6) (Note 5) 15 ns tLZD DOUT ± LOW to TRI-STATE Delay 15 ns tZHD DOUT ± TRI-STATE to HIGH Delay 200 ns tZLD DOUT ± TRI-STATE to LOW Delay 200 ns tPLD Serializer PLL Lock Time RL = 100Ω, (Figure 7) 10 ms tSD Serializer Delay RL = 100Ω, (Figure 8) VODSEL = L, TRFB = H 3.5T + 2.85 3.5T + 10 ns RL = 100Ω, (Figure 8) VODSEL = L, TRFB = L 3.5T + 2.85 3.5T + 10 ns TxOUT_E_O TxOUT_Eye_Opening (respect to ideal) 3–40 MHz (Figure 9) (Notes 9, 13) 0.68 UI (Note 10) Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tRCP Receiver out Clock Period tRCP = tTCP (Note 8) RCLK 25 T 333 ns tRDC RCLK Duty Cycle RCLK 45 50 55 % tCLH LVCMOS Low-to-High Transition Time CL = 8 pF (lumped load) (Figure 11) ROUT [23:0], LOCK, RCLK 2.5 3.5 ns tCHL LVCMOS High-to-Low Transition Time 2.5 3.5 ns www.national.com 4 DS99R105/DS99R106

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tROS ROUT (7:0) Setup Data to RCLK (Group 1) (Figure 15) ROUT [7:0] (0.40)* tRCP (29/56)*tRCP ns tROH ROUT (7:0) Hold Data to RCLK (Group 1) (0.40)* tRCP (27/56)*tRCP ns tROS ROUT (15:8) Setup Data to RCLK (Group 2) (Figure 15) ROUT [15:8], LOCK (0.40)* tRCP 0.5*tRCP ns tROH ROUT (15:8) Hold Data to RCLK (Group 2) (0.40)* tRCP 0.5*tRCP ns tROS ROUT (23:16) Setup Data to RCLK (Group 3) (Figure 15) ROUT [23:16] (0.40)* tRCP (27/56)*tRCP ns tROH ROUT (23:16) Hold Data to RCLK (Group 3) (0.40)* tRCP (29/56)*tRCP ns tHZR HIGH to TRI-STATE Delay (Figure 13) ROUT [23:0], RCLK, LOCK 3 10 ns tLZR LOW to TRI-STATE Delay 3 10 ns tZHR TRI-STATE to HIGH Delay 3 10 ns tZLR TRI-STATE to LOW Delay 3 10 ns tDD Deserializer Delay (Figure 12) RCLK [4+(3/56)]T +5.9 [4+(3/56)]T +18.5 ns tDRDL Deserializer PLL Lock Time from Powerdown (Figure 14) (Notes 7, 8)

3 MHz 5 50 ms

40 MHz 5 50 ms

RxIN_TOL_L Receiver INput TOLerance Left (Figure 16) (Notes 6, 8, 10) 3 MHz–40 MHz 0.25 UI RxIN_TOL_R Receiver INput TOLerance Right (Figure 16) (Notes 6, 8, 10) 3 MHz–40 MHz 0.25 UI Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Note 5: When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer. Note 6: RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a measurement in reference with the ideal bit position, please see National’s AN-1217 for detail. Note 7: The Deserializer PLL lock time (tDRDL) may vary depending on input data patterns and the number of transitions within the pattern. Note 8: Specification is guaranteed by characterization and is not tested in production. Note 9: tJIT (@BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter. Note 10: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency. Note 11: Figures 1, 2, 8, 12, 14 show a falling edge data strobe (TCLK IN/RCLK OUT). Note 12: Figures 5, 15 show a rising edge data strobe (TCLK IN/RCLK OUT). Note 13: TxOUT_E_O is affected by pre-emphasis value. 5 www.national.com DS99R105/DS99R106

DS99R105 Serializer Pin Descriptions Pin # Pin Name I/O Description LVCMOS PARALLEL INTERFACE PINS 4-1, 48-44, 41-32, 29-25 DIN[23:0] LVCMOS_I Transmitter Parallel Interface Data Inputs Pins. Tie LOW if unused, do not float. 10 TCLK LVCMOS_I Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin. CONTROL AND CONFIGURATION PINS

9 TPWDNB LVCMOS_I Transmitter Power Down Bar

TPWDNB = H; Transmitter is Enabled and ON TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS Driver DOUT (+/-) Outputs are in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.

18 DEN LVCMOS_I Transmitter Data Enable

DEN = H; LVDS Driver Outputs are Enabled (ON). DEN = L; LVDS Driver Outputs are Disabled (OFF), Transmitter LVDS Driver DOUT (+/-) Outputs are in TRI-STATE, PLL still operational and locked to TCLK. 23 PRE LVCMOS_I PRE-emphasis select pin. PRE = L; Pre-emphasis is enabled PRE = H; Pre-emphasis is disabled

11 TRFB LVCMOS_I Transmitter Clock Edge Select Pin

TRFB = H; Parallel Interface Data is strobed on the Rising Clock Edge TRFB = L; Parallel Interface Data is strobed on the Falling Clock Edge

12 VODSEL LVCMOS_I VOD Level Select

VODSEL = L; LVDS Driver Output is ±400 mV (RL = 100Ω) VODSEL = H; LVDS Driver Output is ±750 mV (RL = 100Ω) For normal applications, set this pin LOW. For long cable applications where a larger VOD is required, set this pin HIGH. 5 DCAOFF LVCMOS_I RESERVED – This pin MUST be tied LOW. 8 DCBOFF LVCMOS_I RESERVED – This pin MUST be tied LOW. 13 RESRVD LVCMOS_I RESERVED – This pin MUST be tied LOW. LVDS SERIAL INTERFACE PINS 20 DOUT+ LVDS_O Transmitter LVDS True (+) Output. This output is intended to be loaded with a 100 ohm load to the DOUT+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor. 19 DOUT− LVDS_O Transmitter LVDS Inverted (-) Output This output is intended to be loaded with a 100 ohm load to the DOUT- pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor. POWER / GROUND PINS

22 VDDDR VDD Analog Voltage Supply, LVDS Output Power

21 VSSDR GND Analog Ground, LVDS Output Ground

16 VDDPT0 VDD Analog Voltage supply, VCO Power

17 VSSPT0 GND Analog Ground, VCO Ground

14 VDDPT1 VDD Analog Voltage supply, PLL Power

15 VSSPT1 GND Analog Ground, PLL Ground

30 VDDT VDD Digital Voltage supply, Tx Serializer Power

31 VSST GND Digital Ground, Tx Serializer Ground

7 VDDL VDD Digital Voltage supply, Tx Logic Power

6 VSSL GND Digital Ground, Tx Logic Ground

42 VDDIT VDD Digital Voltage supply, Tx Input Power

43 VSSIT GND Digital Ground, Tx Input Ground

24 VSS GND ESD Ground

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DS99R106 Deserializer Pin Descriptions Pin # Pin Name I/O Description LVCMOS PARALLEL INTERFACE PINS 25-28, 31-34 ROUT[7:0] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 1 13-16, 21-24 ROUT[15:8] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 2 3-6, 9-12 ROUT[23:16] LVCMOS_O Receiver Parallel Interface Data Outputs – Group 3 18 RCLK LVCMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin. CONTROL AND CONFIGURATION PINS

43 RRFB LVCMOS_I Receiver Clock Edge Select Pin

RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge. RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.

48 REN LVCMOS_I Receiver Data Enable

REN = H; ROUT[23-0] and RCLK are Enabled (ON). REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs are in TRI-STATE, PLL still operational and locked to TCLK.

1 RPWDNB LVCMOS_I Receiver Data Enable

REN = H; ROUT[23-0] and RCLK are Enabled (ON). REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs are in TRI-STATE, PLL still operational and locked to TCLK.

17 LOCK LVCMOS_O LOCK indicates the status of the receiver PLL

LOCK = H; receiver PLL is locked LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED 2 RESRVD LVCMOS_I RESERVED – This pin MUST be tied LOW. LVDS SERIAL INTERFACE PINS 41 RIN+ LVDS_I Receiver LVDS True (+) Input This input is intended to be terminated with a 100 ohm load to the RIN+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor. 42 RIN− LVDS_I Receiver LVDS Inverted (−) Input This input is intended to be terminated with a 100 ohm load to the RIN- pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor. POWER / GROUND PINS

39 VDDIR VDD Analog LVDS Voltage supply, Power

40 VSSIR GND Analog LVDS Ground

47 VDDPR0 VDD Analog Voltage supply, PLL Power

46 VSSPR0 GND Analog Ground, PLL Ground

45 VDDPR1 VDD Analog Voltage supply, PLL VCO Power

44 VSSPR1 GND Analog Ground, PLL VCO Ground

37 VDDR1 VDD Digital Voltage supply, Logic Power

38 VSSR1 GND Digital Ground, Logic Ground

36 VDDR0 VDD Digital Voltage supply, Logic Power

35 VSSR0 GND Digital Ground, Logic Ground

30 VDDOR1 VDD Digital Voltage supply, LVCMOS Output Power

29 VSSOR1 GND Digital Ground, LVCMOS Output Ground

20 VDDOR2 VDD Digital Voltage supply, LVCMOS Output Power

19 VSSOR2 GND Digital Ground, LVCMOS Output Ground

7 VDDOR3 VDD Digital Voltage supply, LVCMOS Output Power

8 VSSOR3 GND Digital Ground, LVCMOS Output Ground

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The DS99R105 Serializer and DS99R106 Deserializer chipset is an easy-to-use transmitter and receiver pair that sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 72 Mbps to 960 Mbps throughput. The DS99R105 transforms a 24-bit wide parallel LVCMOS data into a single high speed LVDS serial data stream with em- bedded clock. The DS99R106 receives the LVDS serial data stream and converts it back into a 24-bit wide parallel data and recovered clock. The 24-bit Serializer/Deserializer chipset is designed to transmit data over shielded twisted pair (STP) at clock speeds from 3 MHz to 40 MHz. The Deserializer can attain lock to a data stream without the use of a separate reference clock source. The Deserializer synchronizes to the Serializer regardless of data pattern, de- livering true automatic “plug and lock” performance. The De- serializer recovers the clock and data by extracting the embedded clock information and validating data integrity from the incoming data stream and then deserializes the data. The Deserializer monitors the incoming clock information, deter- mines lock status, and asserts the LOCK output high when lock occurs. Each has a power down control to enable efficient operation in various applications. INITIALIZATION AND LOCKING MECHANISM Initialization of the DS99R105 and DS99R106 must be es- tablished before each device sends or receives data. Initial- ization refers to synchronizing the Serializer’s and Deserializer’s PLL’s together. After the Serializers locks to the input clock source, the Deserializer synchronizes to the Seri- alizers as the second and final initialization step. Step 1: When VDD is applied to both Serializer and/or Dese- rializer, the respective outputs are held in TRI-STATE and internal circuitry is disabled by on-chip power-on circuitry. When VDD reaches VDD OK (2.2V) the PLL in Serializer begins locking to a clock input. For the Serializer, the local clock is the transmit clock, TCLK. The Serializer outputs are held in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the Serializer block is now ready to send data patterns. The Deserializer output will remain in TRI-STATE while its PLL locks to the embedded clock information in serial data stream. Also, the Deserializer LOCK output will remain low until its PLL locks to incoming data and sync-pattern on the RIN± pins. Step 2: The Deserializer PLL acquires lock to a data stream without requiring the Serializer to send special patterns. The Serializer that is generating the stream to the Deserializer will automatically send random (non-repetitive) data patterns dur- ing this step of the Initialization State. The Deserializer will lock onto embedded clock within the specified amount of time. An embedded clock and data recovery (CDR) circuit locks to the incoming bit stream to recover the high-speed receive bit clock and re-time incoming data. The CDR circuit expects a coded input bit stream. In order for the Deserializer to lock to a random data stream from the Serializer, it performs a series of operations to identify the rising clock edge and validates data integrity, then locks to it. Because this locking procedure is independent on the data pattern, total random locking du- ration may vary. At the point when the Deserializer’s CDR locks to the embedded clock, the LOCK pin goes high and valid RCLK/data appears on the outputs. Note that the LOCK signal is synchronous to valid data appearing on the outputs. The Deserializer’s LOCK pin is a convenient way to ensure data integrity is achieved on receiver side. DATA TRANSFER After lock is established, the Serializer inputs DIN0–DIN23 are used to input data to the Serializer. Data is clocked into the Serializer by the TCLK input. The edge of TCLK used to strobe the data is selectable via the TRFB pin. TRFB high selects the rising edge for clocking data and low selects the falling edge. The Serializer outputs (DOUT±) are intended to drive point-to-point connections or limited multi-point applica- tions. CLK1, CLK0, DCA, DCB are four overhead bits transmitted along the single LVDS serial data stream. The CLK1 bit is always high and the CLK0 bit is always low. The CLK1 and CLK0 bits function as the embedded clock bits in the serial stream. DCB functions as the DC Balance control bit. It does not require any pre-coding of data on transmit side. The DC Balance bit is used to minimize the short and long-term DC bias on the signal lines. This bit operates by selectively send- ing the data either unmodified or inverted. The DCA bit is used to validate data integrity in the embedded data stream. Both DCA and DCB coding schemes are integrated and automat- ically performed within Serializer and Deserializer. The chipset supports clock frequency ranges of 3 MHz to 40 MHz. Every clock cycle, 24 databits are sent along with 4 ad- ditional overhead control bits. Thus the line rate is 1.12 Gbps maximum (84 Mbps minimum). The link is extremely efficient at 86% (24/28). Twenty five (24 data + 1 clock) plus associ- ated ground signals are reduced to only 1 single LVDS pair providing a compression ratio of better then 25 to 1. Serialized data and clock/control bits (24+4 bits) are trans- mitted from the serial data output (DOUT±) at 28 times the TCLK frequency. For example, if TCLK is , the serial rate is 40 x 28 = 1.12 Giga bits per second. Since only 24 bits are from input data, the serial “payload” rate is 24 times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data rate is 40 x 24 = 960 Mbps. TCLK is provided by the data source and must be in the range of 3 MHz to 40 MHz nominal. The Serializer outputs (DOUT±) can drive a point-to-point connection as shown in Figure 17. The outputs transmit data when the enable pin (DEN) is high and TPWDNB is high. The DEN pin may be used to TRI-STATE the outputs when driven low. When the Deserializer channel attains lock to the input from a Serializer, it drives its LOCK pin high and synchronously delivers valid data and recovered clock on the output. The Deserializer locks onto the embedded clock, uses it to gen- erate multiple internal data strobes, and then drives the re- covered clock to the RCLK pin. The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[23:0] pins. While LOCK is high, data on ROUT[23:0] is valid. Oth- erwise, ROUT[23:0] is invalid. The polarity of the RCLK edge is controlled by the RRFB input. ROUT(0-23), LOCK and RCLK outputs will each drive a maximum of 8 pF load with a 40 MHz clock. REN controls TRI-STATE for ROUTn and the RCLK pin on the Deserializer. RESYNCHRONIZATION If the Deserializer loses lock, it will automatically try to re-es- tablish lock. For example, if the embedded clock edge is not detected one time in succession, the PLL loses lock and the LOCK pin is driven low. The Deserializer then enters the op- erating mode where it tries to lock to a random data stream. It looks for the embedded clock edge, identifies it and then proceeds through the locking process. The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is high, the data is valid. The system www.national.com 16 DS99R105/DS99R106

must monitor the LOCK pin to determine whether data on the ROUT is valid. POWERDOWN The Powerdown state is a low power sleep mode that the Se- rializer and Deserializer may use to reduce power when no data is being transferred. The TPWDNB and RPWDNB are used to set each device into power down mode, which re- duces supply current to the µA range. The Serializer enters powerdown when the TPWDNB pin is driven low. In power- down, the PLL stops and the outputs go into TRI-STATE, disabling load current and reducing supply. To exit Power- down, TPWDNB must be driven high. When the Serializer exits Powerdown, its PLL must lock to TCLK before it is ready for the Initialization state. The system must then allow time for Initialization before data transfer can begin. The Deserializer enters powerdown mode when RPWDNB is driven low. In powerdown mode, the PLL stops and the outputs enter TRI- STATE. To bring the Deserializer block out of the powerdown state, the system drives RPWDNB high. Both the Serializer and Deserializer must reinitialize and re- lock before data can be transferred. The Deserializer will initialize and assert LOCK high when it is locked to the en- coded clock. TRI-STATE For the Serializer, TRI-STATE is entered when the DEN or TPWDNB pin is driven low. This will TRI-STATE both driver output pins (DOUT+ and DOUT−). When DEN is driven high, the serializer will return to the previous state as long as all other control pins remain static (TPWDNB, TRFB). When you drive the REN or RPWDNB pin low, the Deserial- izer enters TRI-STATE. Consequently, the receiver output pins (ROUT0–ROUT23) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the state of the PLL. The Deserializer input pins are high impedance during receiver powerdown (RPWDNB low) and power-off (V DD = 0V). PRE-EMPHASIS The DS99R105 features a Pre-Emphasis mode used to com- pensate for long or lossy transmission media. Cable drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output current during transitions to coun- teract cable loading effects. The transmission distance will be limited by the loss characteristics and quality of the media. Pre-Emphasis adds extra current during LVDS logic transition to reduce the cable loading effects and increase driving dis- tance. In addition, Pre-Emphasis helps provide faster transi- tions, increased eye openings, and improved signal integrity. The ability of the DS99R105 to use the Pre-Emphasis feature will extend the transmission distance in most cases. AC-COUPLING AND TERMINATION The DS99R105 and DS99R106 supports AC-coupled inter- connects through integrated DC balanced encoding/decoding scheme. To use AC coupled connection between the Serial- izer and Deserializer, insert external AC coupling capacitors in series in the LVDS signal path as illustrated in Figure 17. The Deserializer input stage is designed for AC-coupling by providing a built-in AC bias network which sets the internal VCM to +1.2V. With AC signal coupling, capacitors provide the ac-coupling path to the signal input. For the high-speed LVDS transmissions, the smallest avail- able package should be used for the AC coupling capacitor. This will help minimize degradation of signal quality due to package parasitics. The most common used capacitor value for the interface is 100 nF (0.1 uF) capacitor. A termination resistor across DOUT± is also required for proper operation to be obtained. The termination resistor should be equal to the differential impedance of the media being driven. This should be in the range of 90 to 132 Ohms.

100 Ohms is a typical value common used with standard 100

Ohm transmission media. This resistor is required for control of reflections and also to complete the current loop. It should be placed as close to the Serializer DOUT± outputs to mini- mize the stub length from the pins. To match with the defer- ential impedance on the transmission line, the LVDS I/O are terminated with 100 ohm resistors on Serializer DOUT± out- puts pins. PROGRESSIVE TURN–ON (PTO) Deserializer ROUT[23:0] outputs are grouped into three groups of eight, with each group switching about 0.5UI apart in phase to reduce EMI, simultaneous switching noise, and system ground bounce. Applications Information USING THE DS99R105 AND DS99R106 The DS99R105/DS99R106 Serializer/Deserializer (SERDES) pair sends 24 bits of parallel LVCMOS data over a serial LVDS link up to 960 Mbps. Serialization of the input data is accomplished using an on-board PLL at the Serializer which embeds clock with the data. The Deserializer extracts the clock/control information from the incoming data stream and deserializes the data. The Deserializer monitors the in- coming clockl information to determine lock status and will indicate lock by asserting the LOCK output high. POWER CONSIDERATIONS An all CMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally, the constant current source nature of the LVDS outputs minimize the slope of the speed vs. IDD curve of CMOS designs. NOISE MARGIN The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still reli- ably recover data. Various environmental and systematic fac- tors include: Serializer: TCLK jitter, VDD noise (noise bandwidth and out- of-band noise) Media: ISI, V CM noise Deserializer: V DD noise For a graphical representation of noise margin, please see Figure 16. TRANSMISSION MEDIA The Serializer and Deserializer can be used in point-to-point configuration, through a PCB trace, or through twisted pair cable. In a point-to-point configuration, the transmission me- dia needs be terminated at both ends of the transmitter and receiver pair. Interconnect for LVDS typically has a differential impedance of 100 Ohms. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. In most applications that involve cables, the transmission distance will be determined on data rates in- volved, acceptable bit error rate and transmission medium. 17 www.national.com DS99R105/DS99R106

lock to the active data stream during a live insertion event. planes, reducing the impedance at high frequency. ing noise effects between different sections of the circuit. sensitive circuits such as PLLs. Use at least a four layer board with a power and ground plane. to prevent coupling from the LVCMOS lines to the LVDS lines. coupled lines will also radiate less. See AN-1108 and AN-905 for full details.

• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings —S = space between the pair —2S = space between pairs —3S = space to LVCMOS/LVTTL signal
• Minimize the number of VIA
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the National web site at: www.national.com/lvds 20208118

FIGURE 17. AC Coupled Application

FIGURE 18. DS99R105 Typical Application Connection

FIGURE 19. DS99R106 Typical Application Connection

TABLE 1. DS99R105 Serializer Truth Table TABLE 2. DS99R106 Deserializer Truth Table

Physical Dimensions inches (millimeters) unless otherwise noted Dimensions show in millimeters only

Ordering Information

DS99R105VS 48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch VBC48A DS99R105VSX 48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch, 1000 std reel VBC48A DS99R106VS 48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch VBC48A DS99R106VSX 48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch, 1000 std reel VBC48A www.national.com 22 DS99R105/DS99R106

Physical Dimensions inches (millimeters) unless otherwise noted Dimensions show in millimeters only DS99R105SQ 48 Lead LLP style, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch SQA48D DS99R105SQX 48 Lead LLP style, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch, 1000 std reel SQA48D DS99R106SQ 48 Lead LLP style, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch SQA48D DS99R106SQX 48 Lead LLP style, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch, 1000 std reel SQA48D 23 www.national.com DS99R105/DS99R106

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