DS99R105VSX/NOPB

Texas Instruments

DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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DS99R105,DS99R106 www.ti.com SNLS242D –MARCH 2007–REVISED APRIL 2013 DS99R105/DS99R1063-40MHzDC-Balanced24-BitLVDSSerializerandDeserializer Check forSamples: DS99R105 ,DS99R106 1FEATURES DESCRIPTION The DS99R105/DS99R106 Chipsettranslatesa 24- 2• 3 MHz –40 MHz Clock Embedded and DC- bitparallelbus intoa fullytransparentdata/controlBalancing24:1and 1:24Data Transmissions LVDS serialstreamwithembedded clockinformation.• Capable toDriveShieldedTwisted-PairCable Thissingleserialstreamsimplifiestransferringa 24-

User SelectableClock Edge forParallelData bitbus overPCB tracesand cableby eliminatingthe skew problems between paralleldata and clockon Both Transmitterand Receiver paths.Itsaves system costby narrowingdatapaths• InternalDC BalancingEncode/Decode – thatin turnreduce PCB layers,cable width,andSupports AC-Coupling Interfacewithno connectorsizeand pins.ExternalCoding Required The DS99R105/DS99R106 incorporates LVDS• IndividualPower-Down ControlsforBoth signalingon thehigh-speedI/O.LVDS providesa lowTransmitterand Receiver power and low noise environment for reliably• Embedded Clock CDR (Clockand Data transferringdata over a serialtransmissionpath.By Recovery)on Receiverand no ExternalSource optimizingthe serializeroutputedge rate for the ofReferenceClock Needed operatingfrequencyrangeEMI isfurtherreduced.
AllCodes RDL (Random Data Lock) toSupport Inadditionthedevicefeaturespre-emphasistoboost Live-PluggableApplications signalsover longerdistancesusing lossy cables. InternalDC balancedencoding/decodingisused to• LOCK Output FlagtoEnsure Data Integrityat supportAC-Coupled interconnects.ReceiverSide
Balanced TSETUP /THOLD between RCLK and RDATA on ReceiverSide
PTO (ProgressiveTurn-On)LVCMOS Outputs toReduce EMI and MinimizeSSO Effects
AllLVCMOS Inputsand ControlPins have InternalPulldown
On-Chip FiltersforPLLs on Transmitterand Receiver
Integrated100Ω InputTerminationon Receiver
4 mA ReceiverOutput Drive
48-PinTQFP and 48-PinWQFN Packages
Pure CMOS .35μm Process
Power Supply Range 3.3V± 10%
Temperature Range 0°C to+70°C
8 kV HBM ESD Tolerance Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2007–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SERIALIZER ± DS99R105 PLL Timing and Control D OUT - R T = 100 RT = 100 (Integrated )R IN- DESERIALIZER ± DS99R106 D OUT + R IN+ PLL Timing and Control R OUT LOCK RCLKClock Recovery Output Latch Serial to Parallel DC Balance Decode Input Latch Parallel to Serial DC Balance Encode CLK1bit0bit1bit2bit3bit4bit5bit bit bit bit bit bit DCA DCB bit bit bit bit bit bit bit bit bit bit bit bit CLK0 PRE (on/off) DS99R105,DS99R106 SNLS242D –MARCH 2007–REVISED APRIL 2013 www.ti.com Block Diagram Figure1. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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DS99R105,DS99R106 www.ti.com SNLS242D –MARCH 2007–REVISED APRIL 2013 AbsoluteMaximum Ratings (1)(2) SupplyVoltage(VDD ) −0.3Vto+4V LVCMOS/LVTTL InputVoltage −0.3Vto(VDD +0.3V) LVCMOS/LVTTL OutputVoltage −0.3Vto(VDD +0.3V) LVDS ReceiverInputVoltage −0.3Vto3.9V LVDS DriverOutputVoltage −0.3Vto3.9V LVDS OutputShortCircuitDuration 10 ms JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature (Soldering,4 seconds) +260°C Maximum Package Power DissipationCapacityPackage De-rating: 48L TQFP 1/θJA °C/W above +25°C DS99R105 θJA 45.8(4L*);75.4(2L*)°C/W θJC 21.0°C/W DS99R106 θJA 45.4(4L*);75.0(2L*)°C/W θJC 21.1°C/W 48L WQFN 1/θJA °C/W above +25°C DS99R105 θJA 28 (4L*);79.1(2L*)°C/W θJC 3.7°C/W DS99R106 θJA 28 (4L*);79.1(2L*)°C/W θJC 3.71°C/W *JEDEC ESD Rating(HBM) ≥±8 kV (1) “AbsoluteMaximum Ratings”indicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingConditions Min Nom Max Units SupplyVoltage(VDD ) 3.0 3.3 3.6 V OperatingFreeAir Temperature(TA) 0 +25 +70 °C ClockRate 3 40 MHz SupplyNoise ±100 mV P-P Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS99R105 DS99R106

DS99R105,DS99R106 SNLS242D –MARCH 2007–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics(1)(2)(3) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Parameter TestConditions Pin/Freq. Min Typ Max Units LVCMOS/LVTTL DC SPECIFICATIONS VIH HighLevelVoltage Tx:DIN[23:0],TCLK, 2.0 1.5 VDD V TPWDNB, DEN, TRFB,VIL Low LevelInputVoltage GND 1.5 0.8 VDCAOFF, DCBOFF, VCL InputClamp Voltage ICL = −18 mA VODSEL (4) −0.8 −1.5 VRx: RPWDNB, RRFB, REN IIN InputCurrent VIN = 0V or3.6V Tx:DIN[23:0],TCLK, TPWDNB, DEN, TRFB, −10 ±1 +10 µADCAOFF, DCBOFF, VODSEL Rx: RPWDNB, RRFB, −20 ±5 +20 µAREN VOH HighLevelOutputVoltage IOH = −4 mA Rx: ROUT[23:0],RCLK, 2.3 3.0 VDD V LOCKVOL Low LevelOutputVoltage IOL = +4 mA GND 0.33 0.5 V IOS OutputShortCircuitCurrent VOUT = 0V −40 −70 −110 mA(4) IOZ TRI-STATE OutputCurrent RPWDNB, REN = 0V Rx: ROUT[23:0],RCLK, −30 ±0.4 +30 µAVOUT = 0V or2.4V LOCK LVDS DC SPECIFICATIONS VTH DifferentialThresholdHigh VCM = +1.2V Rx: R IN+,R IN− +50 mVVoltage VTL DifferentialThresholdLow −50 mVVoltage IIN InputCurrent VIN = +2.4V, ±300 µAVDD = 3.6V VIN = 0V,VDD = 3.6V ±300 µA R T DifferentialInternal 90 100 130 ΩTerminationResistance VOD OutputDifferentialVoltage R L = 100Ω,w/o Pre-emphasis Tx:D OUT+ ,D OUT − 250 400 600 mV(DOUT+ )–(DOUT −) VODSEL = L (Figure11) R L = 100Ω,w/o Pre-emphasis 450 750 1200 mVVODSEL = H (Figure11) ΔVOD OutputDifferentialVoltage R L = 100Ω,w/o Pre-emphasis 4 50 mVUnbalance VOS OffsetVoltage R L = 100Ω,w/o Pre-emphasis 1.00 1.25 1.50 V ΔVOS OffsetVoltageUnbalance R L = 100Ω,w/o Pre-emphasis 1 50 mV IOS OutputShortCircuitCurrent DOUT = 0V,DIN = H, TPWDNB, DEN = 2.4V, −2 −5 −8 mA VODSEL = L DOUT = 0V,DIN = H, TPWDNB, DEN = 2.4V, −7 −10 −13 mA VODSEL = H IOZ TRI-STATE OutputCurrent TPWDNB, DEN = 0V, −15 ±1 +15 µADOUT = 0V or2.4V (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms atVDD = 3.3V,Ta = +25 degC, and attheRecommended OperationConditions atthetimeofproductcharacterizationand arenotensured. (3) Currentintodevicepinsisdefinedas positive.Currentoutofa devicepinisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages. (4) Specificationisensuredby characterizationand isnottestedinproduction.

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DS99R105,DS99R106 www.ti.com SNLS242D –MARCH 2007–REVISED APRIL 2013 ElectricalCharacteristics(1)(2)(3)(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Parameter TestConditions Pin/Freq. Min Typ Max Units SER/DES SUPPLY CURRENT (DVDD*, PVDD* and AVDD* pins)*Digital,PLL, and Analog VDDs IDDT Serializer(Tx) R L = 100Ω f= 40 MHz TotalSupplyCurrent Pre-emphasis= OFF 40 80 mA(includesloadcurrent) VODSEL = L Checker-boardpattern(Figure2) R L = 100Ω f= 40 MHz Pre-emphasis= ON 45 85 mAVODSEL = L Checker-boardpattern(Figure2) Serializer(Tx) R L = 100Ω f= 40 MHz TotalSupplyCurrent Pre-emphasis= OFF 40 85 mA(includesloadcurrent) VODSEL = H Checker-boardpattern(Figure2) R L = 100Ω f= 40 MHz Pre-emphasis= ON 45 90 mAVODSEL = H Checker-boardpattern(Figure2) IDDTZ Serializer(Tx) TPWDNB = 0V 1 100 µASupplyCurrentPower-down (AllotherLVCMOS Inputs= 0V) IDDR Deserializer(Rx) C L = 8 pF LVCMOS Output f= 40 MHz TotalSupplyCurrent Checker-boardpattern 95 mA (includesloadcurrent) (Figure3) Deserializer(Rx) C L = 8 pF LVCMOS Output f= 40 MHz TotalSupplyCurrent Random pattern 90 mA (includesloadcurrent) IDDRZ Deserializer(Rx) RPWDNB = 0V SupplyCurrentPower-down (AllotherLVCMOS Inputs= 0V, 1 50 µA R IN+/R IN-= 0V) SerializerTiming Requirements forTCLK (1)(2) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Parameter TestConditions Min Typ Max Units tTCP TransmitClockPeriod (Figure6) 25 T 333 ns tTCIH TransmitClockHighTime 0.4T 0.5T 0.6T ns tTCIL TransmitClockLow Time 0.4T 0.5T 0.6T ns tCLKT TCLK InputTransitionTime (Figure5) 3 6 ns tJIT TCLK InputJitter (3) 33 ps (RMS) (1) Figure2,Figure3,Figure9,Figure13,and Figure15 show a fallingedge datastrobe(TCLK IN/RCLK OUT). (2) Figure6 and Figure16 show a risingedge datastrobe(TCLK IN/RCLK OUT). (3) tJIT(@BER of10e-9)specifiestheallowablejitteron TCLK. tJITnotincludedinTxOUT_E_O parameter. SerializerSwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Parameter TestConditions Min Typ Max Units tLLHT LVDS Low-to-HighTransitionTime R L = 100Ω,(Figure4) 0.6 ns C L = 10 pF toGNDtLHLT LVDS High-to-LowTransitionTime 0.6 nsVODSEL = L tDIS DIN (23:0)SetuptoTCLK R L = 100Ω, 5 ns C L = 10 pF toGNDtDIH DIN (23:0)HoldfromTCLK 5 ns(1) (1) Specificationisensuredby characterizationand isnottestedinproduction. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS99R105 DS99R106

DS99R105,DS99R106 SNLS242D –MARCH 2007–REVISED APRIL 2013 www.ti.com SerializerSwitchingCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Parameter TestConditions Min Typ Max Units tHZD DOUT ± HIGH toTRI-STATE Delay R L = 100Ω, 15 ns C L = 10 pF toGNDtLZD DOUT ± LOW toTRI-STATE Delay 15 ns(Figure7)(2) tZHD DOUT ± TRI-STATE toHIGH Delay 200 ns tZLD DOUT ± TRI-STATE toLOW Delay 200 ns tPLD SerializerPLL Lock Time R L = 100Ω,(Figure8) 10 ms tSD SerializerDelay R L = 100Ω,(Figure9) 3.5T+ 3.5T+ nsVODSEL = L,TRFB = H 2.85 10 R L = 100Ω,(Figure9) 3.5T+ 3.5T+ nsVODSEL = L,TRFB = L 2.85 10 TxOUT_E_O TxOUT_Eye_Opening 3–40 MHz UI0.68(respecttoideal) (Figure10)(3)(4) (5) (2) When theSerializeroutputistri-stated,theDeserializerwilllosePLL lock.ResynchronizationMUST occurbeforedatatransfer. (3) tJIT(@BER of10e-9)specifiestheallowablejitteron TCLK. tJITnotincludedinTxOUT_E_O parameter. (4) TxOUT_E_O isaffectedby pre-emphasisvalue. (5) UI – UnitInterval,equivalenttoone idealserializeddatabitwidth.The UI scaleswithfrequency. DeserializerSwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Parameter TestConditions Pin/Freq. Min Typ Max Units tRCP R eceiveroutC lockPeriod tRCP = tTCP (1) RCLK 25 T 333 ns tRDC R CLK D utyC ycle RCLK 45 50 55 % tCLH LVC MOS Low-to-H igh C L = 8 pF ROUT [23:0], 2.5 3.5 nsTransitionTime (lumpedload) LOCK, RCLK (Figure12)tCHL LVC MOS H igh-to-Low 2.5 3.5 nsTransitionTime tROS RO UT (7:0)SetupData toRCLK (Figure16) ROUT [7:0] (0.40)* (29/56)*tRCP ns(Group1) tRCP tROH RO UT (7:0)H oldData toRCLK (0.40)* (27/56)*tRCP ns(Group1) tRCP tROS RO UT (15:8)SetupData toRCLK (Figure16) ROUT [15:8], (0.40)* 0.5*tRCP ns(Group2) LOCK tRCP tROH RO UT (15:8)H oldData toRCLK (0.40)* 0.5*tRCP ns(Group2) tRCP tROS RO UT (23:16)SetupData to (Figure16) ROUT [23:16] (0.40)* (27/56)*tRCP nsRCLK (Group3) tRCP tROH RO UT (23:16)H oldData toRCLK (0.40)* (29/56)*tRCP ns(Group3) tRCP tHZR H IGH toTRI-STATE Delay (Figure14) ROUT [23:0], 3 10 ns RCLK, LOCKtLZR LOW toTRI-STATE Delay 3 10 ns tZHR TRI-STATE toH IGH Delay 3 10 ns tZLR TRI-STATE toLOW Delay 3 10 ns tDD D eserializerD elay (Figure13) RCLK [4+(3/56)]T[4+(3/56)]T ns +5.9 +18.5 tDRDL DeserializerPLL Lock Time from (Figure15) 3 MHz 5 50 ms Powerdown (2)(1)

40 MHz 5 50 ms

RxIN_TOL_L R eceiverINputTOL eranceLeft (Figure17) (3)(1)(4) 3 MHz –40 MHz 0.25 UI RxIN_TOL_R R eceiverINputTOL eranceR ight (Figure17) (3)(1)(4) 3 MHz –40 MHz 0.25 UI (1) Specificationisensuredby characterizationand isnottestedinproduction. (2) The DeserializerPLL locktime(tDRDL )may varydependingon inputdatapatternsand thenumber oftransitionswithinthepattern. (3) RxIN_TOL isa measure ofhow much phase noise(jitter)thedeserializercan tolerateintheincomingdatastreambeforebiterrors occur.Itisa measurement inreferencewiththeidealbitposition,pleasesee TI’s AN-1217 (SNLA053 )fordetail. (4) UI – UnitInterval,equivalenttoone idealserializeddatabitwidth.The UI scaleswithfrequency.

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80% 20% 80% 20% tCLKT tCLK TCLK VDD 80% 20% 80% 20% Vdiff = 0V tLLHT tLHLT Differential Signal Vdiff = (DOUT+) - (DOUT-) 100: DOUT+ DOUT- 10 pF 10 pF RCLK ODD ROUT EVEN ROUT Signal PatternDevice Pin Name TCLK ODD DIN EVEN DIN Signal PatternDevice Pin Name DS99R105,DS99R106 www.ti.com SNLS242D –MARCH 2007–REVISED APRIL 2013 AC Timing Diagrams and TestCircuits See SerializerTimingRequirementsforTCLK Note (1). Figure2. SerializerInputChecker-boardPattern See SerializerTimingRequirementsforTCLK Note (1). Figure3. DeserializerOutput Checker-boardPattern Figure4. SerializerLVDS Output Load and TransitionTimes Figure5. SerializerInputClock TransitionTimes Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS99R105 DS99R106

100: Parasitic package and Trace capcitance 200 mV DCA DCA DCA DCA $OOGDWD³0´V CLK1 tZLD tTCP DCADCADCADCA CLK1 tTCP 200 mV DEN (single-ended) 200 mV DCA DCA DCA DCA $OOGDWD³1´V CLK0 tZHD tTCP DCADCADCADCA CLK0 tTCP 200 mV DOUT± (differential) VCC /2 DOUT± (differential) VCC /2 tHZD DEN (single-ended) VCC /2 0V 0V VCC /2 tLZD SetupVDD /2 Hold tDIHtDIS TCLK DIN [0:23] tTCP VDD /2 VDD /2 V DD /2VDD /2 VDD DS99R105,DS99R106 SNLS242D –MARCH 2007–REVISED APRIL 2013 www.ti.com See SerializerTimingRequirementsforTCLK Note (2). Figure6. SerializerSetup/HoldTimes Figure7. SerializerTRI-STATE TestCircuitand Delay

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Ideal Center Position (tBIT/2) tBIT (1UI) TxOUT_E_O Ideal Data Bit End Ideal Data Bit Beginning tBIT(1/2UI) tBIT(1/2UI) 232 1 0 START BIT STOP BITSYMBOL N 232 1 0 START BIT STOP BITSYMBOL N-1 232 1 0 START BIT STOP BITSYMBOL N-2 232 1 0 START BIT STOP BITSYMBOL N-3 232 1 0 STOP BITSYMBOL N-4 DOUT0-23 DCA, DCB TCLK tSD DIN SYMBOL N+1SYMBOL N SYMBOL N+2 SYMBOL N+3 | | 2.0V 0.8V TCLK DOUT± tHZD or tLZD tZHD or tZLD Output Active tPLD PWDWN TRI-STATE TRI-STATE DS99R105,DS99R106 www.ti.com SNLS242D –MARCH 2007–REVISED APRIL 2013 Figure8. SerializerPLL Lock Time,and TPWDNB TRI-STATE Delays See SerializerTimingRequirementsforTCLK Note (1). Figure9. SerializerDelay Figure10. TransmitterOutput Eye Opening (TxOUT_E_O) VOD = (DOUT+ )– (DOUT -) Differentialoutputsignalisshown as (DOUT+ )– (DOUT -),deviceinData Transfermode. Figure11. SerializerVOD Diagram Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS99R105 DS99R106

VOL + 0.5V VOL ROUT [23:0] VOL + 0.5V tLZR 500: VREF = VDD /2 for tZLR or tLZR , VOH - 0.5V VOH + 0.5V tZLR tHZR tZHR VDD /2 VDD /2 VOH VOL REN VREF + - VREF = 0V for tZHR or tHZRC L = 8pF 232 1 0 START BIT STOP BITSYMBOL N+3 232 1 0 START BIT STOP BITSYMBOL N+2 232 1 0 START BIT STOP BITSYMBOL N+1 232 1 0 START BIT STOP BITSYMBOL N RIN0-23 DCA, DCB RCLK tDD ROUT0-23 SYMBOL N-1 SYMBOL NSYMBOL N-2SYMBOL N-3 80% 20% 80% 20% tCLH Deserializer 8 pF lumped Single-ended Signal tCHL DS99R105,DS99R106 SNLS242D –MARCH 2007–REVISED APRIL 2013 www.ti.com Figure12. DeserializerLVCMOS/LVTTL Output Load and TransitionTimes See SerializerTimingRequirementsforTCLK Note (1). Figure13. DeserializerDelay Note:C L includesinstrumentationand fixturecapacitancewithin6 cm ofROUT[23:0] Figure14. DeserializerTRI-STATE TestCircuitand Timing

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After RCLKROUT [7:0] Data Valid Before RCLK Data Valid After RCLKROUT [15:8], LOCK Data Valid Before RCLK Data Valid After RCLK VDD /2ROUT [23:16] RCLK tLOW tHIGH tROS tROH tROS tROH (group 1) (group 1) (group 2) (group 2) 1/2 UI 1/2 UI tROS tROH (group 3) (group 3) 1/2 UI 1/2 UI VDD /2 VDD /2VDD /2 VDD /2VDD /2 VDD /2VDD /2 RIN± TRI-STATE TRI-STATE TRI-STATE TRI-STATE TRI-STATE ROUT [0:23] RCLK TRI-STATELOCK }v[ tHZR or tLZR tDRDL REN PWDN 2.0V 0.8V DS99R105,DS99R106 www.ti.com SNLS242D –MARCH 2007–REVISED APRIL 2013 See SerializerTimingRequirementsforTCLK Note (1). Figure15. DeserializerPLL Lock Times and RPWDNB TRI-STATE Delay See SerializerTimingRequirementsforTCLK Note (2). Figure16. DeserializerSetup and Hold Times Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS99R105 DS99R106

48DIN[19] 47DIN[18] 46DIN[17] 45DIN[16] 44DIN[15] 43VSSIT 42VDDIT 41DIN[14] 40DIN[13] 39DIN[12] 38DIN[11] 37DIN[10] RESRVD VDDPT1 VSSPT1 VDDPT0 VSSPT0 DEN DOUT- DOUT+ VSSDR VDDDR PRE VSS VODSEL TRFB TCLK TPWDNB DCBOFF VDD L VSS L DCAOFF DIN[23] DIN[22] DIN[21] DIN[20] 252627282930313233343536 DIN[0]DIN[1]DIN[2]DIN[3]DIN[4]VDD T VSS T DIN[5]DIN[6]DIN[7]DIN[8]DIN[9] DS99R105

48 PIN WQFN

48 PIN TQFP

(1UI) Sampling Window Ideal Data Bit End Ideal Data Bit Beginning RxIN_TOL -L tBIT ( ) RxIN_TOL -R DS99R105,DS99R106 SNLS242D –MARCH 2007–REVISED APRIL 2013 www.ti.com RxIN_TOL_L istheidealnoisemarginon theleftofthefigure,withrespecttoideal. RxIN_TOL_R istheidealnoisemarginon therightofthefigure,withrespecttoideal. TxOUT_E_O isaffectedby pre-emphasisvalue. Figure17. ReceiverInputTolerance(RxIN_TOL) and Sampling Window DS99R105 Pin Diagram Top View Figure18. Serializer-DS99R105 See Package Numbers NJU0048D and PFB0048A

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DS99R105,DS99R106 www.ti.com SNLS242D –MARCH 2007–REVISED APRIL 2013 DS99R105 SerializerPin Descriptions Pin Pin Name I/O DescriptionNo. LVCMOS PARALLEL INTERFACE PINS 4-1, DIN[23:0] LVCMOS_I TransmitterParallelInterfaceData InputsPins.TieLOW ifunused,do notfloat. 48-44, 41-32, 29-25 10 TCLK LVCMOS_I TransmitterParallelInterfaceClockInputPin.Strobeedge setby TRFB configurationpin. CONTROL AND CONFIGURATION PINS

9 TPWDNB LVCMOS_I TransmitterPower Down Bar

TPWDNB = H; TransmitterisEnabledand ON TPWDNB = L;Transmitterisinpower down mode (Sleep),LVDS DriverDOUT (+/-)Outputsare inTRI-STATE stand-bymode, PLL isshutdowntominimizepower consumption.

18 DEN LVCMOS_I TransmitterData Enable

DEN = H; LVDS DriverOutputsareEnabled(ON). DEN = L;LVDS DriverOutputsareDisabled(OFF),TransmitterLVDS DriverDOUT (+/-)Outputs areinTRI-STATE, PLL stilloperationaland lockedtoTCLK. 23 PRE LVCMOS_I PRE -emphasisselectpin. PRE = L;Pre-emphasisisenabled PRE = H; Pre-emphasisisdisabled

11 TRFB LVCMOS_I TransmitterClockEdge SelectPin

TRFB = H; ParallelInterfaceData isstrobedon theRisingClockEdge TRFB = L;ParallelInterfaceData isstrobedon theFallingClockEdge

12 VODSEL LVCMOS_I VOD LevelSelect

VODSEL = L;LVDS DriverOutputis±400 mV (RL = 100Ω) VODSEL = H; LVDS DriverOutputis±750 mV (RL = 100Ω) Fornormalapplications,setthispinLOW. Forlongcableapplicationswhere a largerVOD is required,setthispinHIGH. 5 DCAOFF LVCMOS_I RESERVED – ThispinMUST be tiedLOW. 8 DCBOFF LVCMOS_I RESERVED – ThispinMUST be tiedLOW. 13 RESRVD LVCMOS_I RESERVED – ThispinMUST be tiedLOW. LVDS SERIAL INTERFACE PINS 20 DOUT+ LVDS_O TransmitterLVDS True(+)Output.Thisoutputisintendedtobe loadedwitha 100 ohm loadto theDOUT+ pin.The interconnectshouldbe AC Coupledtothispinwitha 100 nF capacitor.

19 DOUT − LVDS_O TransmitterLVDS Inverted(-)OutputThisoutputisintendedtobe loadedwitha 100 ohm loadto

theDOUT- pin.The interconnectshouldbe AC Coupledtothispinwitha 100 nF capacitor. POWER /GROUND PINS

22 VDDDR VDD AnalogVoltageSupply,LVDS OutputPower

21 VSSDR GND AnalogGround,LVDS OutputGround

16 VDDPT0 VDD AnalogVoltagesupply,VCO Power

17 VSSPT0 GND AnalogGround,VCO Ground

14 VDDPT1 VDD AnalogVoltagesupply,PLL Power

15 VSSPT1 GND AnalogGround,PLL Ground

30 VDDT VDD DigitalVoltagesupply,Tx SerializerPower

31 VSST GND DigitalGround,Tx SerializerGround

7 VDDL VDD DigitalVoltagesupply,Tx LogicPower

6 VSSL GND DigitalGround,Tx LogicGround

42 VDDIT VDD DigitalVoltagesupply,Tx InputPower

43 VSSIT GND DigitalGround,Tx InputGround

24 VSS GND ESD Ground

ROUT[15] ROUT[14] ROUT[13] ROUT[12] LOCK RCLK VSSOR2 VDDOR2 ROUT[11] ROUT[10] ROUT[9] ROUT[8] ROUT[16] ROUT[17] ROUT[18] ROUT[19] VSS OR3 VDD OR3 ROUT[20] ROUT[21] ROUT[22] ROUT[23] RESRVD RPWDNB 252627282930313233343536 ROUT[7]ROUT[6]ROUT[5]ROUT[4]VSS OR1 VDD OR1 ROUT[3]ROUT[2]ROUT[1]ROUT[0]VSS VDD PTO GROUP 3 PTO GROUP 1 PTO GROUP 2 DS99R106 DS99R105,DS99R106 SNLS242D –MARCH 2007–REVISED APRIL 2013 www.ti.com DS99R106 Pin Diagram Top View Figure19. Deserializer-DS99R106 See Package Numbers NJU0048D and PFB0048A DS99R106 DeserializerPin Descriptions Pin Pin Name I/O DescriptionNo. LVCMOS PARALLEL INTERFACE PINS 25-28, ROUT[7:0] LVCMOS_O ReceiverParallelInterfaceData Outputs– Group 1 31-34 13-16, ROUT[15:8] LVCMOS_O ReceiverParallelInterfaceData Outputs– Group 2 21-24 3-6,9- ROUT[23:16] LVCMOS_O ReceiverParallelInterfaceData Outputs– Group 3 18 RCLK LVCMOS_O ParallelInterfaceClockOutputPin.Strobeedge setby RRFB configurationpin. CONTROL AND CONFIGURATION PINS

43 RRFB LVCMOS_I ReceiverClockEdge SelectPin

RRFB = H; ROUT LVCMOS Outputsstrobedon theRisingClockEdge. RRFB = L;ROUT LVCMOS Outputsstrobedon theFallingClockEdge.

48 REN LVCMOS_I ReceiverData Enable

REN = H; ROUT[23-0]and RCLK areEnabled(ON). REN = L;ROUT[23-0]and RCLK areDisabled(OFF),ReceiverROUT[23-0]and RCLK Outputs areinTRI-STATE, PLL stilloperationaland lockedtoTCLK.

1 RPWDNB LVCMOS_I ReceiverData Enable

REN = H; ROUT[23-0]and RCLK areEnabled(ON). REN = L;ROUT[23-0]and RCLK areDisabled(OFF),ReceiverROUT[23-0]and RCLK Outputs areinTRI-STATE, PLL stilloperationaland lockedtoTCLK.

14 SubmitDocumentationFeedback Copyright© 2007–2013,Texas InstrumentsIncorporated

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DS99R105,DS99R106 www.ti.com SNLS242D –MARCH 2007–REVISED APRIL 2013 DS99R106 DeserializerPin Descriptions(continued) Pin Pin Name I/O DescriptionNo.

17 LOCK LVCMOS_O LOCK indicatesthestatusofthereceiverPLL

LOCK = H; receiverPLL islocked LOCK = L;receiverPLL isunlocked,ROUT[23-0]and RCLK areTRI-STATED 2 RESRVD LVCMOS_I RESERVED – ThispinMUST be tiedLOW. LVDS SERIAL INTERFACE PINS

41 RIN+ LVDS_I ReceiverLVDS True(+)InputThisinputisintendedtobe terminatedwitha 100 ohm loadtothe

RIN+ pin.The interconnectshouldbe AC Coupledtothispinwitha 100 nF capacitor.

42 RIN− LVDS_I ReceiverLVDS Inverted(−)InputThisinputisintendedtobe terminatedwitha 100 ohm loadto

theRIN-pin.The interconnectshouldbe AC Coupledtothispinwitha 100 nF capacitor. POWER /GROUND PINS

39 VDDIR VDD AnalogLVDS Voltagesupply,Power

40 VSSIR GND AnalogLVDS G round

47 VDDPR0 VDD AnalogVoltagesupply,PLL Power

46 VSSPR0 GND AnalogGround,PLL Ground

45 VDDPR1 VDD AnalogVoltagesupply,PLL VCO Power

44 VSSPR1 GND AnalogGround,PLL VCO Ground

37 VDDR1 VDD DigitalVoltagesupply,LogicPower

38 VSSR1 GND DigitalGround,LogicGround

36 VDDR0 VDD DigitalVoltagesupply,LogicPower

35 VSSR0 GND DigitalGround,LogicGround

30 VDDOR1 VDD DigitalVoltagesupply,LVCMOS OutputPower

29 VSSOR1 GND DigitalGround,LVCMOS OutputGround

20 VDDOR2 VDD DigitalVoltagesupply,LVCMOS OutputPower

19 VSSOR2 GND DigitalGround,LVCMOS OutputGround

7 VDDOR3 VDD DigitalVoltagesupply,LVCMOS OutputPower

8 VSSOR3 GND DigitalGround,LVCMOS OutputGround

DS99R105,DS99R106 SNLS242D –MARCH 2007–REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION The DS99R105 Serializerand DS99R106 Deserializerchipsetisan easy-to-usetransmitterand receiverpairthat sends 24-bitsofparallelLVCMOS dataovera singleserialLVDS linkfrom 72 Mbps to960 Mbps throughput. The DS99R105 transformsa 24-bitwideparallelLVCMOS dataintoa singlehighspeed LVDS serialdatastream withembedded clock.The DS99R106 receivestheLVDS serialdatastreamand convertsitback intoa 24-bit wide paralleldata and recoveredclock.The 24-bitSerializer/Deserializerchipsetisdesignedto transmitdata overshieldedtwistedpair(STP)atclockspeeds from3 MHz to40 MHz. The Deserializercan attainlockto a data stream withoutthe use of a separatereferenceclocksource.The DeserializersynchronizestotheSerializerregardlessofdatapattern,deliveringtrueautomatic“plugand lock” performance.The Deserializerrecoversthe clockand data by extractingthe embedded clockinformationand validatingdataintegrityfromtheincomingdatastreamand thendeserializesthedata.The Deserializermonitors the incomingclockinformation,determineslockstatus,and assertsthe LOCK outputhighwhen lockoccurs. Each has a power down controltoenableefficientoperationinvariousapplications. INITIALIZATIONAND LOCKING MECHANISM InitializationoftheDS99R105 and DS99R106 must be establishedbeforeeach devicesends or receivesdata. InitializationreferstosynchronizingtheSerializer’s and Deserializer’s PLL’s together.AftertheSerializerslocks totheinputclocksource,theDeserializersynchronizestotheSerializersas thesecond and finalinitialization step. 1. When VDD isappliedtobothSerializerand/orDeserializer,therespectiveoutputsareheldinTRI-STATE and internalcircuitryisdisabledby on-chippower-on circuitry.When VDD reachesVDD OK (2.2V)the PLL in Serializerbeginslockingtoa clockinput.For theSerializer,thelocalclockisthetransmitclock,TCLK. The Serializeroutputsare held in TRI-STATE whilethe PLL locksto the TCLK. Afterlockingto TCLK, the Serializerblockisnow readytosend datapatterns.The DeserializeroutputwillremaininTRI-STATE while itsPLL lockstotheembedded clockinformationinserialdatastream.Also,theDeserializerLOCK outputwill remainlowuntilitsPLL lockstoincomingdataand sync-patternon theRIN± pins. 2. The DeserializerPLL acquireslocktoa datastreamwithoutrequiringtheSerializertosend specialpatterns. The Serializerthatis generatingthe stream to the Deserializerwillautomaticallysend random (non- repetitive)datapatternsduringthisstepoftheInitializationState.The Deserializerwilllockontoembedded clockwithinthespecifiedamount oftime.An embedded clockand datarecovery(CDR) circuitlockstothe incomingbitstreamtorecoverthehigh-speedreceivebitclockand re-timeincomingdata.The CDR circuit expectsa coded inputbitstream.In orderforthe Deserializerto lockto a random data stream from the Serializer,itperformsa seriesofoperationstoidentifytherisingclockedge and validatesdataintegrity,then lockstoit.Because thislockingprocedureisindependenton thedatapattern,totalrandom lockingduration may vary.At thepointwhen theDeserializer’s CDR lockstotheembedded clock,theLOCK pingoes high and validRCLK/data appears on the outputs.Note thatthe LOCK signalis synchronousto validdata appearingon the outputs.The Deserializer’s LOCK pin isa convenientway to ensure data integrityis achievedon receiverside. DATA TRANSFER Afterlockisestablished,the SerializerinputsDIN0–DIN23 are used to inputdata to the Serializer.Data is clockedintotheSerializerby theTCLK input.The edge ofTCLK used tostrobethedataisselectableviathe TRFB pin.TRFB highselectstherisingedge forclockingdataand low selectsthefallingedge.The Serializer outputs(DOUT ±)areintendedtodrivepoint-to-pointconnectionsorlimitedmulti-pointapplications. CLK1, CLK0, DCA, DCB arefouroverheadbitstransmittedalongthesingleLVDS serialdatastream.The CLK1 bitisalwayshighand theCLK0 bitisalwayslow.The CLK1 and CLK0 bitsfunctionas theembedded clockbits intheserialstream.DCB functionsas theDC Balancecontrolbit.Itdoes notrequireany pre-codingofdataon transmitside.The DC Balancebitisused tominimizetheshortand long-termDC biason thesignallines.This bitoperatesby selectivelysendingthedataeitherunmodifiedor inverted.The DCA bitisused tovalidatedata integrityinthe embedded data stream.Both DCA and DCB codingschemes are integratedand automatically performedwithinSerializerand Deserializer. The chipsetsupportsclockfrequencyrangesof3 MHz to40 MHz. Everyclockcycle,24 databitsaresentalong with4 additionaloverheadcontrolbits.Thus thelinerateis1.12Gbps maximum (84Mbps minimum).The linkis extremelyefficientat86% (24/28).Twenty five(24data+ 1 clock)plusassociatedgroundsignalsarereducedto only1 singleLVDS pairprovidinga compressionratioofbetterthen25 to1.

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DS99R105,DS99R106 www.ti.com SNLS242D –MARCH 2007–REVISED APRIL 2013 Serializeddataand clock/controlbits(24+4bits)aretransmittedfromtheserialdataoutput(DOUT ±)at28 times theTCLK frequency.For example,ifTCLK is,theserialrateis40 x 28 = 1.12Giga bitspersecond.Sinceonly 24 bitsarefrominputdata,theserial“payload”rateis24 timestheTCLK frequency.For instance,ifTCLK = 40 MHz, thepayloaddatarateis40 x 24 = 960 Mbps. TCLK isprovidedby thedatasourceand must be inthe range of 3 MHz to 40 MHz nominal.The Serializeroutputs(DOUT ±) can drivea point-to-pointconnectionas shown inFigure20.The outputstransmitdatawhen theenablepin(DEN) ishighand TPWDNB ishigh.The DEN pinmay be used toTRI-STATE theoutputswhen drivenlow. When the Deserializerchannel attainslockto the inputfrom a Serializer,itdrivesitsLOCK pin high and synchronouslydeliversvaliddataand recoveredclockon theoutput.The Deserializerlocksontotheembedded clock,uses ittogeneratemultipleinternaldatastrobes,and thendrivestherecoveredclocktotheRCLK pin. The recoveredclock(RCLK outputpin)issynchronoustothedataon theROUT[23:0]pins.WhileLOCK ishigh, dataon ROUT[23:0]isvalid.Otherwise,ROUT[23:0]isinvalid.The polarityoftheRCLK edge iscontrolledby the RRFB input.ROUT(0-23),LOCK and RCLK outputswilleach drivea maximum of8 pF loadwitha 40 MHz clock. REN controlsTRI-STATE forROUTn and theRCLK pinon theDeserializer. RESYNCHRONIZATION Ifthe Deserializerloseslock,itwillautomaticallytryto re-establishlock.For example,ifthe embedded clock edge isnotdetectedone timeinsuccession,thePLL loseslockand theLOCK pinisdrivenlow.The Deserializer thenenterstheoperatingmode where ittriestolocktoa random datastream.Itlooksfortheembedded clock edge,identifiesitand thenproceedsthroughthelockingprocess. The logicstateoftheLOCK signalindicateswhetherthedataon ROUT isvalid;when itishigh,thedataisvalid. The systemmust monitortheLOCK pintodeterminewhetherdataon theROUT isvalid. POWERDOWN The Powerdown stateisa low power sleepmode thattheSerializerand Deserializermay use toreducepower when no dataisbeingtransferred.The TPWDNB and RPWDNB are used toseteach deviceintopower down mode, whichreducessupplycurrenttotheµA range.The Serializerenterspowerdown when theTPWDNB pinis drivenlow.Inpowerdown,thePLL stopsand theoutputsgo intoTRI-STATE, disablingloadcurrentand reducing supply.To exitPowerdown, TPWDNB must be drivenhigh.When theSerializerexitsPowerdown, itsPLL must locktoTCLK beforeitisreadyfortheInitializationstate.The system must thenallowtimeforInitializationbefore datatransfercan begin.The Deserializerenterspowerdown mode when RPWDNB isdrivenlow.Inpowerdown mode, thePLL stopsand theoutputsenterTRI-STATE. To bringtheDeserializerblockoutofthepowerdown state,thesystemdrivesRPWDNB high. Both theSerializerand Deserializermust reinitializeand relockbeforedatacan be transferred.The Deserializer willinitializeand assertLOCK highwhen itislockedtotheencoded clock. TRI-STATE For theSerializer,TRI-STATE isenteredwhen theDEN orTPWDNB pinisdrivenlow.ThiswillTRI-STATE both driveroutputpins(DOUT+ and DOUT −).When DEN isdrivenhigh,theserializerwillreturntothepreviousstate as longas allothercontrolpinsremainstatic(TPWDNB, TRFB). When you drivetheREN or RPWDNB pinlow,theDeserializerentersTRI-STATE. Consequently,thereceiver outputpins(ROUT0 –ROUT23) and RCLK willenterTRI-STATE. The LOCK outputremainsactive,reflectingthe stateofthePLL. The Deserializerinputpinsarehighimpedance duringreceiverpowerdown (RPWDNB low)and power-off(VDD = 0V). PRE-EMPHASIS The DS99R105 featuresa Pre-Emphasismode used tocompensate forlongorlossytransmissionmedia.Cable driveisenhanced witha user selectablePre-Emphasisfeaturethatprovidesadditionaloutputcurrentduring transitionsto counteractcable loadingeffects.The transmissiondistancewillbe limitedby the loss characteristicsand qualityofthemedia.Pre-Emphasisadds extracurrentduringLVDS logictransitiontoreduce the cable loadingeffectsand increasedrivingdistance.In addition,Pre-Emphasis helps providefaster transitions,increasedeye openings,and improvedsignalintegrity.The abilityoftheDS99R105 touse thePre- Emphasis featurewillextendthetransmissiondistanceinmost cases. Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS99R105 DS99R106

DS99R105,DS99R106 SNLS242D –MARCH 2007–REVISED APRIL 2013 www.ti.com AC-COUPLING AND TERMINATION The DS99R105 and DS99R106 supports AC-coupled interconnectsthrough integratedDC balanced encoding/decodingscheme. To use AC coupled connectionbetween the Serializerand Deserializer,insert externalAC couplingcapacitorsinseriesintheLVDS signalpathas illustratedinFigure20.The Deserializer inputstageisdesignedforAC-couplingby providinga built-inAC biasnetworkwhich setstheinternalVCM to +1.2V.WithAC signalcoupling,capacitorsprovidetheac-couplingpathtothesignalinput. For the high-speedLVDS transmissions,the smallestavailablepackage shouldbe used forthe AC coupling capacitor.Thiswillhelpminimizedegradationof signalqualitydue to package parasitics.The most common used capacitorvaluefortheinterfaceis100 nF (0.1uF)capacitor. A terminationresistoracross DOUT ± is also requiredforproperoperationto be obtained.The termination resistorshouldbe equaltothedifferentialimpedance ofthemedia beingdriven.Thisshouldbe intherangeof 90 to132 Ohms. 100 Ohms isa typicalvaluecommon used withstandard100 Ohm transmissionmedia.This resistorisrequiredforcontrolofreflectionsand alsotocompletethecurrentloop.Itshouldbe placedas closeto theSerializerDOUT ± outputstominimizethestublengthfromthepins.To match withthedeferentialimpedance on thetransmissionline,theLVDS I/Oareterminatedwith100 ohm resistorson SerializerDOUT ± outputspins. PROGRESSIVE TURN –ON (PTO) DeserializerROUT[23:0] outputsare grouped intothreegroupsofeight,witheach group switchingabout0.5UI apartinphase toreduceEMI,simultaneousswitchingnoise,and systemgroundbounce. ApplicationsInformation USING THE DS99R105 AND DS99R106 The DS99R105/DS99R106 Serializer/Deserializer(SERDES) pairsends 24 bitsofparallelLVCMOS dataovera serialLVDS linkup to960 Mbps. Serializationoftheinputdataisaccomplishedusingan on-boardPLL atthe Serializerwhich embeds clockwiththe data.The Deserializerextractsthe clock/controlinformationfrom the incomingdata stream and deserializesthe data.The Deserializermonitorsthe incomingclocklinformationto determinelockstatusand willindicatelockby assertingtheLOCK outputhigh. POWER CONSIDERATIONS An allCMOS designoftheSerializerand Deserializermakes them inherentlylow power devices.Additionally, theconstantcurrentsourcenatureoftheLVDS outputsminimizetheslopeofthespeed vs.IDD curveofCMOS designs. NOISE MARGIN The Deserializernoisemarginistheamount ofinputjitter(phasenoise)thattheDeserializercan tolerateand still reliablyrecoverdata.Variousenvironmentaland systematicfactorsinclude:

Serializer:TCLK jitter,VDD noise(noisebandwidthand out-of-bandnoise)
Media:ISI,VCM noise
Deserializer:VDD noise Fora graphicalrepresentationofnoisemargin,pleasesee Figure17. TRANSMISSION MEDIA The Serializerand Deserializercan be used in point-to-pointconfiguration,througha PCB trace,or through twistedpaircable.Ina point-to-pointconfiguration,thetransmissionmedia needs be terminatedatbothends of thetransmitterand receiverpair.InterconnectforLVDS typicallyhas a differentialimpedance of100 Ohms. Use cablesand connectorsthathave matched differentialimpedance tominimizeimpedance discontinuities.Inmost applicationsthatinvolvecables,thetransmissiondistancewillbe determinedon dataratesinvolved,acceptable biterrorrateand transmissionmedium.

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DS99R105,DS99R106 www.ti.com SNLS242D –MARCH 2007–REVISED APRIL 2013 LIVE LINK INSERTION The Serializerand Deserializerdevicessupportlivepluggableapplications.The “Hot Inserted” operationon the serialinterfacedoes not disruptcommunicationdata on the activedata lines.The automaticreceiverlockto random data“plug& go” liveinsertioncapabilityallowstheDS99R106 toattainlocktotheactivedatastream duringa liveinsertionevent. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuitboardlayoutand stack-upfortheLVDS SERDES devicesshouldbe designedtoprovidelow-noisepower feed to the device.Good layoutpracticewillalsoseparatehighfrequencyor high-levelinputsand outputsto minimizeunwanted straynoisepickup,feedbackand interference.Power system performancemay be greatly improvedby usingthindielectrics(2to4 mils)forpower /groundsandwiches.Thisarrangementprovidesplane capacitanceforthePCB power system withlow-inductanceparasitics,which has provenespeciallyeffectiveat highfrequencies,and makes thevalueand placementofexternalbypasscapacitorslesscritical.Externalbypass capacitorsshouldincludebothRF ceramicand tantalumelectrolytictypes.RF capacitorsmay use valuesinthe tantalumcapacitorsshouldbe atleast5X thepower supplyvoltagebeingused. Surfacemount capacitorsarerecommended due totheirsmallerparasitics.When usingmultiplecapacitorsper supplypin,locatethesmallervalueclosertothepin.A largebulkcapacitorisrecommend atthepointofpower entry.This is typicallyin the 50uF to 100uF range and willsmooth low frequencyswitchingnoise.Itis recommended toconnectpower and groundpinsdirectlytothepower and groundplaneswithbypass capacitors connectedtotheplanewithviaon bothends ofthecapacitor.Connectingpower or ground pinstoan external bypasscapacitorwillincreasetheinductanceofthepath. A smallbody sizeX7R chipcapacitor,such as 0603,isrecommended forexternalbypass.Itssmallbody size reducesthe parasiticinductanceof the capacitor.The user must pay attentionto the resonancefrequencyof these externalbypass capacitors,usuallyin the range of 20-30 MHz range.To provideeffectivebypassing, multiplecapacitorsare oftenused to achievelow impedance between the supplyrailsover the frequencyof interest.At highfrequency,itisalsoa common practiceto use two viasfrom power and ground pinsto the planes,reducingtheimpedance athighfrequency. Some devicesprovideseparatepower and groundpinsfordifferentportionsofthecircuit.Thisisdone toisolate switchingnoiseeffectsbetween differentsectionsof the circuit.Separateplaneson the PCB are typicallynot required.PinDescriptiontablestypicallyprovideguidanceon whichcircuitblocksareconnectedtowhichpower pinpairs.Insome cases,an externalfiltermany be used toprovidecleanpower tosensitivecircuitssuch as PLLs. Use atleasta fourlayerboardwitha power and groundplane.LocateLVCMOS (LVTTL)signalsaway fromthe LVDS linestopreventcouplingfrom theLVCMOS linestotheLVDS lines.Closely-coupleddifferentiallinesof 100 Ohms are typicallyrecommended forLVDS interconnect.The closelycoupledlineshelp to ensure that couplednoisewillappear as common-mode and thusisrejectedby thereceivers.The tightlycoupledlineswill alsoradiateless. TerminationoftheLVDS interconnectisrequired.Forpoint-to-pointapplications,terminationshouldbe locatedat both ends of the devices.Nominal valueis100 Ohms to match the line’s differentialimpedance.Place the resistoras closetothetransmitterDOUT ± outputsand receiverRIN± inputsas possibletominimizetheresulting stubbetween theterminationresistorand device. LVDS INTERCONNECT GUIDELINES See AN-1108 (SNLA008 )and AN-905 (SNLA035 )forfulldetails.

Use 100Ω coupleddifferentialpairs
Use theS/2S/3Sruleinspacings – S = space between thepair – 2S = space between pairs – 3S = space toLVCMOS/LVTTL signal
Minimizethenumber ofVIA
Use differentialconnectorswhen operatingabove 500Mbps linespeed

Notes: TPWDNB = System GPO DEN = High (ON) TRFB = High (Rising edge) VODSEL = Low (400mV) PRE = Low (OFF) RESRVD = Low DCAOFF = Low DCBOFF = Low DS99R105 (SER) C1 C4 C2 C5 C3 C6 C1 to C3 = 0.01 PF C4 to C6 = 0.1 PF C7, C8 = 100 nF; 50WVDC, NPO or X7R R1 = 100: LVCMOS Parallel Interface Serial LVDS Interface VSS 3.3V TPWDNB DEN TRFB DCAOFF VODSEL PRE DCBOFF 3.3V GPOs if used, or tie High (ON) RESRVD 100: 100 nF 100 nF 100: 100 nF 100 nF DOUT- DOUT+ RIN- RIN+ DS99R105,DS99R106 SNLS242D –MARCH 2007–REVISED APRIL 2013 www.ti.com

Minimizeskew withinthepair
Terminateas closetotheTX outputsand RX inputsas possible Additionalgeneralguidancecan be foundintheLVDS Owner ’s Manual - availableinPDF formatfrom theTI web siteat:http://www.ti.com/ww/en/analog/interface/lvds.shtml Figure20. AC Coupled Application Figure21. DS99R105 TypicalApplicationConnection

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Notes: RPWDNB = System GPO REN = High (ON) RRFB = High (Rising edge) RESRVD = Low 3.3V DS99R106 (DES) C3 C7 C4 C8 C10 C5 C1 VDDIR VDDOR1 VSSPR0 VSSPR1 VSSR0 VSSR1 VSSIR VSSOR1 VSSOR2 VSSOR3 LOCK C2C6 C1 to C4 = 0.01 PF C5 to C8 = 0.1 PF C9, C10 = 100 nF; 50WVDC, NPO or X7R Serial LVDS Interface LVCMOS Parallel Interface GPO if used, or tie High (ON) 3.3V 3.3V 100: DS99R105,DS99R106 www.ti.com SNLS242D –MARCH 2007–REVISED APRIL 2013 Figure22. DS99R106 TypicalApplicationConnection TRUTH TABLES DS99R105 SerializerTruthTable TPWDNB DEN Tx PLL Status LVDS Outputs (Pin9) (Pin18) (Internal) (Pins19 and 20) L X X HiZ H L X HiZ H H Not Locked HiZ H H Locked SerializedData withEmbedded Clock DS99R106 DeserializerTruthTable ROUTn and RCLKRPWDNB REN Rx PLL Status LOCK(See DS99R105 Pin(Pin1) (Pin48) (Internal) (Pin17)Diagram) L X X HiZ HiZ H L X HiZ L = PLL Unocked; H = PLL Locked H H Not Locked HiZ L H H Locked Data and RCLK Active H Copyright© 2007–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:DS99R105 DS99R106

DS99R105,DS99R106 SNLS242D –MARCH 2007–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionC (April2013)toRevisionD Page

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www.ti.com 16-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples DS99R105SQ/NOPB ACTIVE WQFN NJU 48 250 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 DS99R105 DS99R105SQX/NOPB ACTIVE WQFN NJU 48 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 DS99R105 DS99R105VS/NOPB ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 DS99R105 VS DS99R105VSX/NOPB ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 DS99R105 VS DS99R106SQ/NOPB ACTIVE WQFN NJU 48 250 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 DS99R106 DS99R106SQX/NOPB ACTIVE WQFN NJU 48 2500 Green (RoHS & no Sb/Br) CU SN Level-2-260C-1 YEAR 0 to 70 DS99R106 DS99R106VS/NOPB ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 DS99R106 VS DS99R106VSX/NOPB ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 DS99R106 VS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

www.ti.com 16-Apr-2013 Addendum-Page 2 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS99R105SQ/NOPB WQFN NJU 48 250 213.0 191.0 55.0 DS99R105SQX/NOPB WQFN NJU 48 2500 367.0 367.0 38.0 DS99R105VSX/NOPB TQFP PFB 48 1000 367.0 367.0 38.0 DS99R106SQ/NOPB WQFN NJU 48 250 213.0 191.0 55.0 DS99R106SQX/NOPB WQFN NJU 48 2500 367.0 367.0 38.0 DS99R106VSX/NOPB TQFP PFB 48 1000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 2

www.ti.com SQA48D (Rev A)

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 4073176/B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,17 0,27 SQ 7,20 6,80 5,50 TYP SQ8,80 9,20 1,05 0,95 1,20 MAX 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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