DS92LV1224TMSA

DS92LV1224_15 TI1 | Alldatasheet

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(30 MHz to 66 MHz) TCLK_R/F D IN

10 D O+

(30 MHz to 66 MHz) RCLK_R/F DS92LV1224 www.ti.com SNLS189A –APRIL 2005–REVISED APRIL 2013 DS92LV122430-66MHz10BitBusLVDSDeserializer Check forSamples: DS92LV1224 1FEATURES DESCRIPTION The DS92LV1224 isa 300 to 660 Mb/s deserializer 2• 30–66 MHz Single1:10Deserializerwith forhigh-speedunidirectionalserialdatatransmission300–660 Mb/s Throughput over FR-4 printedcircuitboard backplanes and• Robust Bus LVDS SerialData Transmission balanced copper cables.Itreceivesthe Bus LVDS withEmbedded Clock forExceptionalNoise serialdatastreamfroma compatible10–bitserializer, Immunity and Low EMI transformsitback intoa 10-bitwide paralleldatabus and recoversparallelclock.This singleserialdata• Clock Recovery from PLL Lock toRandom streamsimplifiesPCB designand reducesPCB costData Patterns by narrowingdatapathsthatinturnreducePCB size• Ensured TransitionEvery Data TransferCycle and number of layers.The singleserialdata stream

• Low Power Consumption < 300 mW (typ) alsoreduces cablesize,the number of connectors, at66 MHz and eliminatesclock-to-dataand data-to-dataskew.
• SingleDifferentialPairEliminatesMulti- The DS92LV1224 works wellwithBus LVDS 10–bit Channel Skew serializerswithinitsspecifiedfrequencyoperating range.Itfeatureslow power consumption,and high• Flow-Through PinoutforEasy PCB Layout impedance outputsinpower down mode.• SynchronizationMode and LOCK Indicator The DS92LV1224 was designedwiththeflow-through• Programmable Edge Triggeron Clock pinoutand is availablein a space saving28–lead• High Impedance on ReceiverInputswhen SSOP package.Power isOff
• Small 28-Lead SSOP Package Block Diagrams Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2005–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS189A –APRIL 2005–REVISED APRIL 2013 www.ti.com FunctionalDescription The DS92LV1224 isa 10-bitDeserializerdevicewhichtogetherwitha compatibleserializer(i.e.DS92LV1023E) forms a chipsetdesignedto transmitdata over FR-4 printedcircuitboard backplanesand balancedcopper cablesatclockspeeds from30 MHz to66 MHz. The chipsethas threeactivestatesof operation:Initialization,Data Transfer,and Resynchronization;and two passivestates:Powerdown and TRI-STATE. The followingsectionsdescribeeach operationand passivestate. Initialization Initializationofbothdevicesmust occurbeforedatatransmissionbegins.Initializationreferstosynchronizationof the Serializerand DeserializerPLL's to localclocks,which may be the same or separate.Afterwards, synchronizationoftheDeserializertoSerializeroccurs. Step 1:When you applyVCC tobothSerializerand/orDeserializer,therespectiveoutputsenterTRI-STATE, and on-chippower-oncircuitrydisablesinternalcircuitry.When VCC reachesVCC OK (2.5V)thePLL ineach device beginslockingtoa localclock.For theSerializer,thelocalclockisthetransmitclock(TCLK) providedby the sourceASIC orotherdevice.FortheDeserializer,you must applya localclocktotheREFCLK pin. The Serializeroutputsremain in TRI-STATE whilethe PLL locksto the TCLK. Afterlockingto TCLK, the Serializerisnow readytosend dataorSYNC patterns,dependingon thelevelsoftheSYNC1 and SYNC2 inputs or a datastream.The SYNC patternsentby theSerializerconsistsofsixones and sixzerosswitchingatthe inputclockrate. Note thatthe DeserializerLOCK outputwillremain highwhileitsPLL locksto the incomingdata or to SYNC patternson theinput. Step 2:The DeserializerPLL must synchronizetotheSerializertocompleteinitialization.The Deserializerwill locktonon-repetitivedatapatterns.However,thetransmissionofSYNC patternsenablestheDeserializertolock totheSerializersignalwithina specifiedtime. The user'sapplicationdeterminescontrolof the SYNC1 and SYNC 2 pins.One recommendationisa direct feedbackloopfrom the LOCK pin.Under allcircumstances,the SerializerstopssendingSYNC patternsafter bothSYNC inputsreturnlow. When theDeserializerdetectsedge transitionsattheBus LVDS input,itwillattempttolocktotheembedded clockinformation.When theDeserializerlockstotheBus LVDS clock,theLOCK outputwillgo low.When LOCK islow,theDeserializeroutputsrepresentincomingBus LVDS data. Data Transfer Afterinitialization,theSerializerwillacceptdatafrom inputsDIN0–DIN9. The Serializeruses theTCLK inputto latchincomingData. The TCLK_R/ F pin selectswhich edge the Serializeruses to strobeincomingdata. TCLK_R/ F highselectstherisingedge forclockingdataand low selectsthefallingedge.IfeitheroftheSYNC inputsishighfor5*TCLK cycles,thedataatDIN0-DIN9 isignoredregardlessofclockedge.

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www.ti.com SNLS189A –APRIL 2005–REVISED APRIL 2013 Afterdeterminingwhich clockedge touse,a startand stopbit,appended internally,frame thedatabitsinthe register.The startbitisalways high and the stop bitisalways low.The startand stop bitsfunctionas the embedded clockbitsintheserialstream. The Serializertransmitsserializeddataand clockbits(10+2 bits)from theserialdataoutput(DO ±) at12 times theTCLK frequency.For example,ifTCLK is66 MHz, theserialrateis66 × 12 = 792 Mega-bits-per-second. Sinceonly10 bitsarefrominputdata,theserial“payload”rateis10 timestheTCLK frequency.For instance,if TCLK = 66 MHz, thepayloaddatarateis66 × 10 = 660 Mbps. The datasourceprovidesTCLK and must be in therangeof30 MHz to66 MHz nominal. The Serializeroutputs(DO ±) can drivea point-to-pointconnectionor in limitedmulti-pointor multi-drop backplanes.The outputstransmitdata when the enablepin(DEN) ishigh,PWRDN = high,and SYNC1 and SYNC2 arelow.When DEN isdrivenlow,theSerializeroutputpinswillenterTRI-STATE. When the Deserializersynchronizesto the Serializer,the LOCK pin is low.The Deserializerlocksto the embedded clockand uses ittorecovertheserializeddata.ROUT dataisvalidwhen LOCK islow.Otherwise ROUT0 –ROUT9 isinvalid. The ROUT0-ROUT9 pinsuse theRCLK pinas thereferencetodata.The polarityoftheRCLK edge iscontrolled by theRCLK_R/ F input.See Figure6. ROUT(0-9),LOCK and RCLK outputswilldrivea maximum ofthreeCMOS inputgates(15 pF load)witha 66 MHz clock. Resynchronization When theDeserializerPLL lockstotheembedded clockedge,theDeserializerLOCK pinassertsa low.Ifthe Deserializerloseslock,theLOCK pinoutputwillgo highand theoutputs(includingRCLK) willenterTRI-STATE. The user'ssystem monitorstheLOCK pintodetecta lossofsynchronization.Upon detection,thesystem can arrangetopulsetheSerializerSYNC1 or SYNC2 pintoresynchronize.Multipleresynchronizationapproaches are possible.One recommendationistoprovidea feedbackloopusingtheLOCK pinitselftocontrolthesync requestoftheSerializer(SYNC1 or SYNC2). Dual SYNC pinsare providedformultiplecontrolina multi-drop application.Sending sync patternsforresynchronizationisdesirablewhen locktimeswithina specifictimeare critical.However,theDeserializercan locktorandom data,whichisdiscussedinthenextsection. Random Lock Initializationand Resynchronization The initializationand resynchronizationmethods describedintheirrespectivesectionsare the fastestways to establishthelinkbetween theSerializerand Deserializer.However, theDS92LV1224 can attainlocktoa data streamwithoutrequiringtheSerializertosend specialSYNC patterns.ThisallowstheDS92LV1224 tooperatein “open-loop” applications.Equallyimportantisthe Deserializer'sabilityto supporthot insertionintoa running backplane.Intheopen looporhotinsertioncase,we assume thedatastreamisessentiallyrandom.Therefore, because lock time variesdue to data stream characteristics,we cannot possiblypredictexact lock time. However, please see Table 1 forsome generalrandom locktimes under specificconditions.The primary constrainton the “random” locktimeisthe initialphase relationbetween the incomingdata and the REFCLK when theDeserializerpowers up.As describedinthenextparagraph,thedatacontainedinthedatastreamcan alsoaffectlocktime. Ifa specificpatternisrepetitive,theDeserializercouldenter“falselock”-falselyrecognizingthedatapatternas theclockingbits.We refertosuch a patternas a repetitivemulti-transition,RMT. Thisoccurswhen more than one Low-Hightransitiontakesplaceina clockcycleovermultiplecycles.Thisoccurswhen any bit,exceptDIN 9, isheld at a low stateand the adjacentbitisheld high,creatinga 0-1 transition.In the worstcase,the Deserializercouldbecome lockedtothedatapatternratherthantheclock.CircuitrywithintheDS92LV1224 can detectthatthe possibilityof “falselock” exists.The circuitryaccomplishesthisby detectingmore than one potentialpositionforclockingbits.Upon detection,the circuitrywillpreventthe LOCK outputfrom becoming activeuntilthe potential“falselock” patternchanges. The falselockdetectcircuitryexpectsthe data will eventuallychange,causingtheDeserializertoloselocktothedatapatternand thencontinuesearchingforclock bitsintheserialdatastream.GraphicalrepresentationsofRMT are shown inFigure1.PleasenotethatRMT onlyappliestobitsDIN0-DIN8. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS92LV1224

SNLS189A –APRIL 2005–REVISED APRIL 2013 www.ti.com Powerdown When no data transferoccurs,you can use the Powerdown state.The Serializerand Deserializeruse the Powerdown state,a low power sleepmode, toreducepower consumption.The DeserializerentersPowerdown when you drivePWRDN and REN low.The SerializerentersPowerdown when you drivePWRDN low.In Powerdown, thePLL stopsand theoutputsenterTRI-STATE, which disablesloadcurrentand reducessupply currenttothemilliampererange.To exitPowerdown, you must drivethePWRDN pinhigh. Beforevaliddataexchanges between theSerializerand Deserializer,you must reinitializeand resynchronizethe devicestoeach other.InitializationoftheSerializertakes510 TCLK cycles.The Deserializerwillinitializeand assertLOCK highuntillocktotheBus LVDS clockoccurs. TRI-STATE The SerializerentersTRI-STATE when theDEN pinisdrivenlow.Thisputsbothdriveroutputpins(DO+ and DO −)intoTRI-STATE. When you driveDEN high,theSerializerreturnstothepreviousstate,as longas allother controlpinsremainstatic(SYNC1, SYNC2, PWRDN, TCLK_R/ F). When you drivethe REN pinlow,the DeserializerentersTRI-STATE. Consequently,the receiveroutputpins (ROUT0 –ROUT9) and RCLK willenterTRI-STATE. The LOCK outputremainsactive,reflectingthestateofthe PLL. Table1.(1) Random Lock Times fortheDS92LV1224

40 MHz 66 MHz Units

Maximum 26 18 μs Mean 4.5 3.0 μs Minimum 0.77 0.43 μs Conditions: PRBS 215,VCC = 3.3V (1) Differenceinlocktimesaredue todifferentstartingpointsinthedatapatternwithmultipleparts.

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www.ti.com SNLS189A –APRIL 2005–REVISED APRIL 2013 Figure1. RMT PatternsSeen on theBus LVDS SerialOutput DIN0 Held Low-DIN1 Held High Createsan RMT Pattern DIN4 Held Low-DIN5 Held High Createsan RMT Pattern DIN8 Held Low-DIN9 Held High Createsan RMT Pattern Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS92LV1224

SNLS189A –APRIL 2005–REVISED APRIL 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) SupplyVoltage(VCC ) −0.3Vto+4V LVCMOS/LVTTL InputVoltage −0.3Vto(VCC +0.3V) LVCMOS/LVTTL OutputVoltage −0.3Vto(VCC +0.3V) Bus LVDS ReceiverInputVoltage −0.3Vto+3.9V JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature(Soldering,4 seconds) +260°C Maximum Package Power DissipationCapacityat25°C Package:28-LeadSSOP 1.27W Package Derating: 10.3mW/ °C above 28-LeadSSOP +25°C θja 97°C/W θjc 27°C/W HBM (1.5kΩ,100pF) >2kV ESD Rating MM > 250V (1) “AbsoluteMaximum Ratings”arethosevaluesbeyond whichthesafetyofthedevicecannotbe ensured.They arenotmeant toimply thatthedevicesshouldbe operatedattheselimits.The tableof“ElectricalCharacteristics”specifiesconditionsofdeviceoperation. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingConditions Min Nom Max Units SupplyVoltage(VCC ) 3.0 3.3 3.6 V OperatingFreeAir Temperature(TA) −40 +25 +85 °C ReceiverInputRange 0 2.4 V SupplyNoiseVoltage(VCC ) 100 mV P-P

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www.ti.com SNLS189A –APRIL 2005–REVISED APRIL 2013 ElectricalCharacteristics(1)(2)(3) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (applytopinsPWRDN, RCLK_R/ F,REN, REFCLK = inputs;applytopins ROUT, RCLK, LOCK = outputs) VIH HighLevelInputVoltage 2.0 VCC V VIL Low LevelInputVoltage GND 0.8 V VCL InputClamp Voltage ICL = −18 mA −0.62 −1.5 V IIN InputCurrent VIN = 0V or3.6V −10 ±1 +15 μA VOH HighLevelOutputVoltage IOH = −9 mA 2.2 3.0 VCC V VOL Low LevelOutputVoltage IOL = 9 mA GND 0.25 0.5 V IOS OutputShortCircuitCurrent VOUT = 0V −15 −47 −85 mA IOZ TRI-STATE OutputCurrent PWRDN orREN = 0.8V,VOUT = 0V orVCC −10 ±0.1 +10 μA DESERIALIZER Bus LVDS DC SPECIFICATIONS (applytopinsRI+ and RI−) VTH DifferentialThresholdHighVoltage +6 +50 mV VCM = +1.1V VTL DifferentialThresholdLow Voltage −50 −12 mV VIN = +2.4V,VCC = 3.6Vor0V −10 ±1 +15 μA IIN InputCurrent VIN = 0V,VCC = 3.6Vor0V −10 ±0.05 +10 μA DESERIALIZER SUPPLY CURRENT (applytopinsDVCC and AVCC) f= 30 MHz 58 75 mADeserializerSupplyCurrentWorst C L = 15 pFCaseICCR f= 40 MHz 58 75 mASee Figure2 f= 66 MHz 90 110 mA ICCXR DeserializerSupplyCurrent PWRDN = 0.8V,REN = 0.8V 0.36 1.0 mAPowerdown (1) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages. (3) ForthepurposeofspecifyingdeserializerPLL performance,tDSR1 and tDSR2 arespecifiedwiththeREFCLK runningand stable,and withspecificconditionsfortheincomingdatastream(SYNCPATs). Itisrecommended thatthederserializerbe initializedusingeither tDSR1 timingortDSR2 timing.tDSR1 isthetimerequiredforthedeserializertoindicatelockupon power-uporwhen leavingthepower- down mode. Synchronizationpatternsshouldbe senttothedevicebeforeinitiatingeithercondition.tDSR2 isthetimerequiredtoindicate lockforthepowered-upand enableddeserializerwhen theinput(RI+and RI-)conditionschange fromnotreceivingdatatoreceiving synchronizationpatterns(SYNCPATs). DeserializerTiming Requirements forREFCLK Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units tRFCP REFCLK Period 15.15 T 33.33 ns tRFDC REFCLK DutyCycle 30 50 70 % tRFCP / RatioofREFCLK toTCLK 95 1 105tTCP tRFTT REFCLK TransitionTime 3 6 ns Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS92LV1224

SNLS189A –APRIL 2005–REVISED APRIL 2013 www.ti.com DeserializerSwitchingCharacteristics(1)(2) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbo Parameter Conditions Pin/Freq. Min Typ Max Unitsl ReceiveroutClocktRCP tRCP = tTCP RCLK 15.15 33.33 nsPeriod Rout(0-9),CMOS/TTL Low-to-HightCLH LOCK, 1.2 4 nsTransitionTime CL = 15 pF RCLK See Figure3 CMOS/TTL High-to-LowtCHL 1.1 4 nsTransitionTime RCLK 0.4*tRCP 0.5*tRCP ns30MHz ROUT Data Validbefore RCLKtROS See Figure6 0.4*tRCP 0.5*tRCP nsRCLK 40MHz RCLK 0.38*tRCP 0.5*tRCP ns66MHz 30MHz −0.4*tRCP −0.5*tRCP nsROUT Data validaftertROH RCLK See Figure6 40MHz −0.4*tRCP −0.5*tRCP ns 66MHz −0.38*tRCP −0.5*tRCP ns tRDC RCLK DutyCycle 45 50 55 % tHZR HIGH toTRI-STATE Delay 2.8 10 ns tLZR LOW toTRI-STATE Delay 2.8 10 ns See Figure7 Rout(0-9) tZHR TRI-STATE toHIGH Delay 4.2 10 ns tZLR TRI-STATE toLOW Delay 4.2 10 ns 30MHz 1.68 3 μsDeserializerPLL Lock time tDSR1 fromPWRDWN (with 40MHz 1.31 3 μs SYNCPAT) 66MHz 0.84 3 μs 30MHz 0.62 1 μs DeserializerPLL Lock timetDSR2 40MHz 0.47 1 μsfromSYNCPAT 66MHz 0.29 0.8 μs TRI-STATE toHIGH DelaytZHLK LOCK 3.7 12 ns(power-up)

30 MHz 650 950 ps

tRNM DeserializerNoiseMargin See (3) 40 MHz 450 730 ps

66 MHz 250 400 ps

(1) tLLHT and tLHLT specificationsareGuranteedBy Design(GBD) usingstatisticalanalysis. (2) Because theSerializerisinTRI-STATE mode, theDeserializerwilllosePLL lockand have toresynchronizebeforedatatransfer. (3) tRNM isa measure ofhow much phase noise(jitter)thedeserializercan tolerateintheincomingdatastreambeforebiterrorsoccur.The DeserializerNoiseMarginisGuaranteedBy Design(GBD) usingstatisticalanalysis.

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www.ti.com SNLS189A –APRIL 2005–REVISED APRIL 2013 AC Timing Diagrams and TestCircuits Figure2. “Worst Case ” DeserializerICC TestPattern Figure3. DeserializerCMOS/TTL Output Load and TransitionTimes Figure4. SYNC Timing Delays Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS92LV1224

Timing shown for RCLK_R/ = LOWF Duty Cycle (t ) =RDC tHIGH t +HIGH tLOW DS92LV1224 SNLS189A –APRIL 2005–REVISED APRIL 2013 www.ti.com Figure5. DeserializerDelay Figure6. DeserializerData ValidOut Times Figure7. DeserializerTRI-STATE TestCircuitand Timing

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www.ti.com SNLS189A –APRIL 2005–REVISED APRIL 2013 Figure8. DeserializerPLL Lock Times and PWRDN TRI-STATE Delays Figure9. DeserializerPLL Lock Time from SyncPAT Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS92LV1224

SNLS189A –APRIL 2005–REVISED APRIL 2013 www.ti.com SW -Setupand HoldTime (InternalData SamplingWindow) tDJIT -SerializerOutputBitPositionJitterthatresultsfromJitteron TCLK tRNM = ReceiverNoiseMarginTime Figure10. ReceiverBus LVDS InputSkew Margin DeserializerTruthTable(4)(5)(6) INPUTS OUTPUTS PWRDN REN ROUT [0:9] LOCK RCLK H H Z H Z H H Active L Active L X Z Z Z H L Z Active Z (4) LOCK ActiveindicatestheLOCK outputwillreflectthestateoftheDeserializerwithregardtotheselecteddatastream. (5) RCLK ActiveindicatestheRCLK willbe runningiftheDeserializerislocked.The TimingofRCLK withrespecttoROUT isdetermined by RCLK_R/ F (6) ROUT and RCLK areTRI-STATED when LOCK isassertedHigh.

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APPLICATION INFORMATION

USING THE SERIALIZER AND DESERIALIZER CHIPSET The Serializerand Deserializerchipsetisan easy to use transmitterand receiverpairthatsends 10 bitsof parallelLVTTL dataovera serialBus LVDS linkup to660 Mbps. An on-boardPLL serializestheinputdataand embeds two clockbitswithinthedatastream.The Deserializeruses a separatereferenceclock(REFCLK) and an onboard PLL toextracttheclockinformationfrom theincomingdatastreamand thendeserializethedata. The Deserializermonitorstheincomingclockinformation,determineslockstatus,and assertstheLOCK output highwhen lossoflockoccurs. POWER CONSIDERATIONS An allCMOS designoftheSerializerand Deserializermakes them inherentlylow power devices.Inaddition,the constantcurrentsource natureof the Bus LVDS outputsminimizesthe slopeof the speed vs.ICC curve of conventionalCMOS designs. POWERING UP THE DESERIALIZER The DS92LV1224 can be powered up atany timeby followingthepropersequence.The REFCLK inputcan be runningbeforetheDeserializerpowers up,and itmust be runninginorderfortheDeserializertolocktoincoming data.The Deserializeroutputswillremain inTRI-STATE untilthe Deserializerdetectsdata transmissionat its inputsand lockstotheincomingdatastream. TRANSMITTING DATA Once you power up theSerializerand Deserializer,theymust be phase lockedtoeach othertotransmitdata. Phase lockingoccurswhen theDeserializerlockstoincomingdataor when theSerializersends patterns.The Serializersends SYNC patternswhenever the SYNC1 or SYNC2 inputsare high.The LOCK outputof the Deserializerremainshighuntilithas lockedto the incomingdata stream.ConnectingtheLOCK outputof the Deserializerto one of the SYNC inputsof the Serializerwillensure thatenough SYNC patternsare sentto achieveDeserializerlock. The Deserializercan alsolocktoincomingdataby simplypoweringup thedeviceand allowingthe“random lock” circuitrytofindand locktothedatastream. WhiletheDeserializerLOCK outputislow,dataattheDeserializeroutputs(ROUT0-9) isvalid,exceptforthe specificcase oflossoflockduringtransmissionwhichisfurtherdiscussedinthe"RecoveringfromLOCK Loss" sectionbelow. NOISE MARGIN The Deserializernoisemarginistheamount ofinputjitter(phasenoise)thattheDeserializercan tolerateand still reliablyreceivedata.Variousenvironmentaland systematicfactorsinclude: Serializer:TCLK jitter,VCC noise(noisebandwidthand out-of-bandnoise) Media:ISI,LargeVCM shifts Deserializer:VCC noise RECOVERING FROM LOCK LOSS In the case where the Deserializerloseslockduringdata transmission,up to 3 cyclesof data thatwere previouslyreceivedcan be invalid.Thisisdue tothedelayinthelockdetectioncircuit.The lockdetectcircuit requiresthatinvalidclockinformationbe received4 times in a row to indicatelossof lock.Since clock informationhas been lost,itis possiblethatdata was also lostduringthese cycles.Therefore,afterthe Deserializerrelockstotheincomingdatastreamand theDeserializerLOCK pingoes low,atleastthreeprevious datacyclesshouldbe suspectforbiterrors. The Deserializercan relockto the incomingdata stream by making the Serializerresend SYNC patterns,as describedabove, or by random locking,which can take more time,depending on the data patternsbeing received. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS92LV1224

SNLS189A –APRIL 2005–REVISED APRIL 2013 www.ti.com HOT INSERTION Allthe BLVDS devicesare hot pluggableifyou followa few rules.When inserting,ensure the Ground pin(s) makes contactfirst,then the VCC pin(s),and then the I/O pins.When removing,the I/O pins should be unpluggedfirst,thentheVCC, thentheGround.Random lockhotinsertionisillustratedinFigure13 PCB CONSIDERATIONS The Bus LVDS Serializerand Deserializershouldbe placedas closeto the edge connectoras possible.In multipleDeserializerapplications,thedistancefrom theDeserializertotheslotconnectorappearsas a stubto theSerializerdrivingthebackplanetraces.Longer stubslowertheimpedance ofthebus,increasetheloadon theSerializer,and lowerthethresholdmarginattheDeserializers.Deserializerdevicesshouldbe placedmuch lessthan one inchfrom slotconnectors.Because transitiontimesare very faston the SerializerBus LVDS outputs,reducingstublengthsas much as possibleisthebestmethod toensuresignalintegrity. TRANSMISSION MEDIA The Serializerand Deserializercan alsobe used inpoint-to-pointconfigurationofa backplane,througha PCB trace,or throughtwistedpaircable.In point-to-pointconfiguration,the transmissionmedia need only be terminatedat the receiverend. Please note thatin point-to-pointconfiguration,the potentialof offsettingthe ground levelsof the Serializervs.the Deserializermust be considered.Also,Bus LVDS providesa +/− 1.2V common mode rangeatthereceiverinputs. FailsafeBiasingfortheDS92LV1224 The DS92LV1224 has an improved inputthresholdsensitivityof +/− 50mV versus +/− 100mV for the DS92LV1210 orDS92LV1212. ThisallowsforgreaterdifferentialnoisemarginintheDS92LV1224. However,in cases where the receiverinputisnot beingactivelydriven,the increasedsensitivityof the DS92LV1224 can pickupnoiseas a signaland cause unintentionallocking.For example,thiscan occurwhen theinputcableis disconnected. Externalresistorscan be added tothereceivercircuitboardtopreventnoisepick-up.Typically,thenon-inverting receiverinputispulledup and theinvertingreceiverinputispulleddown by highvalueresistors.thepull-upand pull-downresistors(R1 and R 2) providea currentpath throughthe terminationresistor(RL) which biasesthe receiverinputswhen theyarenotconnectedtoan activedriver.The valueofthepull-upand pull-downresistors shouldbe chosen so thatenough currentisdrawn to providea +15mV drop acrossthe terminationresistor. Pleasesee Figure11 fortheFailsafeBiasingSetup. USING TDJIT AND TRNM TO VALIDATE SIGNAL QUALITY The parameterstDJIT and tRNM can be used togeneratean eye patternmask tovalidatesignalqualityinan actual applicationorinsimulation. The parametertDJIT measures thetransmitter'sabilitytoplacedatabitsintheidealpositiontobe sampled by the receiver.The typicaltDJIT parameterof−80 ps indicatesthatthecrossingpointoftheTx datais80 ps ahead of theidealcrossingpoint.The tDJIT(min)and tDJIT(max) parametersspecifytheearliestand latest,respectively,time thata crossingwilloccurrelativetotheidealposition. The parametertRNM iscalculatedby firstmeasuringhow much of the idealbitthe receiverneeds to ensure correctsampling.Afterdeterminingthisamount, what remains of the idealbitthatisavailableforexternal sourcesofnoiseiscalledtRNM .ItistheoffsetfromtDJIT(minor max) forthetestmask withintheeye opening. The verticallimitsofthemask aredeterminedby theDS92LV1224 receiverinputthresholdof+/− 50 mV. Pleaserefertotheeye mask patternofFigure11 fora graphicrepresentationoftDJIT and tRNM .

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www.ti.com SNLS189A –APRIL 2005–REVISED APRIL 2013 Figure11. FailsafeBiasingSetup Figure12. Using tDJIT and tRNM toGenerate an Eye PatternMask and ValidateSignalQuality Figure13. Random Lock Hot Insertion Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS92LV1224

SNLS189A –APRIL 2005–REVISED APRIL 2013 www.ti.com Pin Diagrams Figure14. 28-Lead SSOP See DB Package DESERIALIZER PIN DESCRIPTION Pin Name I/O No. Description ROUT O 15–19,24–28 Data Output.±9 mA CMOS leveloutputs. RCLK_R/ F I 2 RecoveredClockRising/Fallingstrobeselect.TTL levelinput.SelectsRCLK activeedge forstrobingofROUT data.Highselectsrisingedge.Low selects fallingedge. RI+ I 5 + SerialData Input.Non-invertingBus LVDS differentialinput. RI− I 6 − SerialData Input.InvertingBus LVDS differentialinput. PWRDN I 7 Powerdown. TTL levelinput.PWRDN drivenlowshutsdown thePLL and TRI- STATEs outputsputtingthedeviceintoa lowpower sleepmode. LOCK O 10 LOCK goes lowwhen theDeserializerPLL locksontotheembedded clock edge.CMOS leveloutput.Totem poleoutputstructure,does notdirectly supportwireOR connection. RCLK O 9 RecoveredClock.Paralleldatarateclockrecoveredfromembedded clock. Used tostrobeROUT, CMOS leveloutput. REN I 8 OutputEnable.TTL levelinput.TRI-STATEs ROUT0 –ROUT9, LOCK and RCLK when drivenlow. DVCC I 21,23 DigitalCircuitpower supply. DGND I 14,20,22 DigitalCircuitground. AVCC I 4,11 Analogpower supply(PLL and AnalogCircuits). AGND I 1,12,13 Analogground(PLL and AnalogCircuits). REFCLK I 3 Use thispintosupplya REFCLK signalfortheinternalPLL frequency.

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www.ti.com SNLS189A –APRIL 2005–REVISED APRIL 2013

REVISION HISTORY

Changes from Original(April2013)toRevisionA Page Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS92LV1224

www.ti.com 29-May-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS92LV1224TMSA ACTIVE SSOP DB 28 47 TBD Call TI Call TI -40 to 85 DS92LV1224T MSA DS92LV1224TMSA/NOPB ACTIVE SSOP DB 28 47 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 DS92LV1224T MSA DS92LV1224TMSAX/NOPB ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 DS92LV1224T MSA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 29-May-2015 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant DS92LV1224TMSAX/NOP B PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV1224TMSAX/NOP B SSOP DB 28 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Pack Materials-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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