DS92LV1212TMSA

DS92LV1212 NSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 13

Technical content

Features

n Clock recovery without SYNC patterns-random lock n Guaranteed transition every data transfer cycle n Chipset (Tx + Rx) power consumption< 300mW (typ)@ 40MHz n Single differential pair eliminates multi-channel skew n 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock) n 10-bit parallel interface for 1 byte data plus 2 control bits or UTOPIA I Interface n Synchronization mode and LOCK indicator n Flow-through pinout for easy PCB layout n High impedance on receiver inputs when power is off n Programmable edge trigger on clock n Footprint compatible with DS92LV1210 n Small 28-lead SSOP package-MSA Block Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. DS100982-1 April 1999 DS92LV1212 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery © 1999 National Semiconductor Corporation DS100982 www.national.com

Block Diagram (Continued) Functional Description The DS92LV1212 is a 10-bit Deserializer chip designed to receive data over a heavily loaded differential backplanes at clock speeds from 16 MHz to 40 MHz. It may also be used to receive data over Unshielded Twisted Pair (UTP) cable. The chip has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two passive states: Powerdown and TRI-STATE ® . The following sections describe each operation and passive state. Initialization Before data can be transferred the Deserializer must be ini- tialized. The Deserializer should be powered up with the PWRDN pin held low. After V CC stabilizes the PWRDN pin can be forced high. The Deserializer is ready to lock to the incoming data stream. Step 1: When V CC is applied to the Deserializer, the respec- tive outputs are held in TRI-STATE and internal circuitry is disabled by on-chip power-on circuitry. When V CC reaches VCC OK (2.5V) the PLL is ready to lock to incoming data or synchronization patterns. The local clock is applied to the REFCLK pin. The Deserializer LOCK output will remain high while its PLL is locking to the incoming data or to SYNC patterns on the in- put. Step 2: The Deserializer PLL must synchronize to the Serial- izer to complete the initialization. The Deserializer will lock to non-repetitive data patterns, however, the transmission of SYNC patterns to the Deserializer enables the Deserializer to lock to the Serializer signal within a specified time. Control of the Serializer SYNC1/2 pins is left to the user. A feedback loop between the LOCK pin is one recommenda- tion. Another option is that one or both of the Serializer SYNC inputs are asserted for at least 1024 cycles of TCLK to initiate transmission of SYNC patterns. The Serializer will continue to send SYNC patterns after the minimum of 1024 if either of the SYNC inputs remain high. When the Deserializer detects edge transitions at the Bus LVDS input it will attempt to lock to the embedded clock in- formation. When the Deserializer locks to the Bus LVDS clock, the LOCK output will go low. When LOCK is low the Deserializer outputs represent incoming Bus LVDS data. Data Transfer Serialized data and clock bits (10+2 bits) are received at 12 times the TCLK frequency. For example, if TCLK is 40 MHz, the serial rate is 40 x 12 = 480 Mega bits per second. Since only 10 bits are from input data, the serial “payload” rate is 10 times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data rate is 40 x 10 = 400 Mbps. TCLK is provided by the data source and must be in the range 16 MHz to 40 MHz nominal. The LOCK pin on the Deserializer is driven low when it is synchronized with the Serializer. The Deserializer locks to the embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low. Otherwise ROUT0–ROUT9 is invalid. RCLK pin is the reference to data on the ROUT0-ROUT9 pins. The polarity of the RCLK edge is controlled by the RCLK_R/F input. ROUT(0-9), LOCK and RCLK outputs will drive a minimum of three CMOS input gates (15 pF load) with 40 MHz clock. Resynchronization The Deserializer LOCK pin driven low indicates that the De- serializer PLL is locked to the embedded clock edge. If the Deserializer loses lock, the LOCK output will go high and the outputs (including RCLK) will be TRI-STATE. The LOCK pin must be monitored by the system to detect a loss of synchronization. The system can arrange to pulse the Serializer SYNC1 or SYNC2 pin to resynchronize. There are multiple approaches possible. One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync request of the Serializer (SYNC1 or SYNC2). A minimum of 1024 sync patterns are needed to resynchro- nize. Dual SYNC pins are provided for multiple control in a multi-drop application. Application DS100982-2 www.national.com 2

Random Lock Initialization and Resynchronization The initialization and resynchronization methods described in their respective sections are the fastest ways to establish the link between the Serializer and Deserializer, however, the DS92LV1212 can attain lock to a data stream without re- quiring special SYNC patterns to be sent by the Serializer. This allows the DS92LV1212 to be used in applications where the Deserializer must operate “open-loop” and sup- ports hot insertion into a running backplane. Because the data stream is essentially random the time for the DS92LV1212 to attain lock is variable and cannot be pre- dicted. The primary constraint on the “random” lock time is the initial phase relation when the Deserializer is powered up. The data contained in the data stream can also affect lock time. Typical lock times for random data have a mean of 570us and a max of 4.9ms. If a specific pattern is repetitive the Deserializer could be misled into a “false lock” - falsely recognizing the data pat- tern as the clocking bits. We refer to such a pattern as a re- petitive multi-transition, RMT. This is when there is more than one Low-High transition in a single clock cycle. This occurs when any bit, except DIN 9, is held at a low state and the ad- jacent bit is held high creating a 0-1 transition. In the worst case the Deserializer could become locked to the data pat- tern rather than the clock. Circuitry within the DS92LV1212 can detect that the possibility of “false lock” exists (by detect- ing that there is more than 1 potential position for clocking bits) and will prevent the LOCK* output from becoming ac- tive until the potential “false lock” pattern changes. It is ex- pected that the data will eventually change causing the De- serializer to lose lock to the data pattern and continue searching for the clock bits in the serial data stream. A graphical representation of a few cases of RMT is shown below. Please note that RMT applies to bits DIN0-DIN8. Powerdown The Powerdown state is a low power sleep mode that can be used to reduce power when there is no data to be trans- ferred. Powerdown is entered when PWRDN and REN are driven low on the Deserializer. In Powerdown, the PLL is stopped and the outputs go into TRI-STATE, disabling load current and also reducing supply current to the milliamp range. To exit Powerdown, PWRDN is driven high. Both the Serializer and Deserializer must re-initialize and re- synchronize before data can be transferred. Initialization of the Serializer takes 1024 TCLK cycles. The Deserializer will initialize and assert LOCK high until it is locked to the Bus LVDS clock. TRI-STATE For the Deserializer, TRI-STATE is entered when the REN pin is driven low. This will TRI-STATE the receiver output pins (ROUT0–ROUT9), LOCK and RCLK. www.national.com3

DS92LV1021TMSA Serializer MSA28 DS92LV1212TMSA Deserializer MSA28 DS100982-23 DIN0 Held Low-DIN1 Held High Creates an RMT Pattern DS100982-24 DIN4 Held Low-DIN5 Held High Creates an RMT Pattern DS100982-25 DIN8 Held Low-DIN9 Held High Creates an RMT Pattern www.national.com 4

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC ) −0.3V to +4V CMOS/TTL Input Voltage −0.3V to (V CC +0.3V) CMOS/TTL Output Voltage −0.3V to (V CC +0.3V) Bus LVDS Receiver Input Voltage −0.3V to +3.9V Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature (Soldering, 4 seconds) +260˚C Maximum Package Power Dissipation Capacity @ 25˚C Package: 28L SSOP 1.27 W Package Derating: 28L SSOP 10.2 mW/˚C above +25˚C ESD Rating (HBM) >2.5kV Recommended Operating Conditions Min Nom Max Units Supply Voltage (VCC ) 3.0 3.3 3.6 V Operating Free Air Temperature (TA) −40 +25 +85 ˚C Receiver Input Range 0 2.4 V Supply Noise Voltage (VCC ) 100 mV P-P

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units DESERIALIZER CMOS/TTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply to pins ROUT, RCLK, LOCK = outputs) VIH High Level Input Voltage 2.0 V CC V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage I CL = −18 mA −0.62 −1.5 V IIN Input Current V IN = 0V or 3.6V −10 ±2 +10 µA VOH High Level Output Voltage IOH = −9 mA 2.1 2.93 V CC V VOL Low Level Output Voltage I OL = 9 mA GND 0.33 0.6 V IOS Output Short Circuit Current VOUT = 0V −15 −38 −85 mA IOZ TRI-STATE Output Current PWRDN or REN = 0.8V, V OUT =0 Vo rV C C −10 ±0.4 +10 µA DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−) VTH Differential Threshold High Voltage VCM = +1.1V +6 +100 mV VTL Differential Threshold Low Voltage −100 −12 mV I IN Input Current V IN = +2.4V, VCC = 3.6V or 0V −10 ±5 +10 µA VIN = 0V, VCC = 3.6V or 0V −10 ±5 +10 µA DESERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC) I CCR Deserializer Supply Current CL = 15 pF f = 40 MHz 47 60 mA Worst Case Figure 1 f = 16 MHz 30 40 mA ICCXR Deserializer Supply Current Powerdown PWRDN = 0.8V, REN = 0.8V 0.34 1.0 mA Deserializer Timing Requirements for REFCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tRFCP REFCLK Period 25 T 62.5 ns tRFDC REFCLK Duty Cycle 50 % fRef REFCLK Frequency 0.95/t RCP tRCP 1.05/tRCP tRFTT REFCLK Transition Time 3 6 ns www.national.com5

Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tRCP Receiver out Clock Period Figure 3 tRCP =tTCP RCLK 25 62.5 ns tCLH CMOS/TTL Low-to-High Transition Time C L=1 5p F Figure 2 Rout(0-9), 26 n s tCHL CMOS/TTL High-to-Low Transition Time LOCK, RCLK 26 n s tROS ROUT (0-9) Setup Data to RCLK Figure 5 RCLK 0.4*tRCP 0.5*tRCP ns tROH ROUT (0-9) Hold Data to RCLK −0.4*tRCP −0.5*tRCP ns tRDC RCLK Duty Cycle 40 50 60 % tHZR HIGH to TRI-STATE Delay Figure 6 Rout(0-9), LOCK 4.2+0.5*tRCP 10+tRCP ns tLZR LOW to TRI-STATE Delay 4.5+0.5*t RCP 10+tRCP ns tZHR TRI-STATE to HIGH Delay 6+0.5*t RCP 12+tRCP ns tZLR TRI-STATE to LOW Delay 6.0+0.5*t RCP 12+tRCP ns tDSR1 Deserializer PLL Lock Time from PWRDWN (with SYNCPAT) (Note 4) Figure 7 Figure 8 16MHz 18.2 22 µs 40MHz 7.4 25.6 µs tDSR2 Deserializer PLL Lock time from SYNCPAT 16MHz 21.0 30 µs 40MHz 14.4 25 µs tZHLK TRI-STATE to HIGH Delay (power-up) LOCK 4.62 12 ns tRNM Deserializer Noise MarginFigure 9 (Note 5)

16 MHz 400 1100 ps

40 MHz 100 400 ps

Note 1:“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2:Typical values are given for VCC = 3.3V and TA = +25˚C. Note 3:Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD,ΔVOD, VTH and VTL which are differential voltages. Note 4:For the purpose of specifying Deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions of the incoming data stream (SYNCPATs). It is recommended that the Deserializer be initialized using either tDSR1 timing or tDSR2 timing. tDSR1 is thetime required for the Deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device beforeinitiating ei- ther condition. tDSR2 is the time required to indicate lock for the powered-up and enabled Deserializer when the input (RI+ and RI-) conditions changefrom not re- ceiving data to receiving synchronization patterns (SYNCPATs). Note 5:tRNM is a measure of how much phase noise (jitter) the Deserializer can tolerate in the incoming data stream before bit errors occur. www.national.com 6

loads between 27 and 100 Ohms. one volt common mode range at the receiver inputs. Data Output.±9 mA CMOS level outputs. to synchronize to the bus traffic and receive data. FIGURE 10. Random Lock Allows Hot Insertion into Serial Busses

Deserializer Pin Description(Continued) Pin Name I/O No. Description RCLK_R/F I 2 Recovered Clock Rising/Falling strobe select. TTL level input. Selects RCLK active edge for strobing of ROUT data. High selects rising edge. Low selects falling edge. RI+ I 5 + Serial Data Input. Non-inverting Bus LVDS differential input. RI− I 6 − Serial Data Input. Inverting Bus LVDS differential input. PWRDN I 7 Powerdown. TTL level input. PWRDN driven low shuts down the PLL. LOCK O 10 LOCK goes low when the Deserializer PLL locks onto the embedded clock edge. CMOS level output. Totem pole output structure, does not directly support wire OR connection. RCLK O 9 Recovered Clock. Parallel data rate clock recovered from embedded clock. Used to strobe ROUT, CMOS level output. REN I 8 Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9, LOCK and RCLK when driven low. DVCC I 21, 23 Digital Circuit power supply. DGND I 14, 20, 22 Digital Circuit ground. AVCC I 4, 11 Analog power supply (PLL and Analog Circuits). AGND I 1, 12, 13 Analog ground (PLL and Analog Circuits). REFCLK I 3 Use this pin to supply a REFCLK signal for the internal PLL frequency. Truth Table RI RI− RCLK_R/F REFCLK REN PWRDN RCLK LOCK ROUT (0–9) X X X SYSTEM CLK X 0 Z Z Z Z Z X SYSTEM CLK X X Z Z Z DATA (0–9) DATA (0–9)* X SYSTEM CLK 0 1 Z L → Z* * Z DATA (0–9) DATA (0–9)* X SYSTEM CLK 0 1 Z H → PLL ** Z SYNC PTRN SYNC PTRN* X SYSTEM CLK 1 1 CLK 1 SYNC PTRN DATA (0–9) DATA (0–9)* 1 SYSTEM CLK 1 1 L 0 DATA DATA (0–9) DATA (0–9)* 0 SYSTEM CLK 1 1 K 0 DATA * Inverted **If the Rx is locked when REN goes low the LOCK* output will go Tri-state on the rising edge of REFCLK. If the Rx is not locked when REN goes low the LOCK* output will remain active. It will be high as the Rx is not locked but should the Rx attain lock the LOCK* output will go low to indicate lock. www.national.com 12

Physical Dimensionsinches (millimeters) unless otherwise noted LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com Order Number DS92LV1021TMSA or DS92LV1212TMSA DS92LV1212 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.