DS92LV1023E

DS92LV1023E_14 TI1 | Alldatasheet

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-TO -SERIAL INPUT LATCH PLL TIMING and CONTROL D O+ D O- DEN D IN TCLK (30 MHz to 66 MHz) SYNC1 SYNC2 SERIAL -TO -PARALLEL OUTPUT LATCH PLL TIMING and CONTROL R I+ R I- LVDS R OUT REFCLK LOCK CLOCK RECOVERY REN (30 MHz to 66 MHz) TCLK_R/F RCLK_R/F DS92LV1023E 10-Bit Deserializer RCLK DS92LV1023E www.ti.com SNLS187B –MARCH 2005–REVISED APRIL 2013 DS92LV1023E30-66MHz10BitBusLVDSSerializer Check forSamples: DS92LV1023E 1FEATURES DESCRIPTION The DS92LV1023E isa 300 to660 Mb/s serializerfor 2• 30–66 MHz Single10:1Serializerwith300–660 high-speed unidirectionalserialdata transmissionMb/s Throughput over FR-4 printedcircuitboard backplanes and• Robust Bus LVDS SerialData Transmission balancedcopper cables.Ittransformsa 10-bitwide withEmbedded Clock forExceptionalNoise parallelLVCMOS/LVTTL data bus intoa singlehigh Immunity and Low EMI speed Bus LVDS serialdata stream withembedded clock.This singleserialdata stream simplifiesPCB• >10 kV HBM ESD Protectionon Bus LVDS design and reduces PCB cost by narrowingdataOutput Pins paths thatin turnreduce PCB sizeand number of• TransitionEvery Data TransferCycle Ensured layers.The singleserialdata stream also reduces

• Low Power Consumption < 250 mW (typ)at66 cablesize,thenumber ofconnectors,and eliminates MHz clock-to-dataand data-to-dataskew.
• SingleDifferentialPairEliminatesMultichannel The DS92LV1023E works well with any TI Skew Semiconductor'sBus LVDS 10–bitdeserializerwithin itsspecifiedfrequencyoperatingrange.Itfeatures• Flow-Through PinoutforEasy PCB Layout exceptionalESD protection,pin selectableedge• Programmable Edge Triggeron Clock triggeron clock,and high impedance outputsin• High Impedance on DriverOutputs When power down mode. Power isOff The DS92LV1023E was designed with the flow-• Bus LVDS SerialOutput Rated for27Ω Load throughpinoutand is availablein a space saving
• Small 28-Lead SSOP Package 28–leadSSOP package. Block Diagrams Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2005–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS187B –MARCH 2005–REVISED APRIL 2013 www.ti.com FunctionalDescription The DS92LV1023E isa 10-bitSerializerdevicewhichtogetherwitha compatibledeserializer(i.e.DS92LV1224) forms a chipsetdesignedto transmitdata over FR-4 printedcircuitboard backplanesand balancedcopper cablesatclockspeeds from30 to66 MHz. The chipsethas threeactivestatesof operation:Initialization,Data Transfer,and Resynchronization;and two passivestates:Powerdown and TRI-STATE. The followingsectionsdescribeeach operationand passivestate. Initialization Initializationofbothdevicesmust occurbeforedatatransmissionbegins.Initializationreferstosynchronizationof the Serializerand DeserializerPLL's to localclocks,which may be the same or separate.Afterwards, synchronizationoftheDeserializertoSerializeroccurs. Step 1:When you applyVCC tobothSerializerand/orDeserializer,therespectiveoutputsenterTRI-STATE, and on-chippower-oncircuitrydisablesinternalcircuitry.When VCC reachesVCC OK (2.5V)thePLL ineach device beginslockingtoa localclock.For theSerializer,thelocalclockisthetransmitclock(TCLK) providedby the sourceASIC orotherdevice.FortheDeserializer,you must applya localclocktotheREFCLK pin. The Serializeroutputsremain in TRI-STATE whilethe PLL locksto the TCLK. Afterlockingto TCLK, the Serializerisnow readytosend dataorSYNC patterns,dependingon thelevelsoftheSYNC1 and SYNC2 inputs or a datastream.The SYNC patternsentby theSerializerconsistsofsixones and sixzerosswitchingatthe inputclockrate. Note thatthe DeserializerLOCK outputwillremain highwhileitsPLL locksto the incomingdata or to SYNC patternson theinput. Step 2:The DeserializerPLL must synchronizetotheSerializertocompleteinitialization.The Deserializerwill locktonon-repetitivedatapatterns.However,thetransmissionofSYNC patternsenablestheDeserializertolock totheSerializersignalwithina specifiedtime.See Figure7. The user'sapplicationdeterminescontrolof the SYNC1 and SYNC 2 pins.One recommendationisa direct feedbackloopfrom the LOCK pin.Under allcircumstances,the SerializerstopssendingSYNC patternsafter bothSYNC inputsreturnlow. When theDeserializerdetectsedge transitionsattheBus LVDS input,itwillattempttolocktotheembedded clockinformation.When theDeserializerlockstotheBus LVDS clock,theLOCK outputwillgo low.When LOCK islow,theDeserializeroutputsrepresentincomingBus LVDS data.

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www.ti.com SNLS187B –MARCH 2005–REVISED APRIL 2013 Data Transfer Afterinitialization,theSerializerwillacceptdatafrom inputsDIN0–DIN9. The Serializeruses theTCLK inputto latchincomingData. The TCLK_R/ F pin selectswhich edge the Serializeruses to strobeincomingdata. TCLK_R/ F highselectstherisingedge forclockingdataand low selectsthefallingedge.IfeitheroftheSYNC inputsishighfor5*TCLK cycles,thedataatDIN0-DIN9 isignoredregardlessofclockedge. Afterdeterminingwhich clockedge touse,a startand stopbit,appended internally,frame thedatabitsinthe register.The startbitisalways high and the stop bitisalways low.The startand stop bitsfunctionas the embedded clockbitsintheserialstream. The Serializertransmitsserializeddataand clockbits(10+2 bits)from theserialdataoutput(DO ±) at12 times theTCLK frequency.For example,ifTCLK is66 MHz, theserialrateis66 × 12 = 792 Mega-bits-per-second. Sinceonly10 bitsarefrominputdata,theserial“payload”rateis10 timestheTCLK frequency.For instance,if TCLK = 66 MHz, thepayloaddatarateis66 × 10 = 660 Mbps. The datasourceprovidesTCLK and must be in therangeof30 MHz to66 MHz nominal. The Serializeroutputs(DO ±) can drivea point-to-pointconnectionor in limitedmulti-pointor multi-drop backplanes.The outputstransmitdata when the enablepin(DEN) ishigh,PWRDN = high,and SYNC1 and SYNC2 arelow.When DEN isdrivenlow,theSerializeroutputpinswillenterTRI-STATE. When the Deserializersynchronizesto the Serializer,the LOCK pin is low.The Deserializerlocksto the embedded clockand uses ittorecovertheserializeddata.ROUT dataisvalidwhen LOCK islow.Otherwise ROUT0 –ROUT9 isinvalid. The ROUT0-ROUT9 pinsuse theRCLK pinas thereferencetodata.The polarityoftheRCLK edge iscontrolled by theRCLK_R/ F input. ROUT(0-9),LOCK and RCLK outputswilldrivea maximum ofthreeCMOS inputgates(15 pF load)witha 66 MHz clock. Resynchronization When theDeserializerPLL lockstotheembedded clockedge,theDeserializerLOCK pinassertsa low.Ifthe Deserializerloseslock,theLOCK pinoutputwillgo highand theoutputs(includingRCLK) willenterTRI-STATE. The user'ssystem monitorstheLOCK pintodetecta lossofsynchronization.Upon detection,thesystem can arrangetopulsetheSerializerSYNC1 or SYNC2 pintoresynchronize.Multipleresynchronizationapproaches are possible.One recommendationistoprovidea feedbackloopusingtheLOCK pinitselftocontrolthesync requestoftheSerializer(SYNC1 or SYNC2). Dual SYNC pinsare providedformultiplecontrolina multi-drop application.Sending sync patternsforresynchronizationisdesirablewhen locktimeswithina specifictimeare critical.However,theDeserializercan locktorandom data,whichisdiscussedinthenextsection. Random Lock Initializationand Resynchronization The initializationand resynchronizationmethods describedintheirrespectivesectionsare the fastestways to establishthelinkbetween theSerializerand Deserializer.However, theDS92LV1224 can attainlocktoa data streamwithoutrequiringtheSerializertosend specialSYNC patterns.ThisallowstheDS92LV1224 tooperatein “open-loop” applications.Equallyimportantisthe Deserializer'sabilityto supporthot insertionintoa running backplane.Intheopen looporhotinsertioncase,we assume thedatastreamisessentiallyrandom.Therefore, because locktimevariesdue to data stream characteristics,we cannotpossiblypredictexactlocktime.The primaryconstrainton the “random” locktimeisthe initialphase relationbetween the incomingdata and the REFCLK when theDeserializerpowers up.As describedinthenextparagraph,thedatacontainedinthedata streamcan alsoaffectlocktime. Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS92LV1023E

SNLS187B –MARCH 2005–REVISED APRIL 2013 www.ti.com Ifa specificpatternisrepetitive,theDeserializercouldenter“falselock”-falselyrecognizingthedatapatternas theclockingbits.We refertosuch a patternas a repetitivemulti-transition,RMT. Thisoccurswhen more than one Low-Hightransitiontakesplaceina clockcycleovermultiplecycles.Thisoccurswhen any bit,exceptDIN 9, isheld at a low stateand the adjacentbitisheld high,creatinga 0-1 transition.In the worstcase,the Deserializercouldbecome lockedtothedatapatternratherthantheclock.CircuitrywithintheDS92LV1224 can detectthatthe possibilityof “falselock” exists.The circuitryaccomplishesthisby detectingmore than one potentialpositionforclockingbits.Upon detection,the circuitrywillpreventthe LOCK outputfrom becoming activeuntilthe potential“falselock” patternchanges. The falselockdetectcircuitryexpectsthe data will eventuallychange,causingtheDeserializertoloselocktothedatapatternand thencontinuesearchingforclock bitsintheserialdatastream.GraphicalrepresentationsofRMT are shown inFigure1 .PleasenotethatRMT onlyappliestobitsDIN0-DIN8. Powerdown When no data transferoccurs,you can use the Powerdown state.The Serializerand Deserializeruse the Powerdown state,a low power sleepmode, toreducepower consumption.The DeserializerentersPowerdown when you drivePWRDN and REN low.The SerializerentersPowerdown when you drivePWRDN low.In Powerdown, thePLL stopsand theoutputsenterTRI-STATE, which disablesloadcurrentand reducessupply currenttothemilliampererange.To exitPowerdown, you must drivethePWRDN pinhigh. Beforevaliddataexchanges between theSerializerand Deserializer,you must reinitializeand resynchronizethe devicestoeach other.InitializationoftheSerializertakes510 TCLK cycles.The Deserializerwillinitializeand assertLOCK highuntillocktotheBus LVDS clockoccurs.

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www.ti.com SNLS187B –MARCH 2005–REVISED APRIL 2013 TRI-STATE The SerializerentersTRI-STATE when theDEN pinisdrivenlow.Thisputsbothdriveroutputpins(DO+ and DO −)intoTRI-STATE. When you driveDEN high,theSerializerreturnstothepreviousstate,as longas allother controlpinsremainstatic(SYNC1, SYNC2, PWRDN, TCLK_R/ F). When you drivethe REN pinlow,the DeserializerentersTRI-STATE. Consequently,the receiveroutputpins (ROUT0 –ROUT9) and RCLK willenterTRI-STATE. The LOCK outputremainsactive,reflectingthestateofthe PLL. DIN0 Held Low-DIN1 Held High Createsan RMT Pattern DIN8 Held Low-DIN9 Held High Createsan RMT Pattern DIN4 Held Low-DIN5 Held High Createsan RMT Pattern Figure1.RMT PatternsSeen on theBus LVDS SerialOutput Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS92LV1023E

SNLS187B –MARCH 2005–REVISED APRIL 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2)(3)(4) SupplyVoltage(VCC ) −0.3Vto+4V LVCMOS/LVTTL InputVoltage −0.3Vto(VCC +0.3V) Bus LVDS DriverOutputVoltage −0.3Vto+3.9V Bus LVDS OutputShortCircuit Duration 10ms JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature(Soldering,4 seconds) +260°C Maximum Package Power DissipationCapacity @ 25°C Package: 28L SSOP 1.27W Package Derating: 10.3mW/ °C above 28L SSOP +25°C θja 97°C/W θjc 27°C/W Allpins >7kV Bus LVDS pins >10kV ESD RatingHBM (1.5kOhm,100pF) MM > 250V (1) “AbsoluteMaximum Ratings”arethosevaluesbeyond whichthesafetyofthedevicecannotbe ensured.They arenotmeant toimply thatthedevicesshouldbe operatedattheselimits.The tableof“ElectricalCharacteristics”specifiesconditionsofdeviceoperation. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications (3) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C. (4) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages. Recommended OperatingConditions(1)(2) Min Nom Max Units SupplyVoltage(VCC ) 3.0 3.3 3.6 V OperatingFreeAir Temperature(TA) −40 +25 +85 °C SupplyNoiseVoltage(VCC ) 100 mV P-P (1) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages.

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www.ti.com SNLS187B –MARCH 2005–REVISED APRIL 2013 ElectricalCharacteristics(1)(2) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Parameter TestConditions Min Typ Max Units SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (applytoDIN0-9,TCLK, PWRDN, TCLK_R/ F,SYNC1, SYNC2, DEN) VIH HighLevelInputVoltage 2.0 VCC V VIL Low LevelInputVoltage GND 0.8 V VCL InputClamp Voltage ICL = −18 mA -0.86 −1.5 V IIN InputCurrent VIN = 0V or3.6V −15 ±1 +15 μA SERIALIZER Bus LVDS DC SPECIFICATIONS (applytopinsDO+ and DO −) VOD OutputDifferentialVoltage(DO+)–(DO −) RL = 27Ω,Figure11 200 290 mV ΔVOD OutputDifferentialVoltageUnbalance 35 mV VOS OffsetVoltage 1.05 1.1 1.3 V ΔVOS OffsetVoltageUnbalance 4.8 35 mV IOS OutputShortCircuitCurrent D0 = 0V,DIN = High,PWRDN and DEN = −56 −90 mA2.4V IOZ TRI-STATE OutputCurrent PWRDN orDEN = 0.8V,DO = 0V orVCC −30 ±1 +30 μA IOX Power-OffOutputCurrent VCC = 0V,DO=0V or3.6V −100 ±1 +100 μA C O Single-endedOutputCapacitance Any BLVDS OutputPintoGND 7.5 pF SERIALIZER SUPPLY CURRENT (applytopinsDVCC and AVCC) ICCD SerializerSupplyCurrent RL = 27Ω f= 30 MHz 42 60 mA WorstCase Figure2 f= 66 MHz 75 90 mA ICCXD SerializerSupplyCurrentPowerdown PWRDN = 0.8V 47 500 μA (1) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages. SerializerTiming Requirements forTCLK Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Parameter TestConditions Min Typ Max Units tTCP TransmitClockPeriod 15.15 T 33.33 ns tTCIH TransmitClockHighTime 0.4T 0.5T 0.6T ns tTCIL TransmitClockLow Time 0.4T 0.5T 0.6T ns tCLKT TCLK InputTransitionTime 3 6 ns tJIT TCLK InputJitter psSee Figure10 150 (RMS) Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS92LV1023E

SNLS187B –MARCH 2005–REVISED APRIL 2013 www.ti.com SerializerSwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Parameter TestConditions Min Typ Max Units tLLHT Bus LVDS Low-to-High R L = 27Ω 0.2 0.4 nsTransitionTime C L=10pF toGND Figure3tLHLT Bus LVDS High-to-LowTransitionTime 0.25 0.4 ns(1) tDIS DIN (0-9)SetuptoTCLK R L = 27Ω, 0 ns C L=10pF toGNDtDIH DIN (0-9)HoldfromTCLK 4.0 nsFigure5 tHZD DO ± HIGH to R L = 27Ω, 3 10 nsTRI-STATE Delay C L=10pF toGND Figure6tLZD DO ± LOW toTRI-STATE Delay 3 10 ns(2) tZHD DO ± TRI-STATE toHIGH Delay 5 10 ns tZLD DO ± TRI-STATE toLOW Delay 6.5 10 ns tSPW SYNC PulseWidth R L = 27Ω 5*tTCP ns Figure8tPLD SerializerPLL Lock Time 510*tTCP 513*tTCP ns tSD SerializerDelay R L = 27Ω,Figure9 tTCP + 1.0 tTCP + 2.0 tTCP + 3.0 ns tDJIT DeterministicJitter R L = 27Ω, 30 MHz -350 -45 190 ps C L=10pF toGND,

66 MHz -200 -70 80 ps(3)

tRJIT Random Jitter R L = 27Ω, ps19 25C L=10pF toGND (RMS) (1) tLLHT and tLHLT specificationsareGuranteedBy Design(GBD) usingstatisticalanalysis. (2) Because theSerializerisinTRI-STATE mode, theDeserializerwilllosePLL lockand have toresynchronizebeforedatatransfer. (3) tDJIT specificationsareGuranteedBy Designusingstatisticalanalysis. AC Timing Diagrams and TestCircuits Figure2. “Worst Case ” SerializerICC TestPattern Figure3. SerializerBus LVDS Output Load and TransitionTimes Figure4. SerializerInputClock TransitionTime

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www.ti.com SNLS187B –MARCH 2005–REVISED APRIL 2013 Timingshown forTCLK_R/ F = LOW Figure5. SerializerSetup/HoldTimes Figure6. SerializerTRI-STATE TestCircuitand Timing Figure7. SerializerPLL Lock Time,and PWRDN TRI-STATE Delays Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS92LV1023E

SNLS187B –MARCH 2005–REVISED APRIL 2013 www.ti.com Figure8. SYNC Timing Delays Figure9. SerializerDelay

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www.ti.com SNLS187B –MARCH 2005–REVISED APRIL 2013 SW -Setupand HoldTime (InternalData SamplingWindow) tDJIT -SerializerOutputBitPositionJitterthatresultsfromJitteron TCLK tRNM = ReceiverNoiseMarginTime Figure10. ReceiverBus LVDS InputSkew Margin VOD = (DO +)–(DO −). Differentialoutputsignalisshown as (DO+)–(DO −),deviceinData Transfermode. Figure11. VOD Diagram Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS92LV1023E

SNLS187B –MARCH 2005–REVISED APRIL 2013 www.ti.com

APPLICATION INFORMATION

USING THE SERIALIZER AND DESERIALIZER CHIPSET The Serializerand Deserializerchipsetisan easy to use transmitterand receiverpairthatsends 10 bitsof parallelLVTTL dataovera serialBus LVDS linkup to660 Mbps. An on-boardPLL serializestheinputdataand embeds two clockbitswithinthedatastream.The Deserializeruses a separatereferenceclock(REFCLK) and an onboard PLL toextracttheclockinformationfrom theincomingdatastreamand thendeserializethedata. The Deserializermonitorstheincomingclockinformation,determineslockstatus,and assertstheLOCK output highwhen lossoflockoccurs. POWER CONSIDERATIONS An allCMOS designoftheSerializerand Deserializermakes them inherentlylow power devices.Inaddition,the constantcurrentsource natureof the Bus LVDS outputsminimizesthe slopeof the speed vs.ICC curve of conventionalCMOS designs. TRANSMITTING DATA Once you power up theSerializerand Deserializer,theymust be phase lockedtoeach othertotransmitdata. Phase lockingoccurswhen theDeserializerlockstoincomingdataor when theSerializersends patterns.The Serializersends SYNC patternswhenever the SYNC1 or SYNC2 inputsare high.The LOCK outputof the Deserializerremainshighuntilithas lockedto the incomingdata stream.ConnectingtheLOCK outputof the Deserializerto one of the SYNC inputsof the Serializerwillensure thatenough SYNC patternsare sentto achieveDeserializerlock. The Deserializercan alsolocktoincomingdataby simplypoweringup thedeviceand allowingthe“random lock” circuitrytofindand locktothedatastream. WhiletheDeserializerLOCK outputislow,dataattheDeserializeroutputs(ROUT0-9) isvalid,exceptforthe specificcase oflossoflockduringtransmissionwhichisfurtherdiscussedinthe"RecoveringfromLOCK Loss" sectionbelow. HOT INSERTION Allthe BLVDS devicesare hot pluggableifyou followa few rules.When inserting,ensure the Ground pin(s) makes contactfirst,then the VCC pin(s),and then the I/O pins.When removing,the I/O pins should be unpluggedfirst,thentheVCC, thentheGround.Random lockhotinsertionisillustratedinFigure12. PCB CONSIDERATIONS The Bus LVDS Serializerand Deserializershouldbe placedas closeto the edge connectoras possible.In multipleDeserializerapplications,thedistancefrom theDeserializertotheslotconnectorappearsas a stubto theSerializerdrivingthebackplanetraces.Longer stubslowertheimpedance ofthebus,increasetheloadon theSerializer,and lowerthethresholdmarginattheDeserializers.Deserializerdevicesshouldbe placedmuch lessthan one inchfrom slotconnectors.Because transitiontimesare very faston the SerializerBus LVDS outputs,reducingstublengthsas much as possibleisthebestmethod toensuresignalintegrity. TRANSMISSION MEDIA The Serializerand Deserializercan alsobe used inpoint-to-pointconfigurationofa backplane,througha PCB trace,or throughtwistedpaircable.In point-to-pointconfiguration,the transmissionmedia need only be terminatedat the receiverend. Please note thatin point-to-pointconfiguration,the potentialof offsettingthe ground levelsof the Serializervs.the Deserializermust be considered.Also,Bus LVDS providesa +/− 1.2V common mode rangeatthereceiverinputs.

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www.ti.com SNLS187B –MARCH 2005–REVISED APRIL 2013 Figure12. Random Lock Hot Insertion Pin Diagram Figure13. DS92LV1023EMQ -Serializer See Package Number DB0028A Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS92LV1023E

SNLS187B –MARCH 2005–REVISED APRIL 2013 www.ti.com SerializerPin Description Pin Name I/O Pin No. Description DIN I 3–12 Data Input.LVTTL levelsinputs.Data on thesepinsareloadedintoa 10-bit inputregister. TCLK_R/ F I 13 TransmitClockRising/Fallingstrobeselect.LVTTL levelinput.SelectsTCLK activeedge forstrobingofDIN data.Highselectsrisingedge.Low selects fallingedge. DO+ O 22 + SerialData Output.Non-invertingBus LVDS differentialoutput. DO − O 21 − SerialData Output.InvertingBus LVDS differentialoutput. DEN I 19 SerialData OutputEnable.LVTTL levelinput.A low,putstheBus LVDS outputsinTRI-STATE. PWRDN I 24 Powerdown. LVTTL levelinput.PWRDN drivenlowshutsdown thePLL and TRI-STATEs outputsputtingthedeviceintoa lowpower sleepmode. TCLK I 14 TransmitClock.LVTTL levelinput.Inputfor40 MHz –66 MHz (nominal)system clock. SYNC I 1,2 AssertionofSYNC (high)foratleast1024 synchronizationsymbolstobe transmittedon theBus LVDS serialoutput.Synchronizationsymbolscontinue tobe sentifSYNC continuesasserted.TTL levelinput.The two SYNC pins areORed. DVCC I 27,28 DigitalCircuitpower supply. DGND I 15,16 DigitalCircuitground. AVCC I 17,26 Analogpower supply(PLL and AnalogCircuits). AGND I 18,25,20,23 Analogground(PLL and AnalogCircuits).

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www.ti.com SNLS187B –MARCH 2005–REVISED APRIL 2013

REVISION HISTORY

Changes from RevisionA (April2013)toRevisionB Page Copyright© 2005–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS92LV1023E

www.ti.com 13-Sep-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS92LV1023EMQ/NOPB ACTIVE SSOP DB 28 47 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 DS92LV1023 EMQ DS92LV1023EMQX/NOPB ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 DS92LV1023 EMQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 13-Sep-2014 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant DS92LV1023EMQX/NOP B PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV1023EMQX/NOPB SSOP DB 28 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Pack Materials-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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