DS92LV1021TMSA

DS92LV1212A NSC | Alldatasheet

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Technical content

Features

n Clock recovery without SYNC patterns-random lock n Guaranteed transition every data transfer cycle n Chipset (Tx + Rx) power consumption< 300mW (typ)@ 40MHz n Single differential pair eliminates multi-channel skew n 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock) n 10-bit parallel interface for 1 byte data plus 2 control bits or UTOPIA I Interface n Synchronization mode and LOCK indicator n Flow-through pinout for easy PCB layout n High impedance on receiver inputs when power is off n Programmable edge trigger on clock n Footprint compatible with DS92LV1210 n Small 28-lead SSOP package-MSA Block Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. DS101387-1 November 2000 DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery © 2000 National Semiconductor Corporation DS101387 www.national.com

Resynchronization(Continued) recommendation is to provide a feedback loop using the LOCK pin itself to control the sync request of the Serializer (SYNC1 or SYNC2). Dual SYNC pins are provided for mul- tiple control in a multi-drop application. Sending sync pat- terns for resynchronization is desirable when lock times within a specific time are critical. However, the Deserializer can lock to random data, which is discussed in the next section. Random Lock Initialization and Resynchronization The initialization and resynchronization methods described in their respective sections are the fastest ways to establish the link between the Serializer and Deserializer. However, the DS92LV1212A can attain lock to a data stream without requiring the Serializer to send special SYNC patterns. This allows the DS92LV1212A to operate in “open-loop” applica- tions. Equally important is the Deserializer’s ability to support hot insertion into a running backplane. In the open loop or hot insertion case, we assume the data stream is essentially random. Therefore, because lock time varies due to data stream characteristics, we cannot possibly predict exact lock time. The primary constraint on “random” lock time is the initial phase relation between the incoming data and the REFCLK when the Deserializer powers up. As described in the next paragraph, the data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the Deserializer could enter “false lock” - falsely recognizing the data pattern as the clocking bits. We refer to such a pattern as a repetitive multi-transition, RMT. This occurs when more than one Low-High transition takes place in a clock cycle over multiple cycles. This occurs when any bit, except DIN 9, is held at a low state and the adjacent bit is held high, creating a 0-1 transition. In the worst case, the Deserializer could become locked to the data pattern rather than the clock. Circuitry within the DS92LV1212A can detect that the possibility of “false lock” exists. The circuitry accomplishes this by detect- ing more than one potential position for clocking bits. Upon detection, the circuitry will prevent the LOCK output from becoming active until the potential “false lock” pattern changes. The false lock detect circuitry expects the data will eventually change, causing the Deserializer to lose lock to the data pattern and then continue searching for clock bits in the serial data stream. Graphical representations of RMT are shown on the following page. Please note that RMT only applies to bits DIN0-DIN8. Powerdown When no data transfer occurs, you can use the Powerdown state. The Serializer and Deserializer use the Powerdown state, a low power sleep mode, to reduce power consump- tion. The Deserializer enters Powerdown when you drive PWRDN and REN low. The Serializer enters Powerdown when you drive PWRDN low. In Powerdown, the PLL stops and the outputs enterTRI-STATE, which disables load cur- rent and reduces supply current to the milliampere range. To exit Powerdown, you must drive the PWRDN pin high. Before valid data exchanges between the Serializer and Deserializer, you must reinitialize and resynchronize the de- vices to each other. Initialization of the Serializer takes 510 TCLK cycles. The Deserializer will initialize and assert LOCK high until lock to the Bus LVDS clock occurs. TRI-STATE The Serializer enters TRI-STATE when the DEN pin is driven low. This puts both driver output pins (DO+ and DO−) into TRI-STATE. When you drive DEN high, the Serializer returns to the previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When you drive the REN pin low, the Deserializer enters TRI-STATE. Consequently, the receiver output pins (ROUT0–ROUT9) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the state of the PLL. DS92LV1212A www.national.com3

DS92LV1021TMSA Serializer MSA28 DS92LV1212AMSA Deserializer MSA28 DS101387-23 DIN0 Held Low-DIN1 Held High Creates an RMT Pattern DS101387-24 DIN4 Held Low-DIN5 Held High Creates an RMT Pattern DS101387-25 DIN8 Held Low-DIN9 Held High Creates an RMT Pattern DS92LV1212A www.national.com 4

Absolute Maximum Ratings(Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC ) −0.3V to +4V CMOS/TTL Input Voltage −0.3V to (V CC +0.3V) CMOS/TTL Output Voltage −0.3V to (V CC +0.3V) Bus LVDS Receiver Input Voltage −0.3V to +3.9V Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature (Soldering, 4 seconds) +260˚C Maximum Package Power Dissipation Capacity @ 25˚C Package: 28L SSOP 1.27 W Package Derating: 28L SSOP 10.3mW/˚C above +25˚C ESD Rating (HBM) >2kV Recommended Operating Conditions Min Nom Max Units Supply Voltage (VCC ) 3.0 3.3 3.6 V Operating Free Air Temperature (TA) −40 +25 +85 ˚C Receiver Input Range 0 2.4 V Supply Noise Voltage (VCC ) 100 mV P-P

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply to pins ROUT, RCLK, LOCK = outputs) VIH High Level Input Voltage 2.0 V CC V VIL Low Level Input Voltage GND 0.8 V VCL Input Clamp Voltage I CL = −18 mA −0.62 −1.5 V IIN Input Current V IN = 0V or 3.6V −10 ±2 +15 µA VOH High Level Output Voltage IOH = −9 mA 2.1 2.93 V CC V VOL Low Level Output Voltage I OL = 9 mA GND 0.33 0.5 V IOS Output Short Circuit Current VOUT = 0V −15 −38 −85 mA IOZ TRI-STATE Output Current PWRDN or REN = 0.8V, V OUT =0 Vo rV C C −10 ±0.4 +10 µA DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−) VTH Differential Threshold High Voltage VCM = +1.1V +6 +50 mV VTL Differential Threshold Low Voltage −50 −12 mV I IN Input Current V IN = +2.4V, VCC = 3.6V or 0V −10 ±1 +15 µA VIN = 0V, VCC = 3.6V or 0V −10 ±0.05 +10 µA DESERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC) I CCR Deserializer Supply Current CL = 15 pF f = 40 MHz 58 75 mA Worst Case Figure 1 f = 16 MHz 30 45 mA ICCXR Deserializer Supply Current Powerdown PWRDN = 0.8V, REN = 0.8V 0.36 1.0 mA Deserializer Timing Requirements for REFCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units tRFCP REFCLK Period 25 T 62.5 ns tRFDC REFCLK Duty Cycle 50 % fRef REFCLK Frequency 0.95/t RCP tRCP 1.05/tRCP tRFTT REFCLK Transition Time 3 6 ns DS92LV1212A www.national.com5

Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tRCP Receiver out Clock Period Figure 3 tRCP =tTCP RCLK 25 62.5 ns tCLH CMOS/TTL Low-to-High Transition Time C L=1 5p F Figure 2 Rout(0-9), 1.2 4 ns tCHL CMOS/TTL High-to-Low Transition Time LOCK, RCLK 1.1 4 ns Room Temp tROS ROUT (0-9) Setup Data to RCLK Figure 5 RCLK 0.4*tRCP 0.5*tRCP ns tROH ROUT (0-9) Hold Data to RCLK −0.4*tRCP −0.5*tRCP ns tRDC RCLK Duty Cycle 45 50 55 % tHZR HIGH to TRI-STATE Delay Figure 6 Rout(0-9), LOCK 4.2+0.5*tRCP 10+tRCP ns tLZR LOW to TRI-STATE Delay 4.5+0.5*t RCP 10+tRCP ns tZHR TRI-STATE to HIGH Delay 6+0.5*t RCP 12+tRCP ns tZLR TRI-STATE to LOW Delay 6.0+0.5*t RCP 12+tRCP ns tDSR1 Deserializer PLL Lock Time from PWRDWN (with SYNCPAT) Figure 7 Figure 8 (Note 4) 16MHz 41 0 µ s 40MHz 1.31 3 µs tDSR2 Deserializer PLL Lock time from SYNCPAT 16MHz 1.2 5 µs 40MHz 0.47 1 µs tZHLK TRI-STATE to HIGH Delay (Power-up) LOCK 4.62 12 ns tRNM Deserializer Noise MarginFigure 9 (Note 5)

16 MHz 900 1100 ps

40 MHz 450 730 ps

Note 1:“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2:Typical values are given for VCC = 3.3V and TA = +25˚C. Note 3:Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD,ΔVOD, VTH and VTL which are differential voltages. Note 4:For the purpose of specifying Deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions of the incoming data stream (SYNCPATs). It is recommended that the Deserializer be initialized using either tDSR1 timing or tDSR2 timing. tDSR1 is thetime required for the Deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device beforeinitiating either condition. tDSR2 is the time required to indicate lock for the powered-up and enabled Deserializer when the input (RI+ and RI-) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). Note 5:tRNM is a measure of how much phase noise (jitter) the Deserializer can tolerate in the incoming data stream before bit errors occur. DS92LV1212A www.national.com 6

FIGURE 12. Using tDJIT and tRNM to Generate an Eye Pattern Mask and Validate SIgnal Quality

Deserializer Pin Description Pin Name I/O No. Description ROUT O 15–19, 24–28 Data Output.±9 mA CMOS level outputs. RCLK_R/F I 2 Recovered Clock Rising/Falling strobe select. TTL level input. Selects RCLK active edge for strobing of ROUT data. High selects rising edge. Low selects falling edge. RI+ I 5 + Serial Data Input. Non-inverting Bus LVDS differential input. RI− I 6 − Serial Data Input. Inverting Bus LVDS differential input. PWRDN I 7 Powerdown. TTL level input. PWRDN driven low shuts down the PLL. LOCK O 10 LOCK goes low when the Deserializer PLL locks onto the embedded clock edge. CMOS level output. Totem pole output structure, does not directly support wire OR connection. RCLK O 9 Recovered Clock. Parallel data rate clock recovered from embedded clock. Used to strobe ROUT, CMOS level output. REN I 8 Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9, LOCK and RCLK when driven low. DVCC I 21, 23 Digital Circuit power supply. DGND I 14, 20, 22 Digital Circuit ground. AVCC I 4, 11 Analog power supply (PLL and Analog Circuits). AGND I 1, 12, 13 Analog ground (PLL and Analog Circuits). REFCLK I 3 Use this pin to supply a REFCLK signal for the internal PLL frequency. DS92LV1212AMSA - Deserializer DS101387-19 DS92LV1212A www.national.com13

PWRDN REN ROUT [0:9] LOCK RCLK HH Z H Z H H Active L Active LX Z Z Z H L Z Active Z 1) LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream. 2) RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined by RCLK_R/F. 3) ROUT and RCLK are TRI-STATED when LOCK is asserted High. DS92LV1212A www.national.com 14

Physical Dimensionsinches (millimeters) unless otherwise noted LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com Note: Package Dimensions are in millimeters only. Order Number DS92LV1212AMSA DS92LV1212A 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.