DS92LV1021A_14 TI1 | Alldatasheet

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www.ti.com SNLS151G –OCTOBER 2002–REVISED APRIL 2013 DS92LV1021A16-40MHz10BitBusLVDSSerializer Check forSamples: DS92LV1021A 1FEATURES DESCRIPTION The DS92LV1021A transformsa 10-bitwide parallel 2• SpecifiedTransitionEvery Data TransferCycle LVCMOS/LVTTL data bus intoa singlehigh speed• SingleDifferentialPairEliminatesMulti- Bus LVDS serialdata stream withembedded clock.Channel Skew The DS92LV1021A can transmit data over

  • Flow-Through PinoutforEasy PCB Layout backplanesor cable.The singledifferentialpairdata path makes PCB design easier.In addition,the• 400 Mbps SerialBus LVDS Bandwidth (at40 reducedcable,PCB tracecount,and connectorsizeMHz Clock) tremendouslyreducecost.Sinceone outputtransmits• 10-bitParallelInterfacefor1 Byte Data Plus 2 bothclockand databitsserially,iteliminatesclock-to- ControlBits data and data-to-dataskew. The powerdown pin saves power by reducingsupplycurrentwhen the• Programmable Edge Triggeron Clock device is not being used. Upon power up of the• Bus LVDS SerialOutput Rated for27Ω Load Serializer,you can choose toactivatesynchronization• Small 28-Lead SSOP Package-DB mode or use one of TI’s Deserializersin the synchronization-to-random-datafeature.By usingthe synchronizationmode, the Deserializerwillestablish lock to a signalwithinspecifiedlock times.In addition,theembedded clockspecifiesa transitionon the bus every 12-bit cycle. This eliminates transmissionerrorsdue tochargedcableconditions. Furthermore,you may put the DS92LV1021A output pins intoTRI-STATE to achievea high impedance state.The PLL can lockto frequenciesbetween 16 MHz and 40 MHz. Block Diagram Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2002–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS151G –OCTOBER 2002–REVISED APRIL 2013 www.ti.com FunctionalDescription The DS92LV1021A isan upgradetotheDS92LV1021. The DS92LV1021A no longerhas a power-upsequence requirement.Likethe DS92LV1021, the DS92LV1021A isa 10-bitSerializerdesignedto transmitdata over a differentialbackplaneat clockspeeds from 16 to 40MHz. Itmay alsobe used to drivedata over Unshielded TwistedPair(UTP) cable. The DS92LV1021A can be used withany ofTI’s 10-bitBLVDS Deserializers(DS92LV1212A forexample)and has threeactivestatesofoperation:Initialization,Data Transfer,and Resynchronization;and two passivestates: Powerdown and TRI-STATE. The followingsectionsdescribeeach activeand passivestate. Initialization Beforedata can be transferred,the Serializermust be initialized.Initializationrefersto synchronizationof the Serializer’s PLL toa localclock. When VCC isappliedtotheSerializer,theoutputsareheldinTRI-STATE and internalcircuitryisdisabledby on- chippower-oncircuitry.When VCC reachesVCC OK (2.5V)theSerializer’s PLL beginslockingtothelocalclock. The localclockisthetransmitclock,TCLK, providedby thesourceASIC orotherdevice. Once thePLL lockstothelocalclock,theSerializerisreadytosend dataorSYNC patterns,dependingon the levelsoftheSYNC1 and SYNC2 inputs.The SYNC patterniscomposed ofsixones and sixzerosswitchingat theinputclockrate. ControloftheSYNC pinsislefttotheuser.One recommendationisa directfeedbackloopfromtheLOCK pin. Under allcircumstances,theSerializerstopssendingSYNC patternsafterbothSYNC inputsreturnlow. Data Transfer Afterinitialization,theSerializerinputsDIN0–DIN9 may be used toinputdatatotheSerializer.Data isclocked intotheSerializerby theTCLK input.The edge ofTCLK used tostrobethedataisselectableviatheTCLK_R/ F pin.TCLK_R/ F highselectsthe risingedge forclockingdata and low selectsthe fallingedge. Ifeitherof the SYNC inputsishighfor5*TCLK cycles,thedataatDIN0-DIN9 isignoredregardlessoftheclockedge. A startbitand a stopbit,appended internally,framethedatabitsintheregister.The startbitisalwayshighand thestopbitisalwayslow.The startand stopbitsfunctionas theembedded clockbitsintheserialstream. Serializeddataand clockbits(10+2bits)aretransmittedfromtheserialdataoutput(DO ±)at12 timestheTCLK frequency.For example,ifTCLK is40 MHz, theserialrateis40 × 12 = 480 Mega bitspersecond.Sinceonly10 bitsare from inputdata,theserial“payload” rateistentimestheTCLK frequency.For instance,ifTCLK = 40 MHz, thepayloaddatarateis40 × 10 = 400 Mbps. TCLK isprovidedby thedatasourceand must be inthe rangeof16 MHz to40 MHz nominal. The outputs(DO ±) can drivea backplaneor a point-to-pointconnection.The outputstransmitdata when the enablepin(DEN) ishigh,PWRDN ishigh,and SYNC1 and SYNC2 arelow.The DEN pinmay be used toTRI- STATE theoutputswhen drivenlow.

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www.ti.com SNLS151G –OCTOBER 2002–REVISED APRIL 2013 IdealCrossing Point The idealcrossingpointisthebestcase startand stoppointfora normalizedbit.Each idealcrossingpointis foundby dividingtheclockperiodby twelve--twoclockbitsplustendatabits.Forexample,a 40 MHz clockhas a periodof 25ns. The 25ns dividedby 12 bitsis approximately2.08ns.This means thateach bitwidthis approximately2.08ns,and theidealcrossingpointsoccurevery2.08ns.For a graphicalrepresentation,please see Figure9. Resynchronization The DeserializerLOCK pindrivenlow indicatesthattheDeserializerPLL islockedtotheembedded clockedge. IftheDeserializerloseslock,theLOCK outputwillgo highand theoutputs(includingRCLK) willbe TRI-STATE. The LOCK pinmust be monitoredby thesystem todetecta lossofsynchronization,and thesystem must decide ifitisnecessarytopulsetheSerializerSYNC1 or SYNC2 pintoresynchronize.There are multipleapproaches possible.One recommendation isto providea feedbackloop usingthe LOCK pin itselfto controlthe sync requestoftheSerializer(SYNC1 or SYNC2). At thetimeofpublication,otherthantheDS92LV1210, allother DeserializersfromTIhave random lockcapability.Thisfeaturedoes notrequirethesystem usertosend SYNC patternsupon lossoflock.However,locktimescan onlybe specifiedwithtransmissionofSYNC patterns.Dual SYNC pinsareprovidedformultiplecontrolina multi-dropapplication. Powerdown The Powerdown stateisa low power sleepmode thattheSerializerand Deserializermay use toreducepower when no data isbeingtransferred.The deviceentersPowerdown when thePWRDN pinisdrivenlow on the Serializer.InPowerdown, thePLL stopsand theoutputsgo intoTRI-STATE, disablingloadcurrentand reducing supplycurrentintothemilliamprange.To exitPowerdown, PWRDN must be drivenhigh. Both the Serializerand Deserializermust reinitializeand resynchronizebeforedata can be transferred.The Deserializerwillinitializeand assertLOCK highuntilitislockedtotheBus LVDS clock. TRI-STATE For theSerializer,TRI-STATE isenteredwhen theDEN pinisdrivenlow.ThiswillTRI-STATE bothdriveroutput pins(DO+ and DO −).When DEN isdrivenhigh,theserializerwillreturntothepreviousstateas longas allother controlpinsremainstatic(SYNC1, SYNC2, PWRDN, TCLK_R/ F). These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) SupplyVoltage(VCC ) −0.3Vto+4V CMOS/TTL InputVoltage −0.3Vto(VCC +0.3V) CMOS/TTL OutputVoltage −0.3Vto(VCC +0.3V) Bus LVDS ReceiverInputVoltage −0.3Vto+3.9V Bus LVDS DriverOutputVoltage −0.3Vto+3.9V Bus LVDS OutputShortCircuit Duration Continuous JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature(Soldering,4 seconds) +260°C Maximum Package Power DissipationCapacity@ 25°C Package: 28L SSOP 1.27W Package Derating:28L SSOP 10.2mW/ °C above +25°C ESD Rating(HBM) (3) >2.0kV (1) “AbsoluteMaximum Ratings”arethosevaluesbeyond whichthesafetyofthedevicecannotbe specified.They arenotmeant toimply thatthedevicesshouldbe operatedattheselimits.The tableof“ElectricalCharacteristics”specifiesconditionsofdeviceoperation. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. (3) Witha limitedEngineeringsample size,ESD (HBM) testingpassed 2.5kV Copyright© 2002–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS92LV1021A

SNLS151G –OCTOBER 2002–REVISED APRIL 2013 www.ti.com Recommended OperatingConditions Min Nom Max Units SupplyVoltage(VCC ) 3.0 3.3 3.6 V OperatingFreeAirTemperature(TA) −40 +25 +85 °C SupplyNoiseVoltage(VCC ) 100 mV P-P ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units SERIALIZER CMOS/TTL DC SPECIFICATIONS (applytoDIN0-9,TCLK, PWRDN, TCLK_R/ F,SYNC1, SYNC2, DEN) VIH HighLevelInputVoltage 2.0 VCC V VIL Low LevelInputVoltage GND 0.8 V VCL InputClamp Voltage ICL = −18 mA −1.5 V IIN InputCurrent VIN = 0V or3.6V −10 ±2 +10 μA SERIALIZER Bus LVDS DC SPECIFICATIONS (applytopinsDO+ and DO −) VOD OutputDifferentialVoltage 200 270 mV(DO+)–(DO −) ΔVOD OutputDifferentialVoltage 35 mVRL = 27ΩUnbalance VOS OffsetVoltage 0.78 1.1 1.3 V ΔVOS OffsetVoltageUnbalance 35 mV IOS OutputShortCircuitCurrent D0 = 0V,DIN = High,PWRDN and DEN = 2.4V −30 −40 mA IOZ TRI-STATE OutputCurrent PWRDN orDEN = 0.8V,DO = 0V orVCC −10 ±1 +10 μA IOX Power-OffOutputCurrent VCC = 0V,DO = 0V orVCC −20 ±1 +20 μA SERIALIZER SUPPLY CURRENT (applytopinsDVCC and AVCC) ICCD f= 40 MHz 40 55 mAWorstCase SerializerSupply RL = 27Ω,Figure1Current f= 16 MHz 28 35 mA ICCXD SerializerSupplyCurrent PWRDN = 0.8V 88 300 μAPowerdown (1) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages. SerializerTiming Requirements forTCLK Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units tTCP TransmitClockPeriod 25 T 62.5 ns tTCIH TransmitClockHighTime 0.4T 0.5T 0.6T ns tTCIL TransmitClockLow Time 0.4T 0.5T 0.6T ns tCLKT TCLK InputTransitionTime 3 6 ns tJIT TCLK InputJitter ps150 (RMS) (1) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages.

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www.ti.com SNLS151G –OCTOBER 2002–REVISED APRIL 2013 SerializerSwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units tLLHT Bus LVDS Low-to-High 0.31 0.75 nsTransitionTime R L = 27Ω,Figure2, C L=10pF toGNDtLHLT Bus LVDS High-to-Low 0.30 0.75 nsTransitionTime tDIS DIN (0-9)Setupto 0 nsSee Figure4,TCLK R L = 27Ω, tDIH DIN (0-9)Holdfrom C L=10pF toGND 4.0 nsTCLK tHZD DO ± HIGH to 3.5 10 nsTRI-STATE Delay tLZD DO ± LOW toTRI- 2.9 10 nsSee Figure5 ,(3),STATE Delay R L = 27Ω, tZHD DO ± TRI-STATE to C L=10pF toGND 2.5 10 nsHIGH Delay tZLD DO ± TRI-STATE to 2.7 10 nsLOW Delay tSPW SYNC PulseWidth See Figure7, 5*tTCP nsR L = 27Ω tPLD SerializerPLL Lock See Figure6, 510*tTCP 2049*tTCP nsTime R L = 27Ω tSD SerializerDelay See Figure8 ,R L = 27Ω tTCP +1.0 tTCP + 2.0 tTCP +4.0 ns tBIT Bus LVDS BitWidth R L = 27Ω, tCLK /12 nsC L=10pF toGND f= 40 MHz −320 −110 150 psR L = 27Ω,tDJIT DeterministicJitter C L=10pF toGND, (4) f= 16 MHz −800 −160 380 ps (1) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C. (2) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages. (3) Due toTRI-STATE oftheSerializer,theDeserializerwilllosePLL lockand have toresynchronizebeforedatatransfer. (4) tDJIT specificationsarespecifiedby designusingstatisticalanalysis. AC Timing Diagrams and TestCircuits Figure1. “Worst Case ” SerializerICC TestPattern Figure2. SerializerBus LVDS Output Load and TransitionTimes Copyright© 2002–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS92LV1021A

SNLS151G –OCTOBER 2002–REVISED APRIL 2013 www.ti.com Figure3. SerializerInputClock TransitionTime Timingshown forTCLK_R/ F = LOW Figure4. SerializerSetup/HoldTimes Figure5. SerializerTRI-STATE TestCircuitand Timing

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www.ti.com SNLS151G –OCTOBER 2002–REVISED APRIL 2013 Figure6. SerializerPLL Lock Time,and PWRDN TRI-STATE Delays Figure7. SYNC Timing Delays Figure8. SerializerDelay Copyright© 2002–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS92LV1021A

SNLS151G –OCTOBER 2002–REVISED APRIL 2013 www.ti.com Foran explanationoftheIdealCrossingPoint,pleasesee theApplicationInformationSection. Figure9. SerializerDeterministicJitterand IdealCrossing Point

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www.ti.com SNLS151G –OCTOBER 2002–REVISED APRIL 2013

APPLICATION INFORMATION

DIFFERENCES BETWEEN THE DS92LV1021A AND THE DS92LV1021 The DS92LV1021A isan enhanced versionoftheDS92LV1021. The followingenhancements are providedby theDS92LV1021A:

  • TCLK may be appliedbeforepower
  • TCLK may be halted
  • Slowertypicaledge rateshelptoreducereflections
  • PWRDN pinincludesan internalweak pulldown device Likethe DS92LV1021, the DS92LV1021A isa 10-bitSerializerdesignedto transmitdata over a differential backplaneatclockspeeds from 16 to40MHz. Itmay alsobe used todrivedataoverUnshieldedTwistedPair (UTP) cable. USING THE DS92LV1021A The Serializerisan easy touse transmitterthatsends 10 bitsofparallelTTL dataovera serialBus LVDS linkup to400 Mbps. Serializationoftheinputdataisaccomplishedusingan onboardPLL whichembeds two clockbits withthedata. POWER CONSIDERATIONS An allCMOS designoftheSerializermakes itan inherentlylow power device.Additionally,theconstantcurrent sourcenatureoftheBus LVDS outputsminimizetheslopeofthespeed vs.ICC curveofCMOS designs. DIGITAL AND ANALOG POWER PINS Digitaland Analog power supplypinsshouldbe atthesame voltagelevels.The usershouldverifythatvoltage levelsatthedigitaland analogsupplypinsare atthesame voltagelevelsafterboard layoutand afterbypass capacitorsareadded. HOT INSERTION AllBus LVDS devicesare hot pluggableifyou followa few rules.When inserting,ensure the Ground pin(s) makes contactfirst,then the VCC pin(s),and then the I/O pins.When removing,the I/O pins should be unpluggedfirst,thentheVCC, thentheGround. TRANSMITTING DATA Once theSerializerand Deserializerare powered up and runningtheymust be phase lockedtoeach otherin orderto transmitdata.Phase lockingcan be accomplishedby the SerializersendingSYNC patternsto the Deserializer,or by usingthe Deserializer’s random lockcapability.SYNC patternsare sentby the Serializer whenever SYNC1 or SYNC2 inputsare heldhigh.The LOCK outputof the Deserializerishighwhenever the Deserializerisnot locked.Connectingthe LOCK outputof the Deserializerto one of the SYNC inputsof the Serializerwillspecifiythatenough SYNC patternsaresenttoachieveDeserializerlock. While the DeserializerLOCK outputislow,data at the Deserializeroutputs(ROUT0-9) isvalidexceptforthe specificcase oflossoflockduringtransmission. RECOVERING FROM LOCK LOSS In the case where the Serializerloseslockduringdata transmissionup to threecyclesof data thatwas previouslyreceivedcan be invalid.Thisisdue tothedelayinthelockdetectioncircuit.The lockdetectcircuit requiresthatinvalidclockinformationbe received4 times in a row to indicatelossof lock.Since clock informationhas been lostitispossiblethatdatawas alsolostduringthesecycles.When theDeserializerLOCK pingoes low,datafromatleastthepreviousthreecyclesshouldbe resentupon regaininglock. Lock can be regainedattheDeserializerby causingtheSerializertoresendSYNC patternsas describedabove. Copyright© 2002–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS92LV1021A

SNLS151G –OCTOBER 2002–REVISED APRIL 2013 www.ti.com PCB CONSIDERATIONS The Bus LVDS devicesSerializerand Deserializershouldbe placedas closetotheedge connectoras possible. InmultipleDeserializerapplications,thedistancefromtheDeserializertotheslotconnectorappearsas a stubto theSerializerdrivingthebackplanetraces.Longerstubslowertheimpedance ofthebus increasingtheloadon theSerializerand lowersthresholdmarginattheDeserializers.Deserializerdevicesshouldbe placedno more than1 inchfromtheslotconnector. TRANSMISSION MEDIA The Serializerand Deserializeraredesignedfordatatransmissionovera multi-dropbus.Multi-dropbuses use a singleSerializerand multipleDeserializerdevices.SincetheSerializercan be drivingfromany pointon thebus, thebus must be terminatedatbothends.For example,a 100 Ohm differentialbus must be terminatedateach end with100 Ohms loweringtheDC impedance thattheSerializermust driveto50 Ohms. Thisloadisfurther loweredby the additionof multipleDeserializers.Adding up to 20 Deserializersto the bus (dependingupon spacing)willlowerthe totalloadto about 27 Ohms (54 Ohm bus).The SerializerisdesignedforDC loads between 27 and 100 Ohms. The Serializerand Deserializercan alsobe used inpoint-to-pointconfigurationof a backplane,PCB traceor througha twistedpaircable.Inpoint-to-pointconfigurationsthetransmissionmedia need onlybe terminatedat thereceiverend.Inthepoint-to-pointconfigurationthepotentialofoffsettingtheground levelsoftheSerializer vs.theDeserializermust be considered.Bus LVDS providesa plus/minus one voltcommon mode rangeatthe receiverinputs. PIN DIAGRAM Figure10. DS92LV1021AMSA -Serializer

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www.ti.com SNLS151G –OCTOBER 2002–REVISED APRIL 2013 SerializerPin Description Pin Name I/O No. Description DIN I 3–12 Data Input.TTL levelsinputs.Data on thesepinsareloadedintoa 10-bit inputregister. TCLK_R/ F I 13 TransmitClockRising/Fallingstrobeselect.TTL levelinput.SelectsTCLK activeedge forstrobingofDIN data.Highselectsrisingedge.Low selects fallingedge. DO+ O 22 + SerialData Output.Non-invertingBus LVDS differentialoutput. DO − O 21 − SerialData Output.InvertingBus LVDS differentialoutput. DEN I 19 SerialData OutputEnable.TTL levelinput.A low,putstheBus LVDS outputsinTRI-STATE. PWRDN I 24 Powerdown. TTL levelinput.PWRDN drivenlowshutsdown thePLL and TRI-STATEs theoutputsputtingthedeviceintoa lowpower sleepmode. Thispinhas an internalweak pulldown. TCLK I 14 TransmitClock.TTL levelinput.Inputfor16 MHz –40 MHz (nominal)system clock. SYNC I 1,2 AssertionofSYNC (high)foratleast1024 synchronizationsymbolstobe transmittedon theBus LVDS serialoutput.Synchronizationsymbols continuetobe sentifSYNC continuesasserted.TTL levelinput.The two SYNC pinsareORed. DVCC I 27,28 DigitalCircuitpower supply.DVCC voltagelevelshouldbe identicaltothe AVCC voltagelevel. DGND I 15,16 DigitalCircuitground.Ground potentialshouldbe thesame as AGND. AVCC I 17,26 Analogpower supply(PLL and AnalogCircuits).AVCC voltagelevelshould be identicaltotheDVCC voltagelevel. AGND I 18,25,20,23 Analogground(PLL and AnalogCircuits).Ground potentialshouldbe the same as DGND. TruthTable(1) DIN (0–9) TCLK_R/ F TCLK SYNC1/SYNC2 DEN PWRDN DO+ DO − X X X X X 0 Z Z X X X X 0 1 Z Z X X SYSTEM CLK 1∼ 1 1 SYNC PTRN SYNC PTRN* DATA 1 0 1 1 DATA (0–9) DATA (0–9)* DATA 0 0 1 1 DATA (0–9) DATA (0–9)* RI RI− RCLK_R/ F REFCLK REN PWRDN RCLK LOCK X X X X X 0 Z Z X X X X 0** 1 Z Z SYNC PTRN SYNC PTRN* X SYSTEM CLK 1 1 CLK 1† DATA (0–9) DATA (0–9)* 1 SYSTEM CLK 1 1 0 DATA (0–9) DATA (0–9)* 0 SYSTEM CLK 1 1 0 (1) ∼ Pulse5-bits *Inverted †Must be 1 beforeSYNC PTRN starts **Devicemust be lockedfirst Copyright© 2002–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS92LV1021A

SNLS151G –OCTOBER 2002–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionF (April2013)toRevisionG Page

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www.ti.com 13-Sep-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS92LV1021AMSA NRND SSOP DB 28 47 TBD Call TI Call TI -40 to 85 DS92LV1021A MSA >B DS92LV1021AMSA/NOPB ACTIVE SSOP DB 28 47 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 DS92LV1021A MSA >B DS92LV1021AMSAX NRND SSOP DB 28 2000 TBD Call TI Call TI -40 to 85 DS92LV1021A MSA >B DS92LV1021AMSAX/NOPB ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 DS92LV1021A MSA >B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 13-Sep-2014 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant DS92LV1021AMSAX/NOP B PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV1021AMSAX SSOP DB 28 2000 367.0 367.0 35.0 DS92LV1021AMSAX/NOP B SSOP DB 28 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 Pack Materials-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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