DS92LV1021

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DS92LV1021,DS92LV1210 www.ti.com SNLS024C –MARCH 1999–REVISED APRIL 2013 DS92LV1021andDS92LV121016-40MHz10BitBusLVDSSerializerandDeserializer Check forSamples: DS92LV1021 ,DS92LV1210 1FEATURES DESCRIPTION The DS92LV1021 transformsa 10-bitwide parallel 2• Ensured TransitionEvery Data TransferCycle CMOS/TTL data bus intoa singlehigh speed Bus• SingleDifferentialPairEliminatesMulti- LVDS serialdata stream withembedded clock.Thechannel Skew DS92LV1210 receivesthe Bus LVDS serialdata

• Flow-throughPinoutforEasy PCB Layout stream and transformsitback intoa 10-bitwide paralleldata bus and separates clock. The• 400 Mbps SerialBus LVDS Bandwidth (at40 DS92LV1021 may transmitdata over heavilyloadedMHz clock) backplanes or 10 meters of cable.The reduced• 10-bitParallelInterfacefor1 Byte Data Plus 2 cable,PCB tracecount and connectorsize saves ControlBits costand makes PCB designlayouteasier.Clock-to- dataand data-to-dataskew are eliminatedsinceone• SynchronizationMode and LOCK Indicator output willtransmitboth clock and alldata bits• Programmable Edge Triggeron Clock serially.The powerdown pinisused to save power,• High Impedance on ReceiverInputsWhen by reducingsupplycurrentwhen eitherdeviceisnot Power isoff in use. The Serializerhas a synchronizationmode thatshouldbe activatedupon power-upofthedevice.• Bus LVDS SerialOutput Rated for27Ω Load The Deserializerwillestablishlock to thissignal• Small 28-leadSSOP Package (DB) within1024 cycles,and willflagLock status.The embedded clock ensures a transitionon the bus every12-bitcycle;eliminatingtransmissionerrorsdue tochargedcableconditions.The DS92LV1021 output pins may be TRI-STATE to achieve a high impedance state.The PLL can lockto frequencies between 16 MHz and 40 MHz. Block Diagram Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1999–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

DS92LV1021,DS92LV1210 SNLS024C –MARCH 1999–REVISED APRIL 2013 www.ti.com Figure1. Application FunctionalDescription The DS92LV1021 and DS92LV1210 isa 10-bitSerializer/Deserializerchipsetdesignedtotransmitdataovera heavilyloadeddifferentialbackplanesatclockspeeds from16 to40MHz. Itmay alsobe used todrivedataover UnshieldedTwistedPair(UTP) cable. The chipsethas threeactivestatesof operation:Initialization,Data Transfer,and Resynchronization;and two passivestates:Powerdown and TRI-STATE. The followingsectionsdescribeeach operationand passivestate. Initialization Beforedata can be transferredboth devicesmust be initialized.Initializationrefersto synchronizationof the Serializerand the DeserializerPLL's to localclocks that may be the same or separate.Afterward, synchronizationofDeserializertoSerializeroccursas thesecond stepofinitialization. Step 1:When VCC isappliedtobothSerializerand/orDeserializer,therespectiveoutputsareheldinTRI-STATE and internalcircuitryisdisabledby on-chippower-oncircuitry.When VCC reachesVCC OK (2.5V)thePLL ineach devicebeginslockingtoa localclock.For theSerializer,thelocalclockisthetransmitclock,TCLK, providedby the sourceASIC or otherdevice.For the Deserializer,the localclockisprovidedby an on-boardoscillatoror othersourceand appliedtotheREFCLK pin.AfterVCC OK isreachedthedevice'sPLL willlock. The Serializeroutputsare heldinTRI-STATE whilethePLL lockstotheTCLK. The Serializerisnow readyto send dataor SYNC patternsdependingon thelevelsoftheSYNC1 and SYNC2 inputs.The SYNC patternis composed ofsixones and sixzerosswitchingattheinputclockrate. The DeserializerLOCK outputwillremainhighwhileitsPLL islockingtothelocalclock-theREFCLK inputand thentoSYNC patternson theinput. Step2:The DeserializerPLL must synchronizetotheSerializertocompletetheinitialization.The transmissionof SYNC patternstotheDeserializerenablestheDeserializertolocktotheSerializersignal. Controlof the sync pinsisleftto the user.A feedbackloopbetween the LOCK pinisone recommendation. Anotheroptionisthatone orbothoftheSerializerSYNC inputsareassertedforatleast1024 cyclesofTCLK to initiatetransmissionofSYNC patterns.The Serializerwillcontinuetosend SYNC patternsaftertheminimum of 1024 ifeitheroftheSYNC inputsremainhigh. When the Deserializerdetectsedge transitionsat the Bus LVDS inputitwillattemptto lockto the embedded clockinformation.When theDeserializerlockstotheBus LVDS clock,theLOCK outputwillgo low.When LOCK islowtheDeserializeroutputsrepresentincomingBus LVDS data.

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DS92LV1021,DS92LV1210 www.ti.com SNLS024C –MARCH 1999–REVISED APRIL 2013 Data Transfer Afterinitialization,theSerializerinputsDIN0–DIN9 may be used toinputdatatotheSerializer.Data isclocked intotheSerializerby theTCLK input.The edge ofTCLK used tostrobeindataisselectableviatheTCLK_R/ F pin.TCLK_R/ F highselectsthe risingedge forclockingdata and low selectsthe fallingedge. Ifeitherof the SYNC inputsishighfor5*TCLK cyclesthedataatDIN 0-DIN9isignoredregardlessoftheclockedge. A startbitand a stopbit,appended internally,framethedatabitsintheregister.The startbitisalwayshighand thestopbitisalwayslow.The startand stopbitsfunctionas theembedded clockbitsintheserialstream. Serializeddataand clockbits(10+2 bits)aretransmittedfromtheserialdataoutput(DO) at12 timestheTCLK frequency.For example,ifTCLK is40 MHz, theserialrateis40 × 12 = 480 Mega bitspersecond.Sinceonly10 bitsare from inputdata,theserial“payload” rateis10 timestheTCLK frequency.For instance,ifTCLK = 40 MHz, thepayloaddatarateis40 × 10 = 400 Mbps. TCLK isprovidedby thedatasourceand must be inthe range16 MHz to40 MHz nominal. The outputs(DO ±) can drivea heavilyloadedbackplaneor a point-to-pointconnection.The outputstransmit datawhen theenablepin(DEN) ishigh,PWRDN = highand SYNC1 and SYNC2 arelow.The DEN pinmay be used toTRI-STATE theoutputswhen drivenlow. The LOCK pinon theDeserializerisdrivenlowwhen itissynchronizedwiththeSerializer.The Deserializerlocks to the embedded clockand uses itto recoverthe serializeddata.ROUT data isvalidwhen LOCK islow. OtherwiseROUT0 –ROUT9 isinvalid. RCLK pinisthereferencetodataon theROUT0-ROUT9 pins.The polarityoftheRCLK edge iscontrolledby theRCLK_R/ F input. ROUT(0-9),LOCK and RCLK outputswilldrivea minimum ofthreeCMOS inputgates(15pF load)with40 MHz clock. Resynchronization The DeserializerLOCK pindrivenlow indicatesthattheDeserializerPLL islockedtotheembedded clockedge. IftheDeserializerloseslock,theLOCK outputwillgo highand theoutputs(includingRCLK) willbe TRI-STATE. The LOCK pinmust be monitoredby thesystemtodetecta lossofsynchronizationand thesystemmust arrange to pulsethe SerializerSYNC1 or SYNC2 pinto resynchronize.There are multipleapproachespossible.One recommendation isto providea feedbackloop usingthe LOCK pin itselfto controlthe sync requestof the Serializer(SYNC1 or SYNC2). Otherwise,LOCK pinneeds tobe monitoredand when itisa high,thesystem needs toensurethatone orbothoftheSerializerSYNC inputsareaassertedforatleast1024 cyclesofTCLK. A minimum of1024 syncpatternsareneeded toresynchronize.DualSYNC pinsareprovidedformultiplecontrolin a multi-dropapplication. Powerdown The Powerdown stateisa low power sleepmode thattheSerializerand Deserializermay use toreducepower when thereisno datatobe transferred.Powerdown isenteredwhen PWRDN and REN are drivenlow on the Deserializer,and when thePWRDN isdrivenlow on theSerializer.InPowerdown, thePLL isstoppedand the outputsgo intoTRI-STATE, disablingloadcurrentand alsoreducingsupplycurrenttothemilliamprange.To exit Powerdown, PWRDN isdrivenhigh. Both the Serializerand Deserializermust reinitializeand resynchronizebefore data can be transferred. InitializationoftheSerializertakes1024 TCLK cycles.The Deserializerwillinitializeand assertLOCK highuntilit islockedtotheBus LVDS clock. TRI-STATE For theSerializer,TRI-STATE isenteredwhen theDEN pinisdrivenlow.ThiswillTRI-STATE bothdriveroutput pins(DO+ and DO −).When DEN isdrivenhightheserializerwillreturntothepreviousstateas longas allother controlpinsremainstatic(SYNC1, SYNC2, PWRDN, TCLK_R/ F). For theDeserializer,TRI-STATE isenteredwhen theREN pinisdrivenlow.ThiswillTRI-STATE thereceiver outputpins(ROUT0 –ROUT9), LOCK and RCLK. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS92LV1021 DS92LV1210

DS92LV1021,DS92LV1210 SNLS024C –MARCH 1999–REVISED APRIL 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings (1)(2) SupplyVoltage(VCC ) −0.3Vto+4V CMOS/TTL InputVoltage −0.3Vto(VCC +0.3V) CMOS/TTL OutputVoltage −0.3Vto(VCC +0.3V) Bus LVDS ReceiverInputVoltage −0.3Vto+3.9V Bus LVDS DriverOutputVoltage −0.3Vto+3.9V Bus LVDS OutputShortCircuit Duration Continuous JunctionTemperature +150°C StorageTemperature −65°C to+150°C Lead Temperature (Soldering,4 seconds) +260°C Maximum Package Power DissipationCapacity @ 25°C Package: 28L SSOP 1.27W Package Derating: 28L SSOP 10.2mW/ °C above +25°C ESD Rating(HBM) >5kV (1) “AbsoluteMaximum Ratings”arethosevaluesbeyond whichthesafetyofthedevicecannotbe verified.They arenotmeant toimply thatthedevicesshouldbe operatedattheselimits.The tableof“ElectricalCharacteristics”specifiesconditionsofdeviceoperation. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingConditions Min Nom Max Units SupplyVoltage(VCC ) 3.0 3.3 3.6 V OperatingFreeAir Temperature(TA) −40 +25 +85 °C ReceiverInputRange 0 2.4 V SupplyNoiseVoltage (VCC ) 100 mV P-P ElectricalCharacteristics(1) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ (2) Max Units SERIALIZER CMOS/TTL DC SPECIFICATIONS (applytoDIN0-9,TCLK, PWRDN, TCLK_R/ F,SYNC1, SYNC2, DEN) VIH HighLevelInputVoltage 2.0 VCC V VIL Low LevelInputVoltage GND 0.8 V VCL InputClamp Voltage ICL = −18 mA −1.5 V IIN InputCurrent VIN = 0V or3.6V −10 ±2 +10 μA DESERIALIZER CMOS/TTL DC SPECIFICATIONS (applytopinsPWRDN, RCLK_R/ F,REN, REFCLK = inputs;applytopinsROUT, RCLK, LOCK = outputs) VIH HighLevelInputVoltage 2.0 VCC V VIL Low LevelInputVoltage GND 0.8 V VCL InputClamp Voltage ICL = −18 mA −0.62 −1.5 V IIN InputCurrent VIN = 0V or3.6V −10 ±1 +10 μA VOH HighLevelOutputVoltage IOH = −9 mA 2.1 2.93 VCC V VOL Low LevelOutputVoltage IOL = 9 mA GND 0.33 0.6 V IOS OutputShortCircuitCurrent VOUT = 0V −15 −38 −85 mA (1) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages. (2) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C.

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DS92LV1021,DS92LV1210 www.ti.com SNLS024C –MARCH 1999–REVISED APRIL 2013 ElectricalCharacteristics(1)(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ (2) Max Units IOZ TRI-STATE OutputCurrent PWRDN orREN = 0.8V,VOUT = 0V orVCC −10 ±0.4 +10 μA SERIALIZER Bus LVDS DC SPECIFICATIONS (applytopinsDO+ and DO −) VOD OutputDifferentialVoltage RL = 27Ω 200 270 mV(DO+)–(DO −) ΔVOD OutputDifferentialVoltageUnbalance 35 mV VOS OffsetVoltage 0.78 1.1 1.3 V ΔVOS OffsetVoltageUnbalance 35 mV IOS OutputShortCircuitCurrent D0 = 0V,DIN = High,PWRDN and DEN = −10 −15 mA2.4V IOZ TRI-STATE OutputCurrent PWRDN orDEN = 0.8V,DO = 0V orVCC −10 ±1 +10 μA IOX Power-OffOutputCurrent VCC = 0V,DO = 0V orVCC −20 ±1 +20 μA DESERIALIZER Bus LVDS DC SPECIFICATIONS (applytopinsRI+ and RI−) VTH DifferentialThresholdHighVoltage VCM = +1.1V +19 +100 mV VTL DifferentialThresholdLow Voltage −100 −7 mV IIN InputCurrent VIN = +2.4V,VCC = 3.6Vor0V −10 ±1 +10 μA VIN = 0V,VCC = 3.6Vor0V −15 ±1 +15 μA SERIALIZER SUPPLY CURRENT (applytopinsDVCC and AVCC) ICCD SerializerSupplyCurrent RL = 27Ω f= 40 MHz 32 55 mA WorstCase See Figure2 f= 16 MHz 25 45 mA ICCXD SerializerSupplyCurrentPowerdown PWRDN = 0.8V 4 10 mA DESERIALIZER SUPPLY CURRENT (applytopinsDVCC and AVCC) ICCR DeserializerSupplyCurrent C L = 15 pF f= 40 MHz 44 75 mA WorstCase See Figure3 f= 16 MHz 31 55 mA ICCXR DeserializerSupplyCurrent PWRDN = 0.8V,REN = 0.8V 1.5 5.0 mAPowerdown SerializerTiming Requirements forTCLK Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ (1) Max Units tTCP TransmitClockPeriod 25 T 62.5 ns tTCIH TransmitClockHighTime 0.4T 0.5T 0.6T ns tTCIL TransmitClockLow Time 0.4T 0.5T 0.6T ns tCLKT TCLK InputTransitionTime 3 6 ns tJIT TCLK InputJitter 150 ps (1) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C. SerializerSwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ (1) Max Units tLLHT Bus LVDS Low-to-High R L = 27Ω 0.2 1 nsTransitionTime See Figure4 C L=10pF toGNDtLHLT Bus LVDS High-to-Low 0.25 1 nsTransitionTime tDIS DIN (0-9)SetuptoTCLK See Figure7 1.0 0 ns R L = 27Ω,tDIH DIN (0-9)HoldfromTCLK 6.5 4.5 nsC L=10pF toGND (1) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS92LV1021 DS92LV1210

DS92LV1021,DS92LV1210 SNLS024C –MARCH 1999–REVISED APRIL 2013 www.ti.com SerializerSwitchingCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ (1) Max Units tHZD DO ± HIGH to See Figure8 (2) 3.5 10 nsTRI-STATE Delay R L = 27Ω, C L=10pF toGNDtLZD DO ± LOW toTRI-STATE 2.9 10 nsDelay tZHD DO ± TRI-STATE toHIGH 2.5 10 nsDelay tZLD DO ± TRI-STATE toLOW 2.7 10 nsDelay tSPW SYNC PulseWidth See Figure9 1024*tTCP 1029*tTCP ns R L = 27ΩtPLD SerializerPLL Lock Time 2048*tTCP 2049*tTCP ns tSD SerializerDelay See Figure10 R L = 27Ω tTCP tTCP + 2.5 tTCP + 5 ns tBIT Bus LVDS BitWidth R L = 27Ω, tCLK /12 nsC L=10pF toGND (2) Due toTRI-STATE oftheSerializer,theDeserializerwilllosePLL lockand have toresynchronizebeforedatatransfer. DeserializerTiming Requirements forREFCLK Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ (1) Max Units tRFCP REFCLK Period 25 T 62.5 ns tRFDC REFCLK DutyCycle 50 % tRFCP /tTCP RatioofREFCLK toTCLK 0.83 1 1.03Periods tRFTT REFCLK TransitionTime 3 6 ns (1) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C. DeserializerSwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Pin/Freq. Min Typ (1) Max Units tRCP ReceiveroutClock See Figure10 RCLK 25 62.5 nsPeriod tRCP = tTCP tCLH CMOS/TTL Low-to-High CL = 15 pF Rout(0-9), 2 5 nsTransitionTime See Figure5 LOCK, RCLKtCHL CMOS/TTL High-to-Low 2 5 nsTransitionTime tDD DeserializerDelay See Figure11 1.75*tRCP 1.75*tRCP +3 1.75*tRCP +7 ns tROS ROUT (0-9)SetupData See Figure12 RCLK 0.4*tRCP 0.5*tRCP nstoRCLK tROH ROUT (0-9)HoldData −0.4*tRCP −0.5*tRCP nstoRCLK tRDC RCLK DutyCycle 40 50 60 % tHZR HIGH toTRI-STATE See Figure13 Rout(0-9), 4+0.5*tRCP 10+tRCP nsDelay LOCK tLZR LOW toTRI-STATE 4.2+0.5*tRCP 10+tRCP nsDelay tZHR TRI-STATE toHIGH 6+0.5*tRCP 12+tRCP nsDelay tZLR TRI-STATE toLOW 6.5+0.5*tRCP 12+tRCP nsDelay (1) TypicalvaluesaregivenforVCC = 3.3Vand TA = +25°C.

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DS92LV1021,DS92LV1210 www.ti.com SNLS024C –MARCH 1999–REVISED APRIL 2013 DeserializerSwitchingCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Pin/Freq. Min Typ (1) Max Units tDSR1 DeserializerPLL Lock See (2) 16MHz 7 15 μs Time fromPWRDWN See Figure14 40MHz 4.8 25.6 μs(withSYNCPAT) See Figure15 tDSR2 DeserializerPLL Lock 16MHz 7 10 μs timefromSYNCPAT 40MHz 4.5 7 μs tZHLK TRI-STATE toHIGH LOCK 1.5 12 nsDelay(power-up) tRNM DeserializerNoise See Figure16 16 MHz 400 1100 ps Margin See (3)

40 MHz 100 400 ps

(2) ForthepurposeofspecifyingdeserializerPLL performancetDSR1 and tDSR2 arespecifiedwiththeREFCLK runningand stable,and specificconditionsoftheincomingdatastream(SYNCPATs). Itisrecommended thatthederserializerbe initializedusingeithertDSR1 timingortDSR2 timing.tDSR1 isthetimerequiredforthedeserializertoindicatelockupon power-uporwhen leavingthepower-down mode. Synchronizationpatternsshouldbe senttothedevicebeforeinitiatingeithercondition.tDSR2 isthetimerequiredtoindicatelock forthepowered-upand enableddeserializerwhen theinput(RI+and RI-)conditionschange fromnotreceivingdatatoreceiving synchronizationpatterns(SYNCPATs). (3) tRNM isa measure ofhow much phase noise(jitter)thedeserializercan tolerateintheincomingdatastreambeforebiterrorsoccur. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS92LV1021 DS92LV1210

DS92LV1021,DS92LV1210 SNLS024C –MARCH 1999–REVISED APRIL 2013 www.ti.com AC TIMING DIAGRAMS AND TEST CIRCUITS Figure2. “Worst Case ” SerializerICC TestPattern Figure3. “Worst Case ” DeserializerICC TestPattern Figure4. SerializerBus LVDS Output Load and TransitionTimes Figure5. DeserializerCMOS/TTL Output Load and TransitionTimes Figure6. SerializerInputClock TransitionTime

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DS92LV1021,DS92LV1210 www.ti.com SNLS024C –MARCH 1999–REVISED APRIL 2013 Timingshown forTCLK_R/ F = LOW Figure7. SerializerSetup/HoldTimes Figure8. SerializerTRI-STATE TestCircuitand Timing Figure9. SerializerPLL Lock Time,SYNC Timing and PWRDN TRI-STATE Delays Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS92LV1021 DS92LV1210

DS92LV1021,DS92LV1210 SNLS024C –MARCH 1999–REVISED APRIL 2013 www.ti.com Figure10. SerializerDelay Figure11. DeserializerDelay Timingshown forRCLK_R/ F = LOW DutyCycle(tRDC )= Figure12. DeserializerSetup and Hold Times

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DS92LV1021,DS92LV1210 www.ti.com SNLS024C –MARCH 1999–REVISED APRIL 2013 Figure13. DeserializerTRI-STATE TestCircuitand Timing Figure14. DeserializerPLL Lock Times and PWRDN TRI-STATE Delays Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS92LV1021 DS92LV1210

DS92LV1021,DS92LV1210 SNLS024C –MARCH 1999–REVISED APRIL 2013 www.ti.com Figure15. DeserializerPLL Lock Time from SyncPAT SW -Setupand HoldTime (Internaldatasamplingwindow) tJIT-SerializerOutputBitPositionJitter tRSM = ReceiverSamplingMarginTime Figure16. ReceiverBus LVDS InputSkew Margin VOD = (DO +)–(DO −). Differentialoutputsignalisshown as (DO+)–(DO −),deviceinData Transfermode.

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DS92LV1021,DS92LV1210 www.ti.com SNLS024C –MARCH 1999–REVISED APRIL 2013

APPLICATION INFORMATION

USING THE DS92LV1021 AND DS92LV1210 The Serializerand Deserializerchipsetisan easy to use transmitterand receiverpairthatsends 10 bitsof parallelTTL dataovera serialBus LVDS linkup to400 Mbps. Serializationoftheinputdataisaccomplished usingan onboard PLL at the Serializerwhich embeds two clockbitswiththe data.The Deserializeruses a separatereferenceclock(REFCLK) and an onboardPLL toextracttheclockinformationfromtheincomingdata stream and deserializethe data.The Deserializermonitorsthe incomingclockinformationto determinelock statusand willindicatelossoflockby raisingtheLOCK output. POWER CONSIDERATIONS AllCMOS designoftheSerializerand Deserializermakes them inherentlylow power devices.Additionally,the constantcurrentsourcenatureoftheBus LVDS outputsminimizetheslopeofthespeed vs.ICC curveofCMOS designs. POWERING UP THE SERIALIZER The DS92LV1021 must be powered up usinga specificsequence toproperlystartthePLL up.Not followingthe sequence can cause theBus LVDS outputstobe stuckina certainoutputstate.Thismay occuriftheTCLK inputisdrivenbeforepower isappliedtotheSerializer.Itisimportanttonotethatthisisnota latchup condition: no excessivecurrentisdrawn by theSerializerinthisstateand thepower does notneed tobe cycledtorecover from thisstate.CyclingthePWRDWN pinfrom hightolow and back tohighwillresetthePLL and returnthe Serializertonormaloperation. To avoidthiscondition,theSerializershouldbe powered up (ALL VCC pins)simultaneouslywiththePWRDWN pinheldlow for1µs.Do notfloatthePWRDWN pin,externalpullresistorisrecommended. Once theVCC pins have stabilizedtheTCLK inputcan be drivenand theSerializerwillbe readyfordatatransmission. POWERING UP THE DESERIALIZER The DS92LV1210 can be powered up at any timefollowingthe propersequence.The REFCLK inputcan be runningbeforethe Deserializerispowered up and itmust be runninginorderforthe Deserializerto lockto incomingdata.The DeserializeroutputswillremaininTRI-STATE untiltheDeserializerdetectsdatatransmission atitsinputsand lockstotheincomingstream.The recommended power up sequence forthedeserializeristo power up allVCC pinssimultaneouslywiththePWRDWN pinheldlow for1µs.Once theVCC pinshave stabilized theDeserializerisreadyforlocking.Anotheroptiontoensureproperpower up istocyclethePWRDWN pinfrom hightolowand back tohighafterpower up. TRANSMITTING DATA Once theSerializerand Deserializerare powered up and runningtheymust be phase lockedtoeach otherin order to transmitdata.Phase lockingis accomplishedby the Serializersending SYNC patternsto the Deserializer.SYNC patternsare sentby theSerializerwhenever SYNC1 or SYNC2 inputsare heldhigh.The LOCK outputoftheDeserializerishighwhenever theDeserializerisnotlocked.ConnectingtheLOCK outputof theDeserializertoone oftheSYNC inputsoftheSerializerwillensurethatenough SYNC patternsare sentto achieveDeserializerlock. While the DeserializerLOCK outputislow,data at the Deserializeroutputs(ROUT0-9) isvalidexceptforthe specificcase oflossoflockduringtransmission. NOISE MARGIN The Deserializernoisemarginistheamount ofinputjitter(phasenoise)thattheDeserializercan tolerateand still reliablyreceivedata.Variousenvironmentaland systematicfactorsinclude: Serializer:TCLK jitter,VCC noise(noisebandwidthand out-of-bandnoise) Media:ISI,VCM noise Deserializer:VCC noise Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS92LV1021 DS92LV1210

DS92LV1021,DS92LV1210 SNLS024C –MARCH 1999–REVISED APRIL 2013 www.ti.com RECOVERING FROM LOCK LOSS Inthecase where theSerializerloseslockduringdatatransmissionup to5 cyclesofdatathatwas previously receivedcan be invalid.Thisisdue tothedelayinthelockdetectioncircuit.The lockdetectcircuitrequiresthat invalidclockinformationbe received4 timesina row toindicatelossoflock.Sinceclockinformationhas been lostitispossiblethatdatawas alsolostduringthesecycles.When theDeserializerLOCK pingoes low,data fromatleasttheprevious5 cyclesshouldbe resentupon regaininglock. Lock can be regainedattheDeserializerby causingtheSerializertoresendSYNC patternsas describedabove. PCB CONSIDERATIONS The Bus LVDS devicesSerializerand Deserializershouldbe placedas closetotheedge connectoras possible. InmultipleDeserializerapplications,thedistancefromtheDeserializertotheslotconnectorappearsas a stubto theSerializerdrivingthebackplanetraces.Longerstubslowertheimpedance ofthebus increasingtheloadon theSerializerand lowersthresholdmarginattheDeserializers.Deserializerdevicesshouldbe placedno more than1 inchfromtheslotconnector. TRANSMISSION MEDIA The Serializerand Deserializeraredesignedfordatatransmissionovera multi-dropbus.Multi-dropbuses use a singleSerializerand multipleDeserializerdevices.SincetheSerializercan be drivingfromany pointon thebus, thebus must be terminatedatbothends.For example,a 100 Ohm differentialbus must be terminatedateach end with100 Ohms loweringtheDC impedance thattheSerializermust driveto50 Ohms. Thisloadisfurther loweredby the additionof multipleDeserializers.Adding up to 20 Deserializersto the bus (dependingupon spacing)willlowerthe totalloadto about 27 Ohms (54 Ohm bus).The SerializerisdesignedforDC loads between 27 and 100 Ohms. The Serializerand Deserializercan alsobe used inpoint-to-pointconfigurationof a backplane,PCB traceor througha twistedpaircable.Inpoint-to-pointconfigurationsthetransmissionmedia need onlybe terminatedat thereceiverend.Inthepoint-to-pointconfigurationthepotentialofoffsettingtheground levelsoftheSerializer vs.theDeserializermust be considered.Bus LVDS providesa plus/minus one voltcommon mode rangeatthe receiverinputs. Pin Diagrams Figure17. DS92LV1021 SerializerDB Package

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DS92LV1021,DS92LV1210 www.ti.com SNLS024C –MARCH 1999–REVISED APRIL 2013 Figure18. DS92LV1210 DeserializerDB Package SERIALIZER PIN DESCRIPTIONS Pin Name I/O No. Description DIN I 3–12 Data Input.TTL levelsinputs.Data on thesepinsareloadedintoa 10- bitinputregister. TCLK_R/ F I 13 TransmitClockRising/Fallingstrobeselect.TTL levelinput.Selects TCLK activeedge forstrobingofDIN data.Highselectsrisingedge. Low selectsfallingedge. DO+ O 22 + SerialData Output.Non-invertingBus LVDS differentialoutput. DO − O 21 − SerialData Output.InvertingBus LVDS differentialoutput. DEN I 19 SerialData OutputEnable.TTL levelinput.A low,putstheBus LVDS outputsinTRI-STATE. PWRDN I 24 Powerdown. TTL levelinput.PWRDN drivenlowshutsdown thePLL and TRI-STATEs outputsputtingthedeviceintoa lowpower sleep mode. Do notfloatthePWRDWN pin,externalpullresistoris recommended. A pull-downwilldisablethedeviceuntilitisactively driven(enabled). TCLK I 14 TransmitClock.TTL levelinput.Inputfor16 MHz –40 MHz (nominal) systemclock. SYNC I 1,2 AssertionofSYNC (high)foratleast1024 synchronizationsymbolsto be transmittedon theBus LVDS serialoutput.Synchronization symbolscontinuetobe sentifSYNC continuesasserted.TTL level input.The two SYNC pinsareORed. DVCC I 27,28 DigitalCircuitpower supply. DGND I 15,16 DigitalCircuitground. AVCC I 17,26 Analogpower supply(PLL and AnalogCircuits). AGND I 18,25,20,23 Analogground(PLL and AnalogCircuits). DESERIALIZER PIN DESCRIPTION Pin Name I/O No. Description ROUT O 15–19,24–28 Data Output.±9 mA CMOS leveloutputs. RCLK_R/ F I 2 RecoveredClockRising/Fallingstrobeselect.TTL levelinput.Selects RCLK activeedge forstrobingofROUT data.Highselectsrisingedge. Low selectsfallingedge. RI+ I 5 + SerialData Input.Non-invertingBus LVDS differentialinput. RI− I 6 − SerialData Input.InvertingBus LVDS differentialinput. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS92LV1021 DS92LV1210

DS92LV1021,DS92LV1210 SNLS024C –MARCH 1999–REVISED APRIL 2013 www.ti.com DESERIALIZER PIN DESCRIPTION (continued) Pin Name I/O No. Description PWRDN I 7 Powerdown. TTL levelinput.PWRDN drivenlowshutsdown thePLL and TRI-STATEs outputsputtingthedeviceintoa lowpower sleep mode. LOCK O 10 LOCK goes lowwhen theDeserializerPLL locksontotheembedded clockedge.CMOS leveloutput.Totem poleoutputstructure,does not directlysupportwireOR connection. RCLK O 9 RecoveredClock.Paralleldatarateclockrecoveredfromembedded clock.Used tostrobeROUT, CMOS leveloutput. REN I 8 OutputEnable.TTL levelinput.TRI-STATEs ROUT0 –ROUT9, LOCK and RCLK when drivenlow. DVCC I 21,23 DigitalCircuitpower supply. DGND I 14,20,22 DigitalCircuitground. AVCC I 4,11 Analogpower supply(PLL and AnalogCircuits). AGND I 1,12,13 Analogground(PLL and AnalogCircuits). REFCLK I 3 Use thispintosupplya REFCLK signalfortheinternalPLL frequency. TruthTable DIN (0–9) TCLK_R/ F TCLK SYNC1/SYNC2 DEN PWRDN DO+ DO − X X X X X 0 Z Z X X X X 0 1 Z Z X X SYSTEM 1(1) 1 1 SYNC PTRN SYNC CLK PTRN (2) DATA 1 0 1 1 DATA (0–9) DATA (0–9)v DATA 0 0 1 1 DATA (0–9) DATA (0–9)(2) RI RI− RCLK_R/ F REFCLK REN PWRDN RCLK LOCK ROUT (0–9) X X X X X 0 Z Z Z X X X X 0(3) 1 Z Z Z SYNC PTRN SYNC X SYSTEM CLK 1 1 CLK 1(4) SYNC PTRN PTRN (2) DATA (0–9) DATA (0–9)(2) 1 SYSTEM CLK 1 1 0 DATA DATA (0–9) DATA (0–9)(2) 0 SYSTEM CLK 1 1 0 DATA (1) Pulse5-bits (2) Inverted (3) Devicemust be lockedfirst (4) Must be 1 beforeSYNC PTRN starts

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REVISION HISTORY

Changes from RevisionB (April2013)toRevisionC Page Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS92LV1021 DS92LV1210

www.ti.com 13-Sep-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS92LV1021TMSA NRND SSOP DB 28 47 TBD Call TI Call TI DS92LV1021T MSA DS92LV1021TMSA/NOPB NRND SSOP DB 28 47 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR DS92LV1021T MSA DS92LV1021TMSAX/NOPB NRND SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR DS92LV1021T MSA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 13-Sep-2014 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant DS92LV1021TMSAX/NOP B PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV1021TMSAX/NOP B SSOP DB 28 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Pack Materials-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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