DS92LV090A TI | Alldatasheet

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www.ti.com SNLS025D –APRIL 2000–REVISED APRIL 2013 DS92LV090A9ChannelBusLVDSTransceiver Check forSamples: DS92LV090A 1FEATURES DESCRIPTION The DS92LV090A isone in a seriesof Bus LVDS 2• Bus LVDS Signaling transceiversdesignedspecificallyforthehighspeed,• 3.2Nanosecond PropagationDelay Max low power proprietarybackplaneor cableinterfaces.

  • Chip toChip Skew ±800ps The deviceoperatesfroma single3.3V power supply and includesnine differentiallinedriversand nine• Low Power CMOS Design receivers.To minimizebus loading,thedriveroutputs• High SignalingRate Capability(Above 100 and receiverinputsare internallyconnected.TheMbps) separateI/O of the logicsideallowsforloop back
  • 0.1Vto2.3VCommon Mode Range forVID = support.The devicealsofeaturesa flowthroughpin 200mV out which allowseasy PCB routingforshortstubs between itspinsand theconnector.• ±100 mV ReceiverSensitivity The drivertranslates3V TTL levels(single-ended)to• Supports Open and TerminatedFailsafeon differentialBus LVDS (BLVDS) outputlevels.ThisPortPins allowsforhigh speed operation,whileconsuming• 3.3VOperation minimal power with reduced EMI. In addition,the
  • GlitchFree Power Up/Down (Driver& Receiver differentialsignalingprovidescommon mode noise Disabled) rejectionof±1V.
  • LightBus Loading (5pF Typical)per Bus The receiverthresholdislessthan ±100 mV over aLVDS Load ±1V common mode range and translatesthe differentialBus LVDS to standard (TTL/CMOS)• Designed forDouble TerminationApplications levels.(See ApplicationsInformationSectionformore• Balanced Output Impedance details.)• Product Offeredin64 Pin LQFP Package
  • High Impedance Bus Pins on Power off(VCC = 0V)
  • DriverChannel toChannel Skew (Same Device)230ps Typical
  • ReceiverChannel toChannel Skew (Same Device)370ps Typical SimplifiedFunctionalDiagram Figure1. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2000–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS025D –APRIL 2000–REVISED APRIL 2013 www.ti.com Connection Diagram Figure2. Top View PIN DESCRIPTIONS Pin Name Pin # Input/Output Descriptions DO+/RI+ 27,31,35,37,41,45, I/O TrueBus LVDS DriverOutputsand ReceiverInputs. 47,51,55 DO −/RI− 26,30,34,36,40,44, I/O ComplimentaryBus LVDS DriverOutputsand ReceiverInputs. 46,50,54 D IN 2,6,12,18,20,22,58, I TTL DriverInput. 60,62 RO 3,7,13,19,21,23,59, O TTL ReceiverOutput. 61,63 RE 17 I ReceiverEnableTTL Input(ActiveLow). DE 16 I DriverEnableTTL Input(ActiveHigh). GND 4,5,9,14,25,56 Power Ground fordigitalcircuitry(mustconnecttoGND on PC board).These pins connectedinternally. VCC 10,15,24,57,64 Power VCC fordigitalcircuitry(mustconnecttoVCC on PC board).These pins connectedinternally. AGND 28,33,43,49,53 Power Ground foranalogcircuitry(mustconnecttoGND on PC board).These pins connectedinternally. AV CC 29,32,42,48,52 Power AnalogVCC (mustconnecttoVCC on PC board).These pinsconnected internally. NC 1,8,11,38,39 N/A Leave open circuit,do notconnect. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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www.ti.com SNLS025D –APRIL 2000–REVISED APRIL 2013 AbsoluteMaximum Ratings (1)(2)(3) SupplyVoltage(VCC ) 4.0V EnableInputVoltage(DE,RE) −0.3Vto(VCC +0.3V) DriverInputVoltage(DIN) −0.3Vto(VCC +0.3V) ReceiverOutputVoltage(ROUT ) −0.3Vto(VCC +0.3V) Bus PinVoltage(DO/RI±) −0.3Vto+3.9V ESD (HBM 1.5kΩ,100 pF) >4.5kV DriverShortCircuitDuration momentary ReceiverShortCircuitDuration momentary Maximum Package Power Dissipationat25°C LQFP 1.74W DerateLQFP Package 13.9mW/ °C θja 71.7°C/W θjc 10.9°C/W JunctionTemperature +150°C StorageTemperatureRange −65°C to+150°C Lead Temperature(Soldering,4 sec.) 260°C (1) Allcurrentsintodevicepinsarepositive;allcurrentsoutofdevicepinsarenegative.Allvoltagesarereferencedtogroundunless otherwisespecifiedexceptVOD ,ΔVOD and VID. (2) “AbsoluteMaximum Ratings”arethosevaluesbeyond whichthesafetyofthedevicecannotbe ensured.They arenotmeant toimply thatthedevicesshouldbe operatedattheselimits.The tableof“ElectricalCharacteristics”providesconditionsforactualdevice operation. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingConditions Min Max Units SupplyVoltage(VCC ) 3.0 3.6 V ReceiverInputVoltage 0.0 2.4 V OperatingFreeAirTemperature −40 +85 °C Maximum InputEdge Rate (20% to80%) (1) Δt/ΔV Data 1.0 ns/V Control 3.0 ns/V (1) Generatorwaveformsforalltestsunlessotherwisespecified:f= 25 MHz, ZO = 50Ω,tr,tf= <1.0ns (0%–100%).To ensurefastest propagationdelayand minimum skew,datainputedge ratesshouldbe equaltoorfasterthan1ns/V;controlsignalsequaltoorfaster than3ns/V.Ingeneral,thefastertheinputedge rate,thebettertheAC performance. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS92LV090A

SNLS025D –APRIL 2000–REVISED APRIL 2013 www.ti.com DC ElectricalCharacteristics Over recommended operatingsupplyvoltageand temperaturerangesunlessotherwisespecified(1)(2) Symbol Parameter Conditions Pin UnitMin Typ Max s VOD OutputDifferentialVoltage R L = 27Ω,Figure3 DO+/RI+, 240 300 460 mV DO −/RI−ΔVOD VOD MagnitudeChange 27 mV VOS OffsetVoltage 1.1 1.3 1.5 V ΔVOS OffsetMagnitudeChange 5 10 mV VOH DriverOutputHighVoltage(3) R L = 27Ω 1.4 1.65 V VOL DriverOutputLow Voltage(3) R L = 27Ω 0.95 1.1 V IOSD OutputShortCircuitCurrent(4) VOD = 0V,DE = VCC ,Driveroutputs |36| |65| mAshortedtogether VOH VoltageOutputHigh (5) VID = +300 mV IOH = −400 µA R OUT VCC −0.2 V InputsOpen VCC −0.2 V InputsTerminated, VCC −0.2 VR L = 27Ω VOL VoltageOutputLow IOL = 2.0mA, VID = −300 mV 0.05 0.075 V IOD ReceiverOutputDynamic VID = 300mV, VOUT = VCC −1.0V −110 |75| mA Current(4) VID = −300mV, VOUT = 1.0V |75| 110 mA VTH InputThresholdHigh DE = 0V,VCM = 1.5V DO+/RI+, +100 mV DO −/RI−VTL InputThresholdLow −100 mV VCMR ReceiverCommon Mode Range |VID|/2 2.4− V|VID|/2 IIN InputCurrent DE = 0V,RE = 2.4V, −20 ±1 +20 µAVIN = +2.4V or0V VCC = 0V,VIN = +2.4V or0V −20 ±1 +20 µA VIH Minimum InputHighVoltage D IN,DE, RE 2.0 VCC V VIL Maximum InputLow Voltage GND 0.8 V IIH InputHighCurrent VIN = VCC or2.4V −20 ±10 +20 µA IIL InputLow Current VIN = GND or0.4V −20 ±10 +20 µA VCL InputDiodeClamp Voltage ICLAMP = −18 mA −1.5 −0.8 V ICCD Power SupplyCurrentDrivers No Load,DE = RE = VCC , VCC 55 80 mAEnabled,ReceiversDisabled DIN = VCC orGND ICCR Power SupplyCurrentDrivers DE = RE = 0V,VID = ±300mV 73 80 mADisabled,ReceiversEnabled ICCZ Power SupplyCurrent,Drivers DE = 0V;RE = VCC , 35 80 mAand ReceiversTRI-STATE DIN = VCC orGND ICC Power SupplyCurrent,Drivers DE = VCC ;RE = 0V, and ReceiversEnabled DIN = VCC orGND, 170 210 mA R L = 27Ω IOFF Power OffLeakage Current VCC = 0V orOPEN, DO+/RI+, D IN,DE, RE = 0V orOPEN, DO −/RI− −20 +20 µA VAPPLIED = 3.6V(PortPins) C OUTPUT Capacitance@ Bus Pins DO+/RI+, 5 pFDO −/RI− cOUTPUT Capacitance@ R OUT R OUT 7 pF (1) Allcurrentsintodevicepinsarepositive;allcurrentsoutofdevicepinsarenegative.Allvoltagesarereferencedtogroundunless otherwisespecifiedexceptVOD ,ΔVOD and VID. (2) AlltypicalsaregivenforVCC = +3.3V and TA = +25°C, unlessotherwisestated. (3) The DS92LV090A functionswithindatasheetspecificationwhen a resistiveloadisappliedtothedriveroutputs. (4) Onlyone outputata timeshouldbe shorted,do notexceed maximum package power dissipationcapacity. (5) VOH failsafeterminatedtestperformedwith27Ω connectedbetween RI+ and RI− inputs.No externalvoltageisapplied.

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www.ti.com SNLS025D –APRIL 2000–REVISED APRIL 2013 AC ElectricalCharacteristics Over recommended operatingsupplyvoltageand temperaturerangesunlessotherwisespecified(1) Symbol Parameter Conditions Min Typ Max Units DIFFERENTIAL DRIVER TIMING REQUIREMENTS tPHLD DifferentialProp.DelayHightoLow (2) R L = 27Ω, 0.6 1.4 2.2 ns Figure4,Figure5,tPLHD DifferentialProp.DelayLow toHigh (2) 0.6 1.4 2.2 nsC L = 10 pF tSKD1 DifferentialSkew |tPHLD –tPLHD |(3) 80 ps tSKD2 ChiptoChipSkew (4) 1.6 ns tSKD3 ChanneltoChannelSkew (5) 0.25 0.45 ns tTLH TransitionTime Low toHigh 0.6 1.2 ns tTHL TransitionTime HightoLow 0.5 1.2 ns tPHZ DisableTime HightoZ R L = 27Ω, 3 8 ns Figure6,Figure7,tPLZ DisableTime Low toZ 3 8 nsC L = 10 pF tPZH EnableTime Z toHigh 3 8 ns tPZL EnableTime Z toLow 3 8 ns DIFFERENTIAL RECEIVER TIMING REQUIREMENTS tPHLD DifferentialProp.DelayHightoLow (2) Figure8,Figure9, 1.6 2.4 3.2 ns C L = 35 pFtPLHD DifferentialProp DelayLow toHigh (2) 1.6 2.4 3.2 ns tSDK1 DifferentialSkew |tPHLD –tPLHD |(3) 80 ps tSDK2 ChiptoChipSkew (4) 1.6 ns tSDK3 ChanneltoChannelSkew (5) 0.35 0.60 ns tTLH TransitionTime Low toHigh 1.5 2.5 ns tTHL TransitionTime HightoLow 1.5 2.5 ns tPHZ DisableTime HightoZ R L = 500Ω, 4.5 10 ns Figure10,Figure11,tPLZ DisableTime Low toZ 3.5 8 nsC L = 35 pF tPZH EnableTime Z toHigh 3.5 8 ns tPZL EnableTime Z toLow 3.5 8 ns (1) Generatorwaveformsforalltestsunlessotherwisespecified:f= 25 MHz, ZO = 50Ω,tr,tf= <1.0ns (0%–100%).To ensurefastest propagationdelayand minimum skew,datainputedge ratesshouldbe equaltoorfasterthan1ns/V;controlsignalsequaltoorfaster than3ns/V.Ingeneral,thefastertheinputedge rate,thebettertheAC performance. (2) Propagationdelaysarespecifiedby designand characterization. (3) tSKD1 |tPHLD –tPLHD |istheworse case skew between any channeland any deviceoverrecommended operationconditions. (4) ChiptoChipskew isthedifferenceindifferentialpropagationdelaybetween any channelsofany devices,eitheredge. (5) ChanneltoChannelskew isthedifferenceindriveroutputorreceiveroutputpropagationdelaybetween any channelswithina device, eitheredge. Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS92LV090A

SNLS025D –APRIL 2000–REVISED APRIL 2013 www.ti.com APPLICATIONS INFORMATION Generalapplicationguidelinesand hintsmay be found inthe followingapplicationnotes:AN-808 (SNLA028 ), AN-903 (SNLA034 ),AN-971 (SNLA165 ),AN-977 (SNLA166 ),and AN-1108 (SNLA008 ). There are a few common practiceswhich shouldbe impliedwhen designingPCB forBus LVDS signaling. Recommended practicesare:

  • Use atleast4 PCB boardlayer(BusLVDS signals,ground,power and TTL signals).
  • Keep driversand receiversas closetothe(BusLVDS portside)connectoras possible.
  • Bypass each Bus LVDS deviceand alsouse distributedbulkcapacitancebetween power planes.Surface mount capacitorsplacedclosetopower and groundpinswork best.Two orthreehighfrequency,multi-layer ceramic(MLC) surfacemount (0.1µF,0.01µF,0.001µF) inparallelshouldbe used between each VCC and ground.The capacitorsshouldbe as closeas possibletotheVCC pin. – Multipleviasshouldbe used toconnectVCC and Ground planestothepads oftheby-passcapacitors. – Inaddition,randomlydistributedby-passcapacitorsshouldbe used.
  • Use theterminationresistorwhichbestmatches thedifferentialimpedance ofyourtransmissionline.
  • Leave unused Bus LVDS receiverinputsopen (floating).Limittraceson unused inputsto<0.5inches.
  • IsolateTTL signalsfromBus LVDS signals MEDIA (CONNECTOR orBACKPLANE) SELECTION:
  • Use controlledimpedance media. The backplane and connectorsshould have a matched differential impedance. Table1.FunctionalTable MODE SELECTED DE RE DRIVER MODE H H RECEIVER MODE L L TRI-STATE MODE L H LOOP BACK MODE H L Table2.TransmitterMode INPUTS OUTPUTS DE D IN DO+ DO − H L L H H H H L H 0.8V< D IN <2.0V X X L X Z Z Table3.ReceiverMode (1) INPUTS OUTPUT RE (RI+)– (RI−) L L (< −100 mV) L L H (> +100 mV) H L −100 mV < VID < +100 mV X H X Z (1) X = HighorLow logicstate L = Low state Z = Highimpedance state H = Highstate

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www.ti.com SNLS025D –APRIL 2000–REVISED APRIL 2013 TestCircuitsand Timing Waveforms Figure3. DifferentialDriverDC TestCircuit Figure4. DifferentialDriverPropagationDelay and TransitionTime TestCircuit Figure5. DifferentialDriverPropagationDelay and TransitionTime Waveforms Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS92LV090A

SNLS025D –APRIL 2000–REVISED APRIL 2013 www.ti.com Figure6. DriverTRI-STATE Delay TestCircuit Figure7. DriverTRI-STATE Delay Waveforms Figure8. ReceiverPropagationDelay and TransitionTime TestCircuit Figure9. ReceiverPropagationDelay and TransitionTime Waveforms

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www.ti.com SNLS025D –APRIL 2000–REVISED APRIL 2013 Figure10. ReceiverTRI-STATE Delay TestCircuit Figure11. ReceiverTRI-STATE Delay Waveforms TypicalBus ApplicationConfigurations Figure12. Bi-DirectionalHalf-DuplexPoint-to-PointApplications Figure13. Multi-PointBus Applications Copyright© 2000–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS92LV090A

SNLS025D –APRIL 2000–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionC (April2013)toRevisionD Page

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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS92LV090ATVEH/NO.A Active Production LQFP (PM) | 64 160 | JEDEC TRAY (10+1) Yes SN Level-3-260C-168 HR -40 to 85 DS92LV090A TVEH DS92LV090ATVEH/NOPB Active Production LQFP (PM) | 64 160 | JEDEC TRAY (10+1) Yes SN Level-3-260C-168 HR -40 to 85 DS92LV090A TVEH DS92LV090ATVEHX/NO.A Active Production LQFP (PM) | 64 1000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 DS92LV090A TVEH DS92LV090ATVEHX/NOPB Active Production LQFP (PM) | 64 1000 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 85 DS92LV090A TVEH (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

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PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant DS92LV090ATVEHX/ NOPB Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV090ATVEHX/ NOPB LQFP PM 64 1000 356.0 356.0 45.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) DS92LV090ATVEH/ NO.A PM LQFP 64 160 8 X 20 150 322.6 135.9 7620 15.2 13.1 13 DS92LV090ATVEH/ NOPB PM LQFP 64 160 8 X 20 150 322.6 135.9 7620 15.2 13.1 13 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 64X 0.27 0.1760X 0.5 PIN 1 ID

0.05 MIN

4X 7.5 0.08 TYP12.2 11.8 (0.13) TYP

1.6 MAX

B NOTE 3 10.2 9.8 A NOTE 3 10.2 9.8 0.75 0.45 0.25 GAGE PLANE -70 (1.4) PLASTIC QUAD FLATPACK LQFP - 1.6 mm max heightPM0064A PLASTIC QUAD FLATPACK 4215162/A 03/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MS-026. 17 32 4964

0.08 C A B

0.08 SEATING PLANE DETAIL A SCALE: 14 DETAIL A TYPICAL SCALE 1.400

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND 0.05 MIN ALL AROUND 64X (1.5) 64X (0.3) (11.4) (11.4)60X (0.5) (R0.05) TYP LQFP - 1.6 mm max heightPM0064A PLASTIC QUAD FLATPACK 4215162/A 03/2017 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004). LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM SYMM 64 49 17 32 METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 64X (1.5) 64X (0.3) 60X (0.5) (R0.05) TYP (11.4) (11.4) LQFP - 1.6 mm max heightPM0064A PLASTIC QUAD FLATPACK 4215162/A 03/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 64 49 17 32 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

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