DS92LV090A NSC | Alldatasheet

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n 3.2 nanosecond propagation delay max n Chip to Chip skew±800ps n Low power CMOS design n High Signaling Rate Capability (above 100 Mbps) n 0.1V to 2.3V Common Mode Range for VID = 200mV n ±100 mV Receiver Sensitivity n Supports open and terminated failsafe on port pins n 3.3V operation n Glitch free power up/down (Driver & Receiver disabled) n Light Bus Loading (5 pF typical) per Bus LVDS load n Designed for Double Termination Applications n Balanced Output Impedance n Product offered in 64 pin TQFP package n High impedance Bus pins on power off (VCC = 0V) n Driver Channel to Channel skew (same device) 230ps typical n Receiver Channel to Channel skew (same device) 370ps typical Simplified Functional Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. DS100111-1 April 2000 DS92LV090A9 Channel Bus LVDS Transceiver © 2000 National Semiconductor Corporation DS100111 www.national.com

Pin Name Pin # Input/Output Descriptions 45, 47, 51, 55 I/O True Bus LVDS Driver Outputs and Receiver Inputs. 44, 46, 50, 54 I/O Complimentary Bus LVDS Driver Outputs and Receiver Inputs. D IN 2, 6, 12, 18, 20, 22, 58, 60, 62 I TTL Driver Input. RO 3, 7, 13, 19, 21, 23, 59, 61, 63 O TTL Receiver Output. RE 17 I Receiver Enable TTL Input (Active Low). DE 16 I Driver Enable TTL Input (Active High). GND 4, 5, 9, 14, 25, 56 Power Ground for digital circuitry (must connect to GND on PC board). These pins connected internally. VCC 10, 15, 24, 57, 64 Power V CC for digital circuitry (must connect to VCC on PC board). These pins connected internally. AGND 28, 33, 43, 49, 53 Power Ground for analog circuitry (must connect to GND on PC board). These pins connected internally. AV CC 29, 32, 42, 48, 52 Power Analog V CC (must connect to VCC on PC board). These pins connected internally. NC 1, 8, 11, 38, 39 N/A Leave open circuit, do not connect. DS100111-2 Top View Order Number DS92LV090ATVEH See NS Package Number VEH064DB DS92LV090A www.national.com 2

Absolute Maximum Ratings(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC ) 4.0V Enable Input Voltage (DE, RE) −0.3V to (VCC +0.3V) Driver Input Voltage (DIN) −0.3V to (V CC +0.3V) Receiver Output Voltage (ROUT ) −0.3V to (V CC +0.3V) Bus Pin Voltage (DO/RI±) −0.3V to +3.9V ESD (HBM 1.5 kΩ , 100 pF) >4.5 kV Driver Short Circuit Duration momentary Receiver Short Circuit Duration momentary Maximum Package Power Dissipation at 25˚C TQFP 1.74 W Derate TQFP Package 13.9 mW/˚C θ ja 71.7˚C/W θjc 10.9˚C/W Storage Temperature Range −65˚C to +150˚C Lead Temperature (Soldering, 4 sec.) 260˚C Recommended Operating Conditions Min Max Units Supply Voltage (VCC ) 3.0 3.6 V Receiver Input Voltage 0.0 2.4 V Operating Free Air Temperature −40 +85 ˚C Maximum Input Edge Rate (Note 6)(20% to 80%) Δt/ΔV Data 1.0 ns/V Control 3.0 ns/V Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3) Symbol Parameter Conditions Pin Min Typ Max Units VOD Output Differential Voltage R L =2 7Ω ,Figure 1 DO+/RI+, DO−/RI− 240 300 460 mV ΔVOD VOD Magnitude Change 27 mV VOS Offset Voltage 1.1 1.3 1.5 V ΔVOS Offset Magnitude Change 51 0 m V VOH Driver Output High Voltage R L =2 7Ω 1.4 1.65 V VOL Driver Output Low Voltage R L =2 7Ω 0.95 1.1 V IOSD Output Short Circuit Current (Note 10) VOD = 0V, DE = VCC , Driver outputs shorted together |36| |65| mA VOH Voltage Output High (Note 11) VID = +300 mV I OH = −400 µA R OUT VCC −0.2 V Inputs Open V CC −0.2 V Inputs Terminated, R L =2 7Ω VCC −0.2 V VOL Voltage Output Low I OL = 2.0 mA, VID = −300 mV 0.05 0.075 V IOD Receiver Output Dynamic Current (Note 10) V ID = 300mV, VOUT =V CC −1.0V −110 |75| mA VID = −300mV, VOUT = 1.0V |75| 110 mA VTH Input Threshold High DE = 0V, V CM = 1.5V DO+/RI+, DO−/RI− +100 mV VTL Input Threshold Low −100 mV VCMR Receiver Common Mode Range |VID|/2 2.4 − |VID|/2 V IIN Input Current DE = 0V, RE = 2.4V, VIN = +2.4V or 0V −20 ±1 +20 µA VCC = 0V, VIN = +2.4V or 0V −20 ±1 +20 µA DS92LV090A www.national.com3

Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3) Symbol Parameter Conditions Pin Min Typ Max Units VIH Minimum Input High Voltage D IN, DE, RE 2.0 V CC V VIL Maximum Input Low Voltage GND 0.8 V IIH Input High Current V IN =V CC or 2.4V −20 ±10 +20 µA IIL Input Low Current V IN = GND or 0.4V −20 ±10 +20 µA VCL Input Diode Clamp Voltage ICLAMP = −18 mA −1.5 −0.8 V ICCD Power Supply Current Drivers Enabled, Receivers Disabled No Load, DE = RE = V CC , D I N=VCC or GND VCC 55 80 mA ICCR Power Supply Current Drivers Disabled, Receivers Enabled D E=R E=0 V ,V ID = ±300mV 73 80 mA ICCZ Power Supply Current, Drivers and Receivers TRI-STATE DE = 0V; RE = VCC , D I N=VCC or GND 35 80 mA ICC Power Supply Current, Drivers and Receivers Enabled D E=V CC ;R E=0 V , D I N=VCC or GND, R L =2 7Ω 170 210 mA IOFF Power Off Leakage Current VCC = 0V or OPEN, D IN, DE, RE = 0V or OPEN, VAPPLIED = 3.6V (Port Pins) DO+/RI+, DO−/RI− −20 +20 µA C OUTPUT Capacitance@ Bus Pins DO+/RI+, DO−/RI− 5p F cOUTPUT Capacitance@ R OUT R OUT 7p F Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6) Symbol Parameter Conditions Min Typ Max Units DIFFERENTIAL DRIVER TIMING REQUIREMENTS t PHLD Differential Prop. Delay High to Low (Note 8) R L =2 7Ω , Figures 2, 3, C L =1 0p F 0.6 1.4 2.2 ns tPLHD Differential Prop. Delay Low to High (Note 8) 0.6 1.4 2.2 ns tSKD1 Differential Skew |tPHLD –tPLHD | (Note 9) 80 ps tSKD2 Chip to Chip Skew (Note 12) 1.6 ns tSKD3 Channel to Channel Skew (Note 13) 0.25 0.45 ns tTLH Transition Time Low to High 0.6 1.2 ns tTHL Transition Time High to Low 0.5 1.2 ns tPHZ Disable Time High to Z R L =2 7Ω , Figures 4, 5, C L =1 0p F 38 n s tPLZ Disable Time Low to Z 38 n s tPZH Enable Time Z to High 38 n s tPZL Enable Time Z to Low 38 n s DIFFERENTIAL RECEIVER TIMING REQUIREMENTS t PHLD Differential Prop. Delay High to Low (Note 8) Figures 6, 7, C L =3 5p F 1.6 2.4 3.2 ns tPLHD Differential Prop Delay Low to High (Note 8) 1.6 2.4 3.2 ns tSDK1 Differential Skew |tPHLD –tPLHD | (Note 9) 80 ps tSDK2 Chip to Chip Skew (Note 12) 1.6 ns tSDK3 Channel to Channel Skew (Note 13) 0.35 0.60 ns tTLH Transition Time Low to High 1.5 2.5 ns tTHL Transition Time High to Low 1.5 2.5 ns DS92LV090A www.national.com 4

should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 3:All typicals are given for VCC = +3.3V and TA = +25˚C, unless otherwise stated. Note 5:C L includes probe and fixture capacitance. the better the AC performance. Note 7:The DS92LV090A functions within datasheet specification when a resistive load is applied to the driver outputs. Note 8:Propagation delays are guaranteed by design and characterization. Note 9:tSKD1 |tPHLD –tPLHD | is the worse case skew between any channel and any device over recommended operation conditions. Note 10:Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity. Note 11:VOH failsafe terminated test performed with 27Ω connected between RI+ and RI− inputs. No external voltage is applied. Note 12:Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge. Note 13:Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device, either edge.

  • Use at least 4 PCB board layer (Bus LVDS signals, ground, power and TTL signals).
  • Keep drivers and receivers as close to the (Bus LVDS port side) connector as possible.
  • Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes. Surface mount capacitors placed close to power and ground pins work best. Two or three high frequency, multi-layer ceramic (MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in paral- lel should be used between each V CC and ground. The capacitors should be as close as possible to the VCC pin. Multiple vias should be used to connect VCC and Ground planes to the pads of the by-pass capacitors. In addition, randomly distributed by-pass capacitors should be used.
  • Use the termination resistor which best matches the dif- ferential impedance of your transmission line.
  • Leave unused Bus LVDS receiver inputs open (floating). Limit traces on unused inputs to <0.5 inches.
  • Isolate TTL signals from Bus LVDS signals MEDIA (CONNECTOR or BACKPLANE) SELECTION:
  • Use controlled impedance media. The backplane and connectors should have a matched differential imped- ance.

TABLE 1. Functional Table TABLE 2. Transmitter Mode TABLE 3. Receiver Mode

Physical DimensionsAll dimensions are in millimeters LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com 64-Lead Molded TQFP Package Order Number DS92LV090ATVEH DS92LV090A9 Channel Bus LVDS Transceiver National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.