DS92LV090A

DS92LV090A_07 NSC | Alldatasheet

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■ Bus LVDS Signaling ■ 3.2 nanosecond propagation delay max ■ Chip to Chip skew ±800ps ■ Low power CMOS design ■ High Signaling Rate Capability (above 100 Mbps) ■ 0.1V to 2.3V Common Mode Range for VID = 200mV ■ ±100 mV Receiver Sensitivity ■ Supports open and terminated failsafe on port pins ■ 3.3V operation ■ Glitch free power up/down (Driver & Receiver disabled) ■ Light Bus Loading (5 pF typical) per Bus LVDS load ■ Designed for Double Termination Applications ■ Balanced Output Impedance ■ Product offered in 64 pin TQFP package ■ High impedance Bus pins on power off (VCC = 0V) ■ Driver Channel to Channel skew (same device) 230ps typical ■ Receiver Channel to Channel skew (same device) 370ps typical Simplified Functional Diagram 10011101 TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 100111 www.national.com DS92LV090A 9 Channel Bus LVDS Transceiver

Order Number DS92LV090ATVEH See NS Package Number VEH064DB Pin Descriptions Pin Name Pin # Input/Output Descriptions 47, 51, 55 I/O True Bus LVDS Driver Outputs and Receiver Inputs. 46, 50, 54 I/O Complimentary Bus LVDS Driver Outputs and Receiver Inputs. DIN 2, 6, 12, 18, 20, 22, 58, 60, 62 I TTL Driver Input. RO 3, 7, 13, 19, 21, 23, 59, 61, 63 O TTL Receiver Output. RE 17 I Receiver Enable TTL Input (Active Low). DE 16 I Driver Enable TTL Input (Active High). GND 4, 5, 9, 14, 25, 56 Power Ground for digital circuitry (must connect to GND on PC board). These pins connected internally. VCC 10, 15, 24, 57, 64 Power VCC for digital circuitry (must connect to VCC on PC board). These pins connected internally. AGND 28, 33, 43, 49, 53 Power Ground for analog circuitry (must connect to GND on PC board). These pins connected internally. AVCC 29, 32, 42, 48, 52 Power Analog VCC (must connect to VCC on PC board). These pins connected internally. NC 1, 8, 11, 38, 39 N/A Leave open circuit, do not connect. www.national.com 2 DS92LV090A

Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) 4.0V Enable Input Voltage (DE, RE ) −0.3V to (VCC +0.3V) Driver Input Voltage (DIN) −0.3V to (VCC +0.3V) Receiver Output Voltage (R OUT) −0.3V to (VCC +0.3V) Bus Pin Voltage (DO/RI±) −0.3V to +3.9V ESD (HBM 1.5 kΩ, 100 pF) >4.5 kV Driver Short Circuit Duration momentary Receiver Short Circuit Duration momentary Maximum Package Power Dissipation at 25°C TQFP 1.74 W Derate TQFP Package 13.9 mW/°C θja 71.7°C/W θjc 10.9°C/W Junction Temperature +150°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 4 sec.) 260°C Recommended Operating Conditions Min Max Units Supply Voltage (VCC) 3.0 3.6 V Receiver Input Voltage 0.0 2.4 V Operating Free Air Temperature −40 +85 °C Maximum Input Edge Rate (Note 6)(20% to 80%) Δt/ΔV Data 1.0 ns/V Control 3.0 ns/V Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3) Symbol Parameter Conditions Pin Min Typ Max Units VOD Output Differential Voltage RL = 27Ω, Figure 1 DO+/RI+, DO−/RI− 240 300 460 mV ΔVOD VOD Magnitude Change 27 mV VOS Offset Voltage 1.1 1.3 1.5 V ΔVOS Offset Magnitude Change 5 10 mV VOH Driver Output High Voltage RL = 27Ω 1.4 1.65 V VOL Driver Output Low Voltage RL = 27Ω 0.95 1.1 V IOSD Output Short Circuit Current (Note 10) VOD = 0V, DE = VCC, Driver outputs shorted together |36| |65| mA VOH Voltage Output High (Note 11) VID = +300 mV IOH = −400 µA ROUT VCC−0.2 V Inputs Open VCC−0.2 V Inputs Terminated, RL = 27Ω VCC−0.2 V VOL Voltage Output Low IOL = 2.0 mA, VID = −300 mV 0.05 0.075 V IOD Receiver Output Dynamic Current (Note 10) VID = 300mV, VOUT = VCC−1.0V −110 |75| mA VID = −300mV, VOUT = 1.0V |75| 110 mA VTH Input Threshold High DE = 0V, VCM = 1.5V DO+/RI+, DO−/RI− +100 mV VTL Input Threshold Low −100 mV VCMR Receiver Common Mode Range |VID|/2 2.4 − | VID|/2 V IIN Input Current DE = 0V, RE = 2.4V, VIN = +2.4V or 0V −20 ±1 +20 µA VCC = 0V, VIN = +2.4V or 0V −20 ±1 +20 µA VIH Minimum Input High Voltage DIN, DE, RE 2.0 VCC V VIL Maximum Input Low Voltage GND 0.8 V IIH Input High Current VIN = VCC or 2.4V −20 ±10 +20 µA IIL Input Low Current VIN = GND or 0.4V −20 ±10 +20 µA VCL Input Diode Clamp Voltage ICLAMP = −18 mA −1.5 −0.8 V 3 www.national.com DS92LV090A

Symbol Parameter Conditions Pin Min Typ Max Units ICCD Power Supply Current Drivers Enabled, Receivers Disabled No Load, DE = RE = VCC, DIN = VCC or GND VCC 55 80 mA ICCR Power Supply Current Drivers Disabled, Receivers Enabled DE = RE = 0V, VID = ±300mV 73 80 mA ICCZ Power Supply Current, Drivers and Receivers TRI- STATE® DE = 0V; RE = VCC, DIN = VCC or GND 35 80 mA ICC Power Supply Current, Drivers and Receivers Enabled DE = VCC; RE = 0V, DIN = VCC or GND, RL = 27Ω 170 210 mA IOFF Power Off Leakage Current VCC = 0V or OPEN, DIN, DE, RE = 0V or OPEN, VAPPLIED = 3.6V (Port Pins) DO+/RI+, DO−/RI− −20 +20 µA COUTPUT Capacitance @ Bus Pins DO+/RI+, DO−/RI− 5 pF cOUTPUT Capacitance @ ROUT ROUT 7 pF www.national.com 4 DS92LV090A

Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6) Symbol Parameter Conditions Min Typ Max Units DIFFERENTIAL DRIVER TIMING REQUIREMENTS tPHLD Differential Prop. Delay High to Low (Note 8) RL = 27Ω, Figures 2, 3, CL = 10 pF 0.6 1.4 2.2 ns tPLHD Differential Prop. Delay Low to High (Note 8) 0.6 1.4 2.2 ns tSKD1 Differential Skew |tPHLD–tPLHD| (Note 9) 80 ps tSKD2 Chip to Chip Skew (Note 12) 1.6 ns tSKD3 Channel to Channel Skew (Note 13) 0.25 0.45 ns tTLH Transition Time Low to High 0.6 1.2 ns tTHL Transition Time High to Low 0.5 1.2 ns tPHZ Disable Time High to Z RL = 27Ω, Figures 4, 5, CL = 10 pF 3 8 ns tPLZ Disable Time Low to Z 3 8 ns tPZH Enable Time Z to High 3 8 ns tPZL Enable Time Z to Low 3 8 ns DIFFERENTIAL RECEIVER TIMING REQUIREMENTS tPHLD Differential Prop. Delay High to Low (Note 8) Figures 6, 7, CL = 35 pF 1.6 2.4 3.2 ns tPLHD Differential Prop Delay Low to High (Note 8) 1.6 2.4 3.2 ns tSDK1 Differential Skew |tPHLD–tPLHD| (Note 9) 80 ps tSDK2 Chip to Chip Skew (Note 12) 1.6 ns tSDK3 Channel to Channel Skew (Note 13) 0.35 0.60 ns tTLH Transition Time Low to High 1.5 2.5 ns tTHL Transition Time High to Low 1.5 2.5 ns tPHZ Disable Time High to Z RL = 500Ω, Figures 8, 9, CL = 35 pF 4.5 10 ns tPLZ Disable Time Low to Z 3.5 8 ns tPZH Enable Time Z to High 3.5 8 ns tPZL Enable Time Z to Low 3.5 8 ns Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified except VOD, ΔVOD and VID. Note 3: All typicals are given for VCC = +3.3V and TA = +25°C, unless otherwise stated. Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) > 4.5 kV EIAJ (0Ω, 200 pF) > 300V. Note 5: CL includes probe and fixture capacitance. Note 6: Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50Ω, tr, tf = <1.0 ns (0%–100%). To ensure fastest propagation delay and minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge rate, the better the AC performance. Note 7: The DS92LV090A functions within datasheet specification when a resistive load is applied to the driver outputs. Note 8: Propagation delays are guaranteed by design and characterization. Note 9: tSKD1 |tPHLD–tPLHD| is the worse case skew between any channel and any device over recommended operation conditions. Note 10: Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity. Note 11: VOH failsafe terminated test performed with 27Ω connected between RI+ and RI− inputs. No external voltage is applied. Note 12: Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge. Note 13: Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device, either edge. 5 www.national.com DS92LV090A

Typical Bus Application Configurations 10011112 Bi-Directional Half-Duplex Point-to-Point Applications 10011113 Multi-Point Bus Applications 9 www.national.com DS92LV090A

Physical Dimensions inches (millimeters) unless otherwise noted 64-Lead Molded TQFP Package Order Number DS92LV090ATVEH www.national.com 10 DS92LV090A

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