DS92LV0412

DS92LV0411 NSC | Alldatasheet

Document overview

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Technical content

Features

■ 5-channel (4 data + 1 clock) Channel Link LVDS parallel interface supports 24-bit data 3-bit control at 5 – 50 MHz ■ AC Coupled STP Interconnect up to 10 meters in length ■ Integrated serial CML terminations ■ AT–SPEED BIST Mode and status pin ■ Optional I2C compatible Serial Control Bus ■ Power Down Mode minimizes power dissipation ■ 1.8V or 3.3V compatible control pin interface ■ >8 kV ESD (HBM) protection ■ -40° to +85°C temperature range SERIALIZER – DS92LV0411 ■ Data scrambler for reduced EMI ■ DC–balance encoder for AC coupling ■ Selectable output VOD and adjustable de-emphasis DESERIALIZER – DS92LV0412 ■ Random data lock; no reference clock required ■ Adjustable input receiver equalization ■ EMI minimization on output parallel bus (Spread Spectrum Clock Generation and LVDS VOD select)

Applications

■ Embedded Video and Display ■ Machine Vision, Industrial Imaging, Medical Imaging ■ Office Automation — Printers, Scanners, Copiers ■ Security and Video Surveillance ■ General purpose data communication Applications Diagram 30125227 TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2010 National Semiconductor Corporation 301252 www.national.com DS92LV0411 / DS92LV0412 5- 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

Ordering Information

DS92LV0411SQE 36–pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch 250 NOPB SQA36A DS92LV0411SQ 36–pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch 1000 NOPB SQA36A DS92LV0411SQX 36–pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch 2500 NOPB SQA36A DS92LV0412SQE 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch 250 NOPB SQA48A DS92LV0412SQ 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch 1000 NOPB SQA48A DS92LV0412SQX 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch 2500 NOPB SQA48A www.national.com 2 DS92LV0411 / DS92LV0412

DS92LV0411 — Top View DS92LV0411 Pin Descriptions Pin Name Pin # I/O, Type Description Channel Link Parallel Input Interface RxIN[3:0]+ 2, 33, 31, 29 I, LVDS True LVDS Data Input This pair should have a 100 Ω termination for standard LVDS levels. I, LVDS Inverting LVDS Data Input This pair should have a 100 Ω termination for standard LVDS levels. RxCLKIN+ 35 I, LVDS True LVDS Clock Input This pair should have a 100 Ω termination for standard LVDS levels. RxCLKIN- 34 I, LVDS Inverting LVDS Clock Input This pair should have a 100 Ω termination for standard LVDS levels. Control and Configuration PDB 23 I, LVCMOS w/ pull-down Power-down Mode Input PDB = 1, Device is enabled (normal operation). Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section. PDB = 0, Device is powered down When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic high, the PLL is shutdown, IDD is minimized. Control Registers are RESET. 3 www.national.com DS92LV0411 / DS92LV0412

Pin Name Pin # I/O, Type Description VODSEL 20 I, LVCMOS w/ pull-down Differential Driver Output Voltage Select — Pin or Register Control VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typ) — Long Cable / De-E Applications VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typ) De-Emph 19 I, Analog w/ pull-up De-Emphasis Control — Pin or Register Control De-Emph = open (float) - disabled To enable De-emphasis, tie a resistor from this pin to GND or control via register. See Table 4 MAPSEL 26 I, LVCMOS w/ pull-down Channel Link Map Select — Pin or Register Control MAPSEL = 1, MSB on RxIN3+/-. Figure 22 MAPSEL = 0, LSB on RxIN3+/-. Figure 21 CONFIG [1:0] 10, 9 I, LVCMOS w/ pull-down Operating Modes — Pin or Limited Register Control Determines the device operating mode and interfacing device. Table 1 CONFIG[1:0] = 00: Interfacing to DS92LV2412 or DS92LV0412, Control Signal Filter DISABLED CONFIG[1:0] = 01: Interfacing to DS92LV2412 or DS92LV0412, Control Signal Filter ENABLED CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124 CONFIG [1:0] = 11: Interfacing to DS90C124 ID[x] 4 I, Analog Serial Control Bus Device ID Address Select — Optional Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 10. SCL 6 I, LVCMOS Serial Control Bus Clock Input - Optional SCL requires an external pull-up resistor to VDDIO. SDA 7 I/O, LVCMOS Open Drain Serial Control Bus Data Input / Output - Optional SDA requires an external pull-up resistor VDDIO. BISTEN 21 I, LVCMOS w/ pull-down BIST Mode — Optional BISTEN = 1, BIST is enabled BISTEN = 0, BIST is disabled 18, 13, 12, 8 I, LVCMOS w/ pull-down Reserved - tie LOW Channel Link II Serial Interface DOUT+ 16 O, CML True Output. The output must be AC Coupled with a 0.1 μF capacitor. DOUT- 15 O, CML Inverting Output. The output must be AC Coupled with a 0.1 μF capacitor. Power and Ground VDDL 5 Power Logic Power, 1.8 V ±5% VDDP 11 Power PLL Power, 1.8 V ±5% VDDHS 14 Power TX High Speed Logic Power, 1.8 V ±5% VDDTX 17 Power Output Driver Power, 1.8 V ±5% VDDRX 24 Power RX Power, 1.8 V ±5% VDDIO 22 Power LVCMOS I/O Power and Channel Link I/O Power 1.8 V ±5% OR 3.3 V ±10% GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the LLP package. Connect to the ground plane (GND) with at least 9 vias. NOTE: 1= HIGH, 0 L= LOW The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. www.national.com 4 DS92LV0411 / DS92LV0412

DS92LV0412 — Top View DS92LV0412 Pin Descriptions Pin Name Pin # I/O, Type Description Channel Link II Serial Interface RIN+ 40 I, CML True Input. The output must be AC Coupled with a 0.1 μF capacitor. RIN- 41 I, CML Inverting Input. The output must be AC Coupled with a 0.1 μF capacitor. Channel Link Parallel Output Interface RxIN[3:0]+ 15, 19, 21, 23 O, LVDS True LVDS Data Output This pair should have a 100 Ω termination for standard LVDS levels. RxIN[3:0]- 16, 20, 22, 24 O, LVDS Inverting LVDS Data Output This pair should have a 100 Ω termination for standard LVDS levels. RxCLKIN+ 17 O, LVDS True LVDS Clock Output This pair should have a 100 Ω termination for standard LVDS levels. RxCLKIN- 18 O, LVDS Inverting LVDS Clock Output This pair should have a 100 Ω termination for standard LVDS levels. 5 www.national.com DS92LV0411 / DS92LV0412

Pin Name Pin # I/O, Type Description LVCMOS Outputs LOCK 27 O, LVCMOS LOCK Status Output LOCK = 1, PLL is locked, output stated determined by OEN. LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN. See Table XXX. Control and Configuration PDB 1 I, LVCMOS w/ pull-down Power-down Mode Input PDB = 1, Device is enabled (normal operation). Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section. PDB = 0, Device is powered down When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic high, the PLL is shutdown, IDD is minimized. Control Registers are RESET. VODSEL 33 I, LVCMOS w/ pull-down Parallel LVDS Driver Output Voltage Select — Pin or Register Control VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typ) — Long Cable / De-E Applications VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typ) OEN 30 I, LVCMOS w/ pull-down Output Enable. See Table 5. OSS_SEL 35 I, LVCMOS w/ pull-down Output Sleep State Select Input. See Table 5. LFMODE 36 I, LVCMOS w/ pull-down SSCG Low Frequency Mode — Pin or Register Control LF_MODE = 1, low frequency mode (TxCLKOUT = 10–20 MHz) LF_MODE = 0, high frequency mode (TxCLKOUT = 20–65 MHz) SSCG not avaialble above 65 MHz. MAPSEL 34 I, LVCMOS w/ pull-down Channel Link Map Select — Pin or Register Control MAPSEL = 1, MSB on TxOUT3+/-. MAPSEL = 0, LSB on TxOUT3+/-. CONFIG [1:0] 11, 10 I, LVCMOS w/ pull-down Operating Modes — Pin or Limited Register Control Determine the device operating mode and interfacing device. CONFIG[1:0] = 00: Interfacing to DS92LV2411 or DS92LV0411, Control Signal Filter DISABLED CONFIG[1:0] = 01: Interfacing to DS92LV2411 or DS92LV0411, Control Signal Filter ENABLED CONFIG [1:0] = 10: Interfacing to DS90UR241, DS99R421 CONFIG [1:0] = 11: Interfacing to DS90C124 SSC[2:0] 7, 2, 3 I, LVCMOS w/ pull-down Spread Spectrum Clock Generation (SSCG) Range Select See Table 8, Table 9 RES 37 I, LVCMOS w/ pull-down Reserved Control and Configuration — STRAP PIN EQ 28 [PASS] STRAP I, LVCMOS w/ pull-down EQ Gain Control of Channel Link II Serial Input EQ = 1, EQ gain is enabled (~12 dB) EQ = 0, EQ gain is disabled (~ 1.625 dB) Optional BIST Mode BISTEN 29 I, LVCMOS w/ pull-down BIST Mode — Optional BISTEN = 1, BIST is enabled BISTEN = 0, BIST is disabled PASS 28 O, LVCMOS PASS Output (BIST Mode) — Optional PASS =1, no errors detected PASS = 0, errors detected Leave open if unused. Route to a test point (pad) recommended. www.national.com 6 DS92LV0411 / DS92LV0412

Pin Name Pin # I/O, Type Description Optional Serial Bus Control ID[x] 12 I, Analog Serial Control Bus Device ID Address Select — Optional Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See . SCL 5 I, LVCMOS Open Drain Serial Control Bus Clock Input - Optional SCL requires an external pull-up resistor to 3.3V. SDA 4 I/O, LVCMOS Open Drain Serial Control Bus Data Input / Output - Optional SDA requires an external pull-up resistor 3.3V. Power and Ground VDDL 6, 31 Power Logic Power, 1.8 V ±5% VDDA 38, 43 Power Analog Power, 1.8 V ±5% VDDP 6 Power PLL Power, 1.8 V ±5% VDDSC 46, 47 Power SSC Generator Power, 1.8 V ±5% VDDTX 24 Power Channel Link LVDS Parallel Output Power, 1.8 V ±5% VDDIO 25 Power LVCMOS I/O Power and Channel Link I/O Power 1.8 V ±5% OR 3.3 V ±10% GND 9, 14, 26, 32, 39, 44, 45, 48 Ground Ground DAP DAP Ground DAP is the large metal contact at the bottom side, located at the center of the LLP package. Connect to the ground plane (GND) with at least 9 vias. NOTE: 1= HIGH, 0 L= LOW The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage. 7 www.national.com DS92LV0411 / DS92LV0412

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – VDDn (1.8V) −0.3V to +2.5V Supply Voltage – VDDIO −0.3V to +4.0V Supply Voltage – VDDTX (3.3V) −0.3V to +4.0V LVCMOS I/O Voltage −0.3V to +(VDDIO + 0.3V) LVDS Input Voltage −0.3V to (VDDIO + 0.3V) LVDS Output Voltage −0.3V to (VDDTX + 0.3V) CML Driver Output Voltage −0.3V to (– VDDn + 0.3V) Receiver Input Voltage −0.3V to (VDD + 0.3V) Junction Temperature +150°C Storage Temperature −65°C to +150°C Maximum Power Dissipation Capacity at 25°C Derate above 25°C 1/ θJA°C/W θJA 27.4 °C/W θJC 4.5 °C/W Maximum Power Dissipation Capacity at 25°C Derate above 25°C 1/ θJA°C/W θJA 27.7 °C/W θJC 3.0 °C/W ESD Rating (IEC, powered-up only), RD = 330Ω, CS = 150 pF Air Discharge (RIN+, RIN-) ≥±30 kV Contact Discharge (RIN+, RIN-) ≥±8 kV ESD Rating (HBM) ≥±8 kV ESD Rating (CDM) ≥±1.25 kV ESD Rating (MM) ≥±250 V For soldering specifications: See product folder at www.national.com and www.national.com/ms/MS/MS-SOLDERING.pdf Recommended Operating Conditions Min Nom Max Units Supply Voltage (VDDn) 1.71 1.8 1.89 V Supply Voltage (VDDTX) 3.0 3.3 3.6 V LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 V OR LVCMOS Supply Voltage (VDDIO) 3.0 3.3 3.6 V Operating Free Air Temperature (T A) −40 +25 +85 °C RxCLKIN/TxCLKOUT Clock Frequency 5 50 MHz Supply Noise (Note 10) 100 mVP-P Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 3, Note 4) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units DS92LV0411 LVCMOS INPUT DC SPECIFICATIONS VIH High Level Input Voltage VDDIO = 3.0 to 3.6V PDB, VODSEL, MAPSEL, CONFIG[1:0], BISTEN

2.0 VDDIO V

VDDIO = 1.71 to 1.89V 0.65* VDDIO VDDIO V VIL Low Level Input Voltage VDDIO = 3.0 to 3.6V GND 0.8 V VDDIO = 1.71 to 1.89V GND 0.35* VDDIO V IIN Input Current VIN = 0V or VDDIO VDDIO = 3.0 to 3.6V −15 ±1 +15 μA VDDIO = 1.7 to 1.89V −15 ±1 +15 μA www.national.com 8 DS92LV0411 / DS92LV0412

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units DS92LV0412 LVCMOS I/O DC SPECIFICATIONS VIH High Level Input Voltage VDDIO = 3.0 to 3.6V PDB, VODSEL, OEN, MAPSEL, LFMODE, SSC[2:0], BISTEN VDDIO = 1.71 to 1.89V 0.65* VDDIO VDDIO V VIL Low Level Input Voltage VDDIO = 3.0 to 3.6V GND 0.8 V VDDIO = 1.71 to 1.89V GND 0.35* VDDIO V IIN Input Current VIN = 0V or VDDIO VDDIO = 3.0 to 3.6V −15 ±1 +15 μA VDDIO = 1.7 to 1.89V −15 ±1 +15 μA VOH High Level Output Voltage IOH = -0.5 mA LOCK, PASS VDDIO –

0.2 VDDIO V

VOL Low Level Output Voltage IOL = +0.5 mA GND 0.2 V IOS Output Short Circuit Current VOUT = 0V VDDIO = 3.0 to

3.6 V -10

mAVDDIO = 1.71 to 1.89V -3 IOZ TRI-STATE® Output Current PDB = 0V, OSS_SEL = 0V, VOUT = 0V or VDDIO VDDIO = 3.0 to

3.6 V -10 +10

μAVDDIO = 1.71 to 1.89V -15 +15 DS92LV0411 CHANNEL LINK PARALLEL LVDS RECEIVER DC SPECIFICATIONS VTH Differential Threshold High Voltage VCM = 1.2V, Figure 1 RxIN[3:0]+/-, RxCLKIN+/-, +100 mV VTL Differential Threshold Low Voltage −100 |VID| Differential Input Voltage Swing 200 600 mV VCM Common Mode Voltage VDDIO = 3.3V 0 1.2 2.4 VVDDIO = 1.8V 0 1.2 1.7 IIN Input Current −10 ±1 +10 μA DS92LV0412 CHANNEL LINK PARALLEL LVDS DRIVER DC SPECIFICATIONS |VOD| Differential Output Voltage RL = 100Ω VODSEL = L RxCLKOUT TxCLKOUT-, TxOUT[3:0]+, TxOUT[3:0]- 100 250 400 mV VODSEL = H 200 400 600 mV VODp-p Differential Output Voltage A – B VODSEL = L 500 mVp-p VODSEL = H 800 mVp-p ΔVOD Output Voltage Unbalance 1 50 mV VOS Offset Voltage VODSEL = L 1.0 1.2 1.5 V VODSEL = H 1.2 V ΔVOS Offset Voltage Unbalance 1 50 mV IOS Output Short Circuit Current -5 mA IOZ Output TRI-STATE® Current -10 +10 μA 9 www.national.com DS92LV0411 / DS92LV0412

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units DS92LV0411 Channel Link II CML DRIVER DC SPECIFICATIONS VOD Differential Output Voltage RL = 100Ω, De-emph = disabled, Figure 3 VODSEL = 0 DOUT+, DOUT- ±225 ±300 ±375 mVVODSEL = 1 ±350 ±450 ±550 VODp-p Differential Output Voltage (DOUT+) – (DOUT-) VODSEL = 0 600 mVp-p VODSEL = 1 900 mVp-p ΔVOD Output Voltage Unbalance RL = 100Ω, De-emph = disabled, VODSEL = L 1 TBD mV VOS Offset Voltage – Single-ended At TP A & B, Figure 2 RL = 100Ω, De-emph = disabled VODSEL = 0 1.65 V VODSEL = 1 1.575 V ΔVOS Offset Voltage Unbalance Single-ended At TP A & B, Figure 2 RL = 100Ω, De-emph = disabled 1 mV IOS Output Short Circuit Current DOUT+/- = 0V, De-emph = disabled VODSEL = 0 −36 mA RT Internal Termination Resistor 80 120 Ω DS92LV0412 CHANNEL LINK II CML RECEIVER DC SPECIFICATIONS VTH Differential Input Threshold High Voltage VCM = +1.2V (Internal VBIAS) RIN+, RIN- +50 mV VTL Differential Input Threshold Low Voltage -50 mV VCM Common mode Voltage, Internal VBIAS 1.2 V RT Input Termination 85 100 115 Ω DS92LV0411 SUPPLY CURRENT IDDT1 Supply Current (includes load current) RL = 100Ω, f = 50 MHz Checker Board Pattern, De-emph = disabled, VODSEL = H, Figure VDD= 1.89V All VDD pins 65 TBD mA IDDIOT1 VDDIO= 1.89V VDDIO TBD TBD mA VDDIO = 3.6V TBD TBD mA IDDT2 Checker Board Pattern, De-emph = disabled, VODSEL = L, Figure VDD= 1.89V All VDD pins TBD TBD mA IDDIOT2 VDDIO= 1.89V VDDIO TBD TBD mA VDDIO = 3.6V TBD TBD mA IDDT3 RANDOM pattern, De-emph = disabled, VODSEL = H VDD= 1.89V All VDD pins TBD mA IDDIOT3 VDDIO= 1.89V VDDIO TBD mA VDDIO = 3.6V TBD mA IDDZ Supply Current Power-down PDB = 0V , (All other LVCMOS Inputs = 0V) VDD= 1.89V All VDD pins 100 TBD µA IDDIOZ VDDIO= 1.89V VDDIO TBD TBD µA VDDIO = 3.6V TBD TBD µA DS92LV0412 SUPPLY CURRENT IDD1 Supply Current (Includes load current)

50 MHz Clock

Pattern, VODSEL = H, SSCG = On VDDn = 1.89 V All VDD(1:8) pins TBD TBD mA IDDTX1 VDDTX = 3.6 V VDDTX TBD TBD mA IDDIO1 VDDIO = 1.89 V VDDIO TBD TBD mA VDDIO = 3.6 V TBD TBD mA www.national.com 10 DS92LV0411 / DS92LV0412

Symbol Parameter Conditions Pin/Freq. Min Typ Max Units IDDZ Supply Current Power Down PDB = 0V, All other LVCMOS Inputs = 0V VDD = 1.89 V All VDD(1:8) pins TBD TBD mA IDDTXZ VDDTX = 3.6 V VDDTX TBD TBD mA IDDIOZ VDDIO = 1.89 V VDDIO TBD TBD mA VDDIO = 3.6V TBD TBD mA Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units DS92LV0411 CHANNEL LINK PARALLEL LVDS INPUT tRSP0 Receiver Strobe Position-bit 0 RxCLKIN = 50 MHz, RxIN[3:0] Figure 5 TBD 1.1 TBD ns tRSP1 Receiver Strobe Position-bit 1 TBD 3.3 TBD ns tRSP2 Receiver Strobe Position-bit 2 TBD 5.5 TBD ns tRSP3 Receiver Strobe Position-bit 3 TBD 7.7 TBD ns tRSP4 Receiver Strobe Position-bit 4 TBD 9.9 TBD ns tRSP5 Receiver Strobe Position-bit 5 TBD 12.1 TBD ns tRSP6 Receiver Strobe Position-bit 6 TBD 14.3 TBD ns RJIT RxCLKIN Cycle-to-Cycle Jitter (Input clock requirement) TBD ns DS92LV0412 CHANNEL LINK PARALLEL LVDS OUTPUT tLHT Low to High Transition Time RL = 100Ω 0.3 0.6 ns tTHLT High to Low Transition Time 0.3 0.6 ns tDCCJ Cycle-to-Cycle Output Jitter TxCLKOUT± = 5 MHz 900 2100 ps TxCLKOUT± = 50 MHz 75 125 ps tTTP1 Transmitter Pulse Position for bit 1 5 – 50 MHz 0 UI tTTP0 Transmitter Pulse Position for bit 0 1 UI tTTP6 Transmitter Pulse Position for bit 6 2 UI tTTP5 Transmitter Pulse Position for bit 5 3 UI tTTP4 Transmitter Pulse Position for bit 4 4 UI tTTP3 Transmitter Pulse Position for bit 3 5 UI tTTP2 Transmitter Pulse Position for bit 2 6 UI tSD Delay-Latency TBD TBD ns tTPDD Power Down Delay Active to OFF

50 MHz 6 10 ns

50 MHz 40 55 ns

DS92LV0411 Channel Link II CML OUTPUT tHLT Output Low-to-High Transition Time Figure 3 RL = 100Ω, De-emphasis = disabled, VODSEL = 0 100 200 300 ps RL = 100Ω, De-emphasis = disabled, VODSEL = 1 100 200 300 ps 11 www.national.com DS92LV0411 / DS92LV0412

Symbol Parameter Conditions Min Typ Max Units tHLT Output High-to-Low Transition Time Figure 4 RL = 100Ω, De-emphasis = disabled, VODSEL = 0 130 260 390 ps RL = 100Ω, De-emphasis = disabled, VODSEL = 1 100 200 300 ps tXZD Ouput Active to OFF Delay, Figure 9 TBD TBD ns tPLD PLL Lock Time, Figure 7 RL = 100Ω 10 ms tSD Delay - Latency, Figure 10 RL = 100Ω 140*T TBD ns tDJIT Output Total Jitter, Figure 12 RL = 100Ω, De-Emph = disabled, RANDOM pattern 0.3 TBD UI λSTXBW Jitter Transfer Function -3 dB Bandwidth TBD kHz δSTX Jitter Transfer Function Peaking TBD dB DS92LV0412 CHANNEL LINK II CML INPUT tDDLT Lock Time SSCG = OFF,

5 MHz

SSCG = ON, SSCG = OFF,

50 MHz

SSCG = ON, tDJIT Input Jitter Tolerance EQ = OFF Jitter Frequency > 10 MHz >0.45 UI DS92LV0412 LVCMOS OUTPUTS tCLH Low to High Transition Time CL = 8 pF LOCK pin, PASS pin 10 15 ns tCHL High to Low Transition Time 10 15 ns tPASS BIST PASS Valid Time, BISTEN = 1 PASS pin

50 MHz 70 75 ns

tDEV Spread Spectrum Clocking Deviation Frequency TxCLKOUT = 5 – 50 MHz, SSC[2:0] = ON ±0.5 ±2 % tMOD Spread Spectrum Clocking Modulation Frequency TxCLKOUT = 5 – 50 MHz, SSC[2:0] = ON 8 100 kHz www.national.com 12 DS92LV0411 / DS92LV0412

DC and AC Serial Control Bus Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units VIH Input High Level SDA and SCL 0.7* VDDIO VDDIO V VIL Input Low Level Voltage SDA and SCL GND 0.3* VDDIO V VHY Input Hysteresis >50 mV VOL SDA, IOL = 3mA 0 0.36 V Iin SDA or SCL, Vin = VDDIO or GND -10 +10 µA tR SDA RiseTime – READ SDA, RPU = X, Cb ≤ 400pF, Figure 18 TBD TBD ns tF SDA Fall Time – READ TBD TBD ns tSU;DAT Set Up Time — READ Figure 18 TBD ns tHD;DAT Hold Up Time — READ Figure 18 TBD ns tSP Input Filter 50 ns Cin Input Capacitance SDA or SCL <5 pF Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed. Note 3: Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of product characterization and are not guaranteed. Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD, VTH and VTL which are differential voltages. Note 5: When the device output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data transfer require tPLD Note 6: tPLD is the time required by the device to obtain lock when exiting power-down state with an active RxCLKIN. Note 7: UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*PCLK). The UI scales with PCLK frequency. Note 8: tDPJ is the maximum amount the period is allowed to deviate over many samples. Note 9: tDCCJ is the maximum amount of jitter between adjacent clock cycles. Note 10: Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with amplitude = 100 mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the noise frequency is less than 400 kHz. Note 11: Specification is guaranteed by characterization and is not tested in production. Note 12: Specification is guaranteed by design and is not tested in production. 13 www.national.com DS92LV0411 / DS92LV0412

FIGURE 5. DS92LV0411 LVDS Receiver Strobe Positions

Link LVDS bus to the display, ASIC, or FPGA. 27 bit spaces will always be sampled. 3) can be selected by configuring the MAPSEL pin to HIGH. See Figure 13 for the normal Channel Link LVDS mapping. schemes can also be selected by register control. FIGURE 19. Channel Link II Serial Stream selected by pin or through register programming. TABLE 1. DS92LV0411 Configuration Modes TABLE 2. DS92LV0412 Configuration Modes

• Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles. Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal can cause a visual display error. This feature allows for the chipset to validate and filter out any high frequency noise on the control signals. See Figure 20. 21 www.national.com DS92LV0411 / DS92LV0412

modulation and ±0.5, ±1 or ±2% deviations (center spread). external pin or by register. TABLE 3. Ser — Differential Output Voltage TABLE 4. De-Emphasis Resistor Value FIGURE 23. De-Emph vs. R value outputs are both pulled to VDD and present a 0V VOD state. will offer a system power savings.

Optional Serial Bus Control Please see the following section on the optional Serial Bus Control Interface. Optional BIST Mode Please see the following section on the chipset BIST mode for details. DESERIALIZER Functional

Description

The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal check for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins and strap pins or through the op- tional serial control bus. The Des features enhance signal quality on the link with an integrated equalizer on the serial input and Channel Link II data encoding which provides ran- domization, scrambling, and DC balanacing of the data. The Des includes multiple features to reduce EMI associated with data transmission. This includes the randomization and scrambling of the data, the output spread spectrum clock generation (SSCG) support and output clock and data slew rate select. The Des features power saving features with a power down mode, and optional LVCMOS (1.8 V) interface compatibility. Oscillator Output — Optional The DS92LV0412 provides an optional TxCLKOUT when the input clock (serial stream) has been lost. This is based on an internal oscillator. The frequency of the oscillator may be se- lected. This feature may be controlled by the external pin or through the registers. Clock-DATA RECOVERY STATUS FLAC (LOCK), OUTPUT ENABLE (OEN) and OUTPUT STATE SELECT () SS_SEL) When PDB is driven HIGH, the CDR PLL begins locking to the serial input, LOCK is LOW and the Channel Link interface state is determined by the state of the OSS_SEL pin. After the DS92LV0412 completes its lock sequence to the in- put serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is avail- able on the Channel Link outputs. The TxCLKOUT output is held at its current state at the change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered clock (or vice ver- sa). Note that the Channel Link outputs may be held in an inactive state (TRI-STATE®) through the use of the Output Enable pin (OEN). If there is a loss of clock from the input serial stream, LOCK is driven LOW and the state of the outputs are based on the OSS_SEL setting (configuration pin or register). TABLE 5. Des Output State Table feature may be controlled by the external pin or by register. TABLE 6. Receiver Equalization

is controlled by the VODSEL input. TABLE 7. Des — Differential Output outputs are modulated. This will aid to lower system EMI. controlled by external STRAP pins or by register. TABLE 8. SSCG Configuration (LF_MODE = L) — Des Output

TABLE 9. SSCG Configuration (LF_MODE = H) — Des Output FIGURE 24. SSCG Waveform tional Serial Bus Control Registers are RESET. will offer a system power savings.

TABLE 12. DS92LV0411 SERIALIZER — Serial Bus Control Registers

6 R/W 0 MAPSEL 0: LSB on RxIN3

5 R/W 0 Reserved Reserved

4 R/W 0 VODSEL 0: Low

1 R/W 0 SLEEP Note – not the same function as PowerDown (PDB)

1: Sleep Mode – Register settings retained.

0 R/W 0 REG 0: Configurations set from control pins

All other addresses are Reserved.

4 R/W 0 De-E EN 0: De-Emphasis Enabled

TABLE 13. DS92LV0412 DESERIALIZER — Serial Bus Control Registers

6 R/W 0 MAPSEL Channel Link Map Select

4 R/W 0 Reserved Reserved

1: Sleep Mode – Register settings retained.

0 R/W 0 REG Control 0: Configurations set from control pins

All other addresses are Reserved.

6 R/W 0 OSS_SEL Output Sleep State Select

3 R/W 0 VODSEL LVDS Driver Output Voltage Select

(dec) ADD (hex) Register Name Bit(s) R/W Defa ult (bin) Function Description 3 3 Des Features 2 7:5 R/W 000 EQ Gain 000: ~1.625 dB 001: ~3.25 dB 010: ~4.87 dB 011: ~6.5 dB 100: ~8.125 dB 101: ~9.75 dB 110: 11.375 dB 111: 13 dB

4 R/W 0 EQ Enable 0: EQ = disabled

1: EQ = enabled

3 R/W 0 Reserved Reserved

2:0 R/W 000 SSC IF LFMODE = 0 then: 000: SSCG OFF 001: fdev = ±0.9%, fmod = CLK/2168 010: fdev = ±1.2%, fmod = CLK/2168 011: fdev = ±1.9%, fmod = CLK/2168 100: fdev = ±2.3%, fmod = CLK/2168 101: fdev = ±0.7%, fmod = CLK/21300 110: fdev = ±1.3%, fmod = CLK/1300 111: fdev = ±1.57%, fmod = CLK/1300 IF LFMODE = 1, then: 001: fdev = ±0.7%, fmod = CLK/625 010: fdev = ±1.3%, fmod = CLK/625 011: fdev = ±1.8%, fmod = CLK/625 100: fdev = ±2.2%, fmod = CLK/625 101: fdev = ±0.7%, fmod = CLK/385 110: fdev = ±1.2%, fmod = CLK/385 111: fdev = ±1.7%, fmod = CLK/385 www.national.com 32 DS92LV0411 / DS92LV0412

a 4.7 µF capacitor should be used for local device bypassing. are placed on the power lines for effective noise suppression. FIGURE 32. DS92LV0412 Typical Connection Diagram

TABLE 14. Serializer Alternate Color / Data Mapping

TABLE 15. Deserializer Alternate Color / Data Mapping be designed to provide low-noise power feed to the device. should be at least 5X the power supply voltage being used. planes, reducing the impedance at high frequency.

ing noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cas- es, an external filter many be used to provide clean power to sensitive circuits such as PLLs. Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely- coupled differential lines of 100 Ohms are typically recom- mended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise will appear as common- mode and thus is rejected by the receivers. The tightly cou- pled lines will also radiate less. Information on the LLP style package is provided in National Application Note: AN-1187. LVDS INTERCONNECT GUIDELINES See AN-1108 and AN-905 for full details.

• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings – S = space between the pair – 2S = space between pairs – 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above 500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as possible Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the National web site at: www.national.com/lvds 37 www.national.com DS92LV0411 / DS92LV0412

www.national.com 38 DS92LV0411 / DS92LV0412

Physical Dimensions inches (millimeters) unless otherwise noted 36–pin LLP Package (6.0 mm X 6.0 mm X 0.8 mm, 0.5 mm pitch) DS92LV0412 48–pin LLP Package (7.0 mm X 7.0 mm X 0.8 mm, 0.5 mm pitch) NS Package Number SQA48A 39 www.national.com DS92LV0411 / DS92LV0412

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