Interface

DS92LV0411SQ/NOPB

Texas Instruments

5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

Manufacturer: Texas Instruments

Document: 53 Pages / 1Mb

Request Quote Download Datasheet Read online HTML view

More from Texas Instruments Browse D parts

Online Datasheet

Read DS92LV0411SQ/NOPB online.

DS92LV0411_14 TI1 | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 53

Technical content

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 DS92LV0411/DS92LV04125-50MHzChannelLinkIISerializer/DeserializerwithLVDS ParallelInterface Check forSamples: DS92LV0411 ,DS92LV0412 1FEATURES DESCRIPTION The DS92LV0411 (serializer)and DS92LV0412 2• 5-Channel(4data+ 1 clock)Channel Link (deserializer)chipsettranslatesa Channel LinkLVDSLVDS ParallelInterfaceSupports 24-bitData videointerface(4 LVDS Data + LVDS Clock)intoa3-bitControlat5 – 50 MHz high-speedserializedinterfaceover a singleCML

AC Coupled STP Interconnectup to10 Meters pair. inLength The DS92LV0411/DS92LV0412 enablesapplications• IntegratedSerialCML Terminations that currentlyuse the popular Channel Link or
AT –SPEED BIST Mode and StatusPin Channel Linkstyledevicestoseamlesslyupgrade to an embedded clockinterfaceto reduce interconnect• OptionalI2C Compatible SerialControlBus costor ease designchallenges.The parallelLVDS• Power Down Mode MinimizesPower interfacealso reduces FPGA I/O pins,board traceDissipation countand alleviatesEMI issues,when compared to
1.8Vor 3.3VCompatible ControlPin Interface traditionalsingle-endedwidebus interfaces.
>8 kV ESD (HBM) Protection Programmable transmit de-emphasis, receive
-40° to+85°C Temperature Range equalization,on-chipscramblingand DC balancing enables longer distancetransmissionover lossySERIALIZER – DS92LV0411 cables and backplanes. The Deserializer• Data Scrambler forReduced EMI automaticallylocks to incoming data withoutan
DC –Balance Encoder forAC Coupling externalreferenceclock or specialsync patterns, providingeasy “plug-and-go”operation.• SelectableOutput VOD and AdjustableDe- Emphasis The DS92LV0411 and DS92LV0412 are programmable thoughan I2C interfaceas wellas byDESERIALIZER – DS92LV0412 pins.A built-inAT-SPEED BIST featurevalidateslink• Random Data Lock; No ReferenceClock integrityand may be used forsystemdiagnostics.Required The DS92LV0411 and DS92LV0412 can be used• AdjustableInputReceiverEqualization interchangeably with the DS92LV2411 or• EMI Minimizationon Output ParallelBus DS92LV2412. Thisallowsdesignersthe flexibilityto(SpreadSpectrum Clock Generationand LVDS connecttothehostdeviceand receivingdeviceswith VOD Select) differentinterfacetypes,LVDS orLVCMOS.

APPLICATIONS

Embedded Video and Display
Machine Vision,IndustrialImaging,Medical Imaging
OfficeAutomation — Printers,Scanners, Copiers
Securityand Video Surveillance
Generalpurpose datacommunication Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2010–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

RGB Style Display Interface Frame Grabber Or RGB Display QVGA to XGA 24-bit Color Depth DS92LV0411 DS92LV0412 High-Speed Serial Link

1 Pair/AC Coupled

SSC[2:0] VODSEL CONFIG[1:0] BISTEN OSSEL LFMODE VDDIO (1.8V or 3.3V) 1.8V CONFIG[1:0] Channel Link II Channel Link CMF Channel Link RxIN1+/- RxCLKIN+/- RxIN2+/- RxIN0+/- RxIN3+/- TxOUT1+/- TxCLKOUT+/- TxOUT2+/- TxOUT0+/- TxOUT3+/- 3.3V VDDIO (1.8V or 3.3V) 1.8V SDA ID[x] SCL OptionalSDA ID[x] SCL Optional Camera/AFE Or HOST Graphics Processor DOUT+ DOUT- RIN+ RIN- DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com ApplicationsDiagram

2 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

SSC[2:0] OEN VODSEL TxOUT[2]Error Detector PDB BISTEN CMF SCL SCA ID[x] TxOUT[1] TxOUT[0] TxCLKOUT OSS_SEL LFMODE EQ TxOUT[3] PDB DS92LV0411 PLL Timing and Control DOUT- DOUT+ Serial to ParallelParallel to Serial DC Balance Encoder De-Emph VODSEL RxIN3+/- SCL SCA ID[x] CONFIG[1:0] BISTEN Pattern Generator RxIN2+/- RxIN1+/- RxIN0+/- RxCLKIN+/- MAPSEL DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 Block Diagrams Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS92LV0411 DS92LV0412

CONFIG[1] VDDP RES1 RES2 VDDHS DOUT- DOUT+ VDDTX RES3 De-Emph VODSEL BISTEN RES7 RES4 DS92LV0411 (Top View) RxIN3+ RES6 ID[x] VDDL SCL SDA CONFIG[0] RES0 VDDIO PDB VDDRX MAPSEL RxIN1- RxIN0+ RxIN0- DAP = GND RxIN3- RxIN1+ RxCLKIN- RxIN2+ RxIN2- RxCLKIN+ RES5 DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com DS92LV0411 Pin Diagram Figure1. DS92LV0411 — Top View

4 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 Table1.DS92LV0411 PIN DESCRIPTIONS Pin Name Pin # I/O,Type Description Channel LinkParallelInputInterface RxIN[3:0]+ 2,33,31, I,LVDS TrueLVDS Data Input 29 These inputsrequirean external100 Ω differentialterminationforstandardLVDS levels. RxIN[3:0]- 1,34,32, I,LVDS InvertingLVDS Data Input 30,28 These inputsrequirean external100 Ω differentialterminationforstandardLVDS levels. RxCLKIN+ 35 I,LVDS TrueLVDS ClockInput These inputsrequirean external100 Ω differentialterminationforstandardLVDS levels. RxCLKIN- 34 I,LVDS InvertingLVDS ClockInput These inputsrequirean external100 Ω differentialterminationforstandardLVDS levels. Controland Configuration PDB 23 I,LVCMOS Power-down Mode Input w/ pull-down PDB = 1,Deviceisenabled(normaloperation). RefertoPOWER UP REQUIREMENTS AND PDB PIN intheApplicationsInformation Section. PDB = 0,Deviceispowered down When theDeviceisinthepower-down state,thedriveroutputs(DOUT+/-)arebothlogichigh, thePLL isshutdown,IDD isminimized.ControlRegistersareRESET . VODSEL 20 I,LVCMOS DifferentialDriverOutputVoltageSelect— PinorRegisterControl w/ pull-down VODSEL = 1,LVDS VOD is±450 mV, 900 mVp-p (typ)— Long Cable/De-E Applications VODSEL = 0,LVDS VOD is±300 mV, 600 mVp-p (typ) De-Emph 19 I,Analog De-Emphasis Control— PinorRegisterControl w/ pull-up De-Emph = open (float)-disabled To enableDe-emphasis,tiea resistorfromthispintoGND orcontrolviaregister. (See Table5) MAPSEL 26 I,LVCMOS ChannelLinkMap Select— PinorRegisterControl w/ pull-down MAPSEL = 1,MSB on RxIN3+/-.(SeeFigure23) MAPSEL = 0,LSB on RxIN3+/-.(See Figure22) CONFIG[1:0] 10,9 I,LVCMOS OperatingModes w/ pull-down Determinesthedeviceoperatingmode and interfacingdevice.(See Table2) CONFIG[1:0]= 00:InterfacingtoDS92LV2412 orDS92LV0412, ControlSignalFilter DISABLED CONFIG[1:0]= 01:InterfacingtoDS92LV2412 orDS92LV0412, ControlSignalFilter ENABLED CONFIG [1:0]= 10:InterfacingtoDS90UR124, DS99R124 CONFIG [1:0]= 11:InterfacingtoDS90C124 ID[x] 4 I,Analog SerialControlBus DeviceID AddressSelect— Optional ResistortoGround and 10 kΩ pull-upto1.8Vrail.(See Table11) SCL 6 I,LVCMOS SerialControlBus ClockInput-Optional SCL requiresan externalpull-upresistorto3.3V SDA 7 I/O,LVCMOS SerialControlBus Data Input/Output-Optional Open Drain SDA requiresan externalpull-upresistorto3.3V BISTEN 21 I,LVCMOS BIST Mode — Optional w/ pull-down BISTEN = 1,BIST isenabled BISTEN = 0,BIST isdisabled RES[7:0] 25,3,36, I,LVCMOS Reserved -tieLOW 27,18,13, w/ pull-down 12,8 Channel LinkIISerialInterface DOUT+ 16 O, CML TrueOutput. The outputmust be AC Coupledwitha 0.1μF capacitor. DOUT- 15 O, CML InvertingOutput. The outputmust be AC Coupledwitha 0.1μF capacitor. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS92LV0411 DS92LV0412

(Top View) GND VDDSC GND GND RIN- RIN+ VDDA RES VDDTX GND TxOUT3- TxCLKOUT+ TxOUT2- TxOUT1+ TxOUT0+ TxOUT0- GND CMF VDDA VDDSC TxOUT3+ TxCLKOUT- TxOUT2+ TxOUT1- PDB SSC[1] CONFIG[0] ID[x] SSC[0] OSS_SEL MAPSEL VODSEL GND VDDL OEN BISTEN PASS/EQ LOCK GND LFMODE SSC[2] VDDP CONFIG[1] VDDIO GND SDA SCL VDDL DAP = GND DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com Table1.DS92LV0411 PIN DESCRIPTIONS (continued) Pin Name Pin # I/O,Type Description Power and Ground (1) VDDL 5 Power LogicPower,1.8V ±5% VDDP 11 Power PLL Power,1.8V ±5% VDDHS 14 Power TX HighSpeed LogicPower,1.8V ±5% VDDTX 17 Power Output DriverPower, 1.8V ±5% VDDRX 24 Power RX Power,1.8V ±5% VDDIO 22 Power LVCMOS I/OPower and ChannelLinkI/OPower 1.8V ±5% OR 3.3V ±10% GND DAP Ground DAP isthelargemetalcontactatthebottomside,locatedatthecenteroftheWQFN package.Connect totheground plane(GND) withatleast9 vias. (1) 1= HIGH, 0 = LOW. The VDD (VDDn and VDDIO )supplyramp shouldbe fasterthan1.5ms witha monotonicrise.Ifslowerthen1.5ms thena capacitoron thePDB pinisneeded toensurePDB arrivesafteralltheVDD have settledtotherecommended operatingvoltage. DS92LV0412 Pin Diagram Figure2. DS92LV0412 — Top View

6 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 DS92LV0412 PIN DESCRIPTIONS Pin Name Pin # I/O,Type Description Channel LinkIISerialInterface RIN+ 40 I,CML TrueInput. The outputmust be AC Coupledwitha 0.1μF capacitor. RIN- 41 I,CML InvertingInput. The outputmust be AC Coupledwitha 0.1μF capacitor. CMF 42 I,Analog Common Mode Filter VCM centertapisa virtualgroundwhichcan be AC-coupledtogroundtoincreasereceiver common mode noiseimmunity.Recommended valueis4.7μF orhigher. Channel LinkParallelOutput Interface RxIN[3:0]+ 15,19,21,23 O, LVDS TrueLVDS Data Output RxIN[3:0]- 16,20,22,24 O, LVDS InvertingLVDS Data Output RxCLKIN+ 17 O, LVDS TrueLVDS ClockOutput RxCLKIN- 18 O, LVDS InvertingLVDS ClockOutput LVCMOS Outputs LOCK 27 O, LVCMOS LOCK StatusOutput LOCK = 1,PLL islocked,outputstateddeterminedby OEN. LOCK = 0,PLL isunlocked,outputstatesdeterminedby OSS_SEL and OEN. (See Table6) Controland Configuration PDB 1 I,LVCMOS Power-down Mode Input w/ pull-down PDB = 1,Deviceisenabled(normaloperation). PDB = 0,Deviceispowered down and theoutputsareTri-State ControlRegistersareRESET . VODSEL 33 I,LVCMOS ParallelLVDS DriverOutputVoltageSelect— PinorRegisterControl w/ pull-down VODSEL = 1,LVDS VOD is±400 mV, 800 mVp-p (typ)— Long Cable/De-E Applications VODSEL = 0,LVDS VOD is±250 mV, 500 mVp-p (typ) OEN 30 I,LVCMOS OutputEnable. w/ pull-down (See Table6) OSS_SEL 35 I,LVCMOS OutputSleepStateSelectInput. w/ pull-down (See Table6) LFMODE 36 I,LVCMOS SSCG Low FrequencyMode — PinorRegisterControl w/ pull-down LF_MODE = 1,lowfrequencymode (TxCLKOUT = 10–20 MHz) LF_MODE = 0,highfrequencymode (TxCLKOUT = 20–65 MHz) SSCG notavaialbleabove 65 MHz. MAPSEL 34 I,LVCMOS ChannelLinkMap Select— PinorRegisterControl w/ pull-down MAPSEL = 1,MSB on TxOUT3+/-.(See Figure23) MAPSEL = 0,LSB on TxOUT3+/-.(See Figure22) CONFIG[1 11,10 I,LVCMOS OperatingModes :0] w/ pull-down Determinethedeviceoperatingmode and interfacingdevice.(See Table2) CONFIG[1:0]= 00:InterfacingtoDS92LV2411 orDS92LV0411, ControlSignalFilter DISABLED CONFIG[1:0]= 01:InterfacingtoDS92LV2411 orDS92LV0411, ControlSignalFilter ENABLED CONFIG [1:0]= 10:InterfacingtoDS90UR241, DS99R421 CONFIG [1:0]= 11:InterfacingtoDS90C241 SSC[2:0] 7,2,3 I,LVCMOS Spread SpectrumClockGeneration(SSCG) Range Select w/ pull-down (See Table9 and Table10) RES 37 I,LVCMOS Reserved w/ pull-down Controland Configuration— STRAP PIN EQ 28 [PASS] STRAP EQ Gain ControlofChannelLinkIISerialInput I,LVCMOS EQ = 1,EQ gainisenabled(~13dB) w/ pull-down EQ = 0,EQ gainisdisabled(~1.625dB) Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com DS92LV0412 PIN DESCRIPTIONS (continued) Pin Name Pin # I/O,Type Description OptionalBIST Mode BISTEN 29 I,LVCMOS BIST Mode — Optional w/ pull-down BISTEN = 1,BIST isenabled BISTEN = 0,BIST isdisabled PASS 28 O, LVCMOS PASS Output(BISTMode) — Optional PASS =1,no errorsdetected PASS = 0,errorsdetected Leave open ifunused.Route toa testpoint(pad)recommended. OptionalSerialBus Control ID[x] 12 I,Analog SerialControlBus DeviceID AddressSelect— Optional ResistortoGround and 10 kΩ pull-upto1.8Vrail.(See Table11) SCL 5 I,LVCMOS SerialControlBus ClockInput-Optional Open Drain SCL requiresan externalpull-upresistorto3.3V. SDA 4 I/O,LVCMOS SerialControlBus Data Input/Output-Optional Open Drain SDA requiresan externalpull-upresistor3.3V. Power and Ground (1) VDDL 6,31 Power LogicPower,1.8V ±5% VDDA 38,43 Power AnalogPower,1.8V ±5% VDDP 8 Power PLL Power,1.8V ±5% VDDSC 46,47 Power SSC GeneratorPower,1.8V ±5%. Power must be connectedtothesepinsregardlessifthe SSCG featureisused ornot. VDDTX 13 Power Channel LinkLVDS ParallelOutput Power, 3.3V ±10% VDDIO 25 Power LVCMOS I/OPower and ChannelLinkI/OPower 1.8V ±5% OR 3.3V ±10% GND 9,14,26,32, Ground Ground 39,44,45,48 DAP DAP Ground DAP isthelargemetalcontactatthebottomside,locatedatthecenteroftheWQFN package.Connect totheground plane(GND) withatleast9 vias. (1) 1= HIGH, 0 = LOW. The VDD (VDDn and VDDIO )supplyramp shouldbe fasterthan1.5ms witha monotonicrise.Ifslowerthen1.5ms thena capacitoron thePDB pinisneeded toensurePDB arrivesafteralltheVDD have settledtotherecommended operatingvoltage.

8 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) SupplyVoltage– VDDn (1.8V) −0.3Vto+2.5V SupplyVoltage– VDDIO −0.3Vto+4.0V SupplyVoltage– VDDTX (1.8V,Ser)) −0.3Vto+2.5V SupplyVoltage– VDDTX (3.3V,Des) −0.3Vto+4.0V LVCMOS I/OVoltage −0.3Vto(VDDIO + 0.3V) LVDS InputVoltage −0.3Vto(VDDIO + 0.3V) LVDS OutputVoltage −0.3Vto(VDDTX + 0.3V) CML DriverOutputVoltage −0.3Vto(VDDn + 0.3V) ReceiverInputVoltage −0.3Vto(VDD + 0.3V) JunctionTemperature +150°C StorageTemperature −65°C to+150°C Maximum Power DissipationCapacityat25°C Derateabove 25°C 1/θJA°C/W θJA(with9 thermalvia) 27.4°C/W θJC(with9 thermalvia) 4.5°C/W Maximum Power DissipationCapacityat25°C Derateabove 25°C 1/θJA°C/W θJA(with9 thermalvia) 27.7°C/W θJC(with9 thermalvia) 3.0°C/W ESD Rating(IEC,powered-uponly),R D = 330Ω,C S = 150 pF AirDischarge (DOUT +,D OUT -,R IN+,R IN-) ≥±30 kV ContactDischarge (DOUT +,D OUT -,R IN+,R IN-) ≥±8 kV ESD Rating(HBM) ≥±8 kV ESD Rating(CDM) ≥±1.25kV ESD Rating(MM) ≥±250 V Forsolderingspecifications:http://www.ti.com/lit/SNOA549 (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur,includinginoperabilityand degradationof devicereliabilityand/orperformance.Functionaloperationofthedeviceand/ornon-degradationattheAbsoluteMaximum Ratingsor otherconditionsbeyond thoseindicatedintheRecommended OperatingConditionsisnotimplied.The Recommended Operating Conditionsindicateconditionsatwhichthedeviceisfunctionaland thedeviceshouldnotbe operatedbeyond such conditions. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com Recommended OperatingConditions Min Nom Max Units SupplyVoltage(VDDn ) 1.71 1.8 1.89 V SupplyVoltage(VDDTX_Ser ) 1.71 1.8 1.89 V SupplyVoltage(VDDTX_Des ) 3.0 3.3 3.6 V LVCMOS SupplyVoltage(VDDIO ) 1.71 1.8 1.89 V OR LVCMOS SupplyVoltage(VDDIO ) 3.0 3.3 3.6 V OperatingFreeAir Temperature(TA) −40 +25 +85 °C RxCLKIN/TxCLKOUT ClockFrequency 5 50 MHz SupplyNoise(1) 100 mV P-P (1) Supplynoisetestingwas done withminimum capacitorson thePCB. A sinusoidalsignalisAC coupledtotheVDDn (1.8V)supplywith amplitude= 100 mVp-p measured atthedeviceVDDn pins.BiterrorratetestingofinputtotheSer and outputoftheDes with10 meter cableshows no errorwhen thenoisefrequencyon theSer islessthan750 kHz.The Des on theotherhand shows no errorwhen the noisefrequencyislessthan400 kHz. DC ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2)(3)(4)(5) UniSymbol Parameter Conditions Pin/Freq. Min Typ Max ts DS92LV0411 LVCMOS INPUT DC SPECIFICATIONS VDDIO = 3.0to3.6V 2.2 VDDIO V VIH HighLevelInputVoltage 0.65*VDDIO = 1.71to1.89V VDDIO VVDDIO PDB,VDDIO = 3.0to3.6V GND 0.8 V VODSEL,VIL Low LevelInputVoltage 0.35*MAPSEL,VDDIO = 1.71to1.89V GND VVDDIOCONFIG[1:0], BISTENVDDIO = 3.0 −15 ±1 +15 μAto3.6V IIN InputCurrent VIN = 0V orVDDIO VDDIO = 1.7 −15 ±1 +15 μAto1.89V DS92LV0412 LVCMOS I/ODC SPECIFICATIONS VDDIO = 3.0to3.6V 2.2 VDDIO V VIH HighLevelInputVoltage 0.7*VDDIO = 1.71to1.89V VDDIO VVDDIOPDB, VODSEL,VDDIO = 3.0to3.6V GND 0.8 V OEN,VIL Low LevelInputVoltage 0.3*MAPSEL,VDDIO = 1.71to1.89V GND VVDDIOLFMODE, SSC[2:0],VDDIO = 3.0 −15 ±1 +15 μABISTENto3.6V IIN InputCurrent VIN = 0V orVDDIO VDDIO = 1.7 −10 ±1 +10 μAto1.89V (1) The ElectricalCharacteristicstableslistensuredspecificationsunderthelistedRecommended OperatingConditionsexceptas otherwisemodifiedorspecifiedby theElectricalCharacteristicsConditionsand/orNotes.Typicalspecificationsareestimationsonlyand arenotensured. (2) Typicalvaluesrepresentmost likelyparametricnorms atVDD = 1.8V,VDDIO = 3.3V,Ta = +25 °C, and attheRecommended Operation Conditionsatthetimeofproductcharacterizationand arenotensured. (3) Currentintodevicepinsisdefinedas positive.Currentoutofa devicepinisdefinedas negative.Voltagesarereferencedtoground exceptVOD, ΔVOD, VTH and VTL whicharedifferentialvoltages. (4) Specificationisensuredby characterizationand isnottestedinproduction. (5) Specificationisensuredby designand isnottestedinproduction.

10 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 DC ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2)(3)(4)(5) UniSymbol Parameter Conditions Pin/Freq. Min Typ Max ts VDDIO = 3.3V VDDIO – VDDIOIOH = -2mA 0.25 VOH HighLevelOutputVoltage V VDDIO = 1.8V VDDIO – VDDIOIOH = -2mA 0.2 VDDIO = 3.3V or1.8VVOL Low LevelOutputVoltage GND 0.2 VIOL = +0.5mA VDDIO = 3.0 LOCK, -45to3.6V PASS IOS OutputShortCircuitCurrent VOUT = 0V mA VDDIO = 1.71 -13to1.89V VDDIO = 3.0 -10 +10PDB = 0V,OSS_SEL to3.6V IOZ Tri-StateOutputCurrent(6) = 0V,VOUT = 0V or μA VDDIO = 1.71VDDIO -15 +15to1.89V DS92LV0411 CHANNEL LINK PARALLEL LVDS RECEIVER DC SPECIFICATIONS DifferentialThresholdHighVTH +100Voltage mV DifferentialThresholdLow VCM = 1.2V,(See Figure3)VTL −100Voltage RxIN[3:0]+/-, |VID| DifferentialInputVoltageSwing 200 600 mVRxCLKIN+/-, VDDIO = 3.3V 0 1.2 2.4 VCM Common Mode Voltage V VDDIO = 1.8V 0 1.2 1.55 IIN InputCurrent −15 ±1 +15 μA DS92LV0412 CHANNEL LINK PARALLEL LVDS DRIVER DC SPECIFICATIONS VODSEL = L 100 250 400 mV |VOD | DifferentialOutputVoltage VODSEL = H 200 400 600 mV mVVODSEL = L 500 p-pDifferentialOutputVoltageA –VODp-p B mVVODSEL = H 800R L = 100Ω p-pTxCLKOUT-, ΔVOD OutputVoltageUnbalance 4 50 mVTxOUT[3:0]+, TxOUT[3:0]-VODSEL = L 1.0 1.2 1.5 V VOS OffsetVoltage VODSEL = H 1.2 V ΔVOS OffsetVoltageUnbalance 1 50 mV IOS OutputShortCircuitCurrent VOUT = GND -5 mA OEN = GND,IOZ OutputTri-StateCurrent(6) -10 +10 μAVOUT = VDDTX ,orGND (6) When thedeviceoutputisatTri-StatetheDeserializerwilllosePLL lock.Resynchronization/Relockmust occurbeforedatatransfer requiretPLD Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com DC ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2)(3)(4)(5) UniSymbol Parameter Conditions Pin/Freq. Min Typ Max ts DS92LV0411 Channel LinkIICML DRIVER DC SPECIFICATIONS VODSEL = 0 ±225 ±300 ±375 VOD DifferentialOutputVoltage mV VODSEL = 1 ±350 ±450 ±550 R L = 100Ω, mVDe-emph = disabled, VODSEL = 0 600 p-pDifferentialOutputVoltage (SeeFigure5)VODp-p (DOUT+) – (DOUT-) mVVODSEL = 1 900 p-p R L = 100Ω,De-emph = disabled,ΔVOD OutputVoltageUnbalance 1 50 mVVODSEL = L DOUT+, DOUT-VODSEL = 0 1.65 VOffsetVoltage– Single-ended R L = 100Ω,VOS AtTP A & B,(SeeFigure4) De-emph = disabled VODSEL = 1 1.575 V OffsetVoltageUnbalance ΔVOS Single-ended R L = 100Ω,De-emph = disabled 1 mV AtTP A & B,(SeeFigure4) DOUT+/- = 0V,IOS OutputShortCircuitCurrent VODSEL = 0 −35 mADe-emph = disabled R T InternalTerminationResistor 80 120 Ω DS92LV0412 CHANNEL LINK IICML RECEIVER DC SPECIFICATIONS DifferentialInputThresholdVTH VCM = +1.2V (InternalVBIAS) +50 mVHighVoltage DifferentialInputThresholdLowVTL -50 mVRIN+,Voltage RIN- Common mode Voltage,VCM 1.2 VInternalVBIAS R T InputTermination 80 100 120 Ω DS92LV0411 SUPPLY CURRENT IDDT1 CheckerBoard VDD = 1.89V AllVDD pins 80 90 mA Pattern, VDDIO = 1.89V 3 5 mADe-emph = 3 kΩ, IDDIOT1 VDDIOVODSEL = H, (See VDDIO = 3.6V 10 13 mASupplyCurrent Figure18) (includesloadcurrent) IDDT2 CheckerBoard VDD = 1.89V AllVDD pins 75 85 mAR L = 100Ω,f= 50 MHz Pattern, VDDIO = 1.89V 3 5 mADe-emph = 6 kΩ, IDDIOT2 VDDIOVODSEL = L,(See VDDIO = 3.6V 10 13 mAFigure18) IDDZ VDD = 1.89V AllVDD pins 60 1000 µA PDB = 0V ,(AllotherSupplyCurrentPower-down VDDIO = 1.89V 0.5 10 µALVCMOS Inputs= 0V)IDDIOZ VDDIO VDDIO = 3.6V 1 30 µA DS92LV0412 SUPPLY CURRENT IDD1 SupplyCurrent CheckerBoard VDDn = 1.89 AllVDD(1:8) 85 95 mA (Includesloadcurrent) Pattern, V pins 50 MHz Clock VODSEL = H,IDDTX1 VDDTX = 3.6 VDDTX 40 50 mASSCG [2:0]= 000 V IDDIO1 VDDIO = 1.89 VDDIO 0.3 0.8 mA V VDDIO = 3.6V 0.8 1.5 mA

12 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 DC ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2)(3)(4)(5) UniSymbol Parameter Conditions Pin/Freq. Min Typ Max ts IDD2 SupplyCurrent CheckerBoard VDDn = 1.89 AllVDD(1:8) 95 mA (Includesloadcurrent) Pattern, V pins 50 MHz Clock VODSEL = H,IDDTX2 VDDTX = 3.6 VDDTX 40 mASSCG [2:0]= 111 V IDDIO2 VDDIO = 1.89 VDDIO 0.3 mA V VDDIO = 3.6V 0.8 mA IDDZ SupplyCurrentPower Down PDB = 0V, VDD = 1.89V AllVDD(1:8) 0.15 2 mA AllotherLVCMOS pins Inputs= 0VIDDTXZ VDDTX = 3.6 VDDTX 0.01 0.1 mA V IDDIOZ VDDIO = 1.89 VDDIO 0.01 0.08 mA V VDDIO = 3.6V 0.01 0.08 mA SwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units DS92LV0411 CHANNEL LINK PARALLEL LVDS INPUT tRSP0 ReceiverStrobePosition-bit0 0.66 1.10 1.54 ns tRSP1 ReceiverStrobePosition-bit1 2.86 3.30 3.74 ns tRSP2 ReceiverStrobePosition-bit2 5.05 5.50 5.93 nsRxCLKIN = 50 MHz, tRSP3 ReceiverStrobePosition-bit3 RxIN[3:0] 7.25 7.70 8.13 ns (See Figure7)tRSP4 ReceiverStrobePosition-bit4 9.45 9.90 10.33 ns tRSP5 ReceiverStrobePosition-bit5 11.65 12.10 12.53 ns tRSP6 ReceiverStrobePosition-bit6 13.85 14.30 14.73 ns DS92LV0412 CHANNEL LINK PARALLEL LVDS OUTPUT tLHT Low toHighTransitionTime R L = 100Ω 0.3 0.6 ns tTHLT HightoLow TransitionTime 0.3 0.6 ns tDCCJ Cycle-to-CycleOutputJitter(1) TxCLKOUT ± = 5 MHz 900 2100 ps TxCLKOUT ± = 50 MHz 75 125 ps tTTP1 TransmitterPulsePositionforbit1 5 – 50 MHz 1 UI(2) tTTP0 TransmitterPulsePositionforbit0 2 UI tTTP6 TransmitterPulsePositionforbit6 3 UI tTTP5 TransmitterPulsePositionforbit5 4 UI tTTP4 TransmitterPulsePositionforbit4 5 UI tTTP3 TransmitterPulsePositionforbit3 6 UI tTTP2 TransmitterPulsePositionforbit2 7 UI ΔtTTP OffsetTransmitterPulsePosition(bit 50 MHz <+0.1 UI 6— bit0) tDD Delay-Latency 142*T 143*T ns tTPDD Power Down Delay 50 MHz 7 12 nsActivetoOFF tTXZR EnableDelay 50 MHz 40 55 nsOFF toActive (1) tDCCJ isthemaximum amount ofjitterbetween adjacentclockcycles. (2) UI – UnitIntervalisequivalenttoone serializeddatabitwidth(1UI= 1 /28*PCLK).The UI scaleswithPCLK frequency. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com SwitchingCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units DS92LV0411 Channel LinkIICML OUTPUT tHLT OutputLow-to-HighTransitionTime R L = 100Ω,De-emphasis= disabled, 200 ps(See Figure5) VODSEL = 0 R L = 100Ω,De-emphasis= disabled, 200 psVODSEL = 1 tHLT OutputHigh-to-LowTransitionTime R L = 100Ω,De-emphasis= disabled, 260 ps(See Figure6) VODSEL = 0 R L = 100Ω,De-emphasis= disabled, 200 psVODSEL = 1 tXZD Ouput ActivetoOFF Delay(See 5 15 nsFigure11) tPLD PLL Lock Time(3),(See Figure9) R L = 100Ω 1.5 10 ms tSD Delay-Latency,(See Figure12) R L = 100Ω 147*T 148*T ns tDJIT OutputTotalJitter(See Figure14) R L = 100Ω,De-Emph = disabled, RANDOM pattern, 0.26 UI RxCLKIN = 43 and 50 MHz λSTXBW JitterTransfer RxCLKIN = 43 MHz 2.2 MHzFunction-3dB Bandwidth RxCLKIN = 50 MHz 2.6 δSTX JitterTransfer RxCLKIN = 43 MHz 1 dBFunctionPeaking RxCLKIN = 50 MHz 1 DS92LV0412 CHANNEL LINK IICML INPUT tDDLT Lock Time SSCG[2:0]= 000, 7 ms

5 MHz

SSCG[2:0]= 111, 14 ms SSCG[2:0]= 000, 6 ms

50 MHz

SSCG[2:0]= 111, 8 ms tIJIT InputJitterTolerance EQ = OFF >0.9 UI SSCG[2:0]= 000 TxCLKOUT ± = 50 MHz InputJitterFrequency< 2 MHz EQ = OFF >0.5 UI SSCG[2:0]= 000 TxCLKOUT ± = 50 MHz InputJitterFrequency>6 MHz DS92LV0412 LVCMOS OUTPUTS tCLH Low toHighTransitionTime C L = 8 pF 5 15 ns LOCK pin,tCHL HightoLow TransitionTime 5 15 nsPASS pin tPASS BIST PASS ValidTime, PASS pin 570 580 ns BISTEN = 1 5 MHz

50 MHz 50 65 ns

tDEV Spread SpectrumClockingDeviation TxCLKOUT = 5 – 50 MHz, ±0.5 ±2 % Frequency SSC[2:0]= ON tMOD Spread SpectrumClocking TxCLKOUT = 5 – 50 MHz, 8 100 kHz ModulationFrequency SSC[2:0]= ON (3) tPLD isthetimerequiredby thedevicetoobtainlockwhen exitingpower-down statewithan activeRxCLKIN.

14 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 Recommended Timing fortheSerialControlBus Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(Figure20) Symbol Parameter Conditions Min Typ Max Units fSCL SCL ClockFrequency StandardMode >0 100 kHz FastMode >0 400 kHz tLOW SCL Low Period StandardMode 4.7 μs FastMode 1.3 μs tHIGH SCL HighPeriod StandardMode 4.0 μs FastMode 0.6 μs tHD:STA Holdtimefora startora StandardMode 4.0 μs repeatedstartcondition FastMode 0.6 μs tSU:STA SetUp timefora startora StandardMode 4.7 μs repeatedstartcondition FastMode 0.6 μs tHD:DAT Data HoldTime 0 3.45 μs FastMode 0 0.9 μs tSU:DAT Data SetUp Time StandardMode 250 μs FastMode 100 μs tSU:STO SetUp Time forSTOP StandardMode 4.0 μs Condition FastMode 0.6 μs tBUF Bus FreeTime Between STOP StandardMode 4.7 μs and START FastMode 1.3 μs tr SCL & SDA RiseTime StandardMode 1000 ns FastMode 300 ns tf SCL & SDA FallTime StandardMode 300 ns FastMode 300 ns DC and AC SerialControlBus Characteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified. Symbol Parameter Conditions Min Typ Max Units VIH InputHighLevel SDA and SCL 0.7* VDDIO VVDDIO = 3.3V VDDIO VIL InputLow LevelVoltage SDA and SCL 0.3*GND VVDDIO = 3.3V VDDIO VHY InputHysteresis VDDIO = 3.3V >50 mV VOL SDA, IOL = 3mA 0 0.36 VVDDIO = 3.3V Iin SDA orSCL, Vin= 3.3VorGND -10 +10 µA tR SDA RiseTime– READ SDA, RPU = X,Cb ≤ 400pF,(See Figure20) 430 ns tF SDA FallTime – READ 20 ns tSU;DAT SetUp Time – READ See Figure20 560 ns tHD;DAT HoldUp Time – READ See Figure20 615 ns tSP InputFilter 50 ns C in InputCapacitance SDA orSCL <5 pF Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:DS92LV0411 DS92LV0412

+VOD -VOD tLHLTtLLHT (DOUT+) - (DOUT-) 20% 80% D OUT+ D OUT- (DOUT+ ) - (DOUT+ ) GND VOD+ VOD- VOS VODp-p VOD+ VOD- Single-EndedDifferential A B C A C B 50: 50: 50:50: Scope VCM=1.2V GND RxIN[3:0]+ RxCLKIN+ RxIN[3:0]- RxClkIN- VTH VTL DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com AC Timing Diagrams and TestCircuits Figure3. Channel LinkDC VTH/VTL Definition Figure4. DS92LV0411 Output TestCircuit Figure5. Channel LinkIISingle-endedand DifferentialWaveforms Figure6. DS92LV0411 Output TransitionTimes

16 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 Figure7. DS92LV0411 LVDS ReceiverStrobePositions Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:DS92LV0411 DS92LV0412

(Diff.) "X" active tPLD Driver OFF, VOD = 0V Driver On TxCLKOUT± tTTP1 bit 1TxOUT[3:0]± bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tTTP2 tTTP3 tTTP4 tTTP5 tTTP6 1UI Cycle N tTTP7 2UI 3UI 4UI 5UI 6UI 7UI DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com Figure8. DS92LV0412 LVDS TransmitterPulse Positions Figure9. DS92LV0411 Lock Time

18 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

DCA, DCB RxCLKIN tSD NN-1 N+1 N+2 | | RxIN[3:0] PDB VILMA X RxCLKIN DOUT (Diff.) "X"active tXZD active Driver OFF, VOD = 0V R IN± TRI-STATELOCK PDB VOH(min) tDDLT VIH(min) DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 Figure10. DS92LV0412 Lock Time Figure11. DS92LV0411 DisableTime Figure12. DS92LV0411 Latency Delay Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:DS92LV0411 DS92LV0412

(Diff.) tDJIT VOD (+) tBIT (1 UI) TxOUT_E_O VOD (-) tDJIT START BIT STOP BITSYMBOL N+3 START BIT STOP BITSYMBOL N+2 START BIT STOP BITSYMBOL N+1 START BIT STOP BITSYMBOL N R IN+/- TxCLKOUT tRD TxOUT[3:0] SYMBOL N-1 SYMBOL NSYMBOL N-2SYMBOL N-3 DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com Figure13. DS92LV0412 Latency Delay Figure14. DS92LV0411 Output Jitter

20 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

X PDB RIN LOCK PASS TxCLKOUT TxOUT[3:0] Z Z Z Z VILmax active serial stream X PDB RIN (Diff.) LOCK TxOUT[3:0] TxCLKOUT PASS OFFOFF Active ActiveOSC Output L H L H L Z Z Z Z CONDITIONS: OEN = H, OSS_SEL = H, and OSC_SEL not equal to 000. ff Z OSC Output Z ZZ DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 Figure15. DS92LV0412 Output StateDiagram Figure16. DS92LV0412 Power Down Delay Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:DS92LV0411 DS92LV0412

(w/ errors) tPASS Prior BIST Result Current BIST Test - Toggle on Error Result Held VOL MAX RxIN[odd] RxCLKIN RxIN[even] +V OD -VOD +V OD -VOD +V OD -VOD Cycle N Cycle N+1 tTXZR OEN LOCK TxCLKOUT TxOUT[3:0] Z Z VIHmin PDB DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com Figure17. DS92LV0412 Enable Delay Figure18. Checkerboard Data Pattern Figure19. BIST PASS Waveform

22 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

tHD;STA tLOW tr tHD;DAT tHIGH tf tSU;DAT tSU;STA tSU;STO tf START REPEATED START STOP tHD;STA START tSP tr BUFt DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 Figure20. SerialControlBus Timing Diagram Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:DS92LV0411 DS92LV0412

C C DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com FUNCTIONAL DESCRIPTION The DS92LV0411 /DS92LV0412 chipsettransmitsand receives24-bitsofdataand 3 controlsignals,formatted as Channel LinkLVDS data,overa singleserialCML pairoperatingat140 Mbps to1.4Gbps seriallinerate. The serialstream containsan embedded clock,videocontrolsignalsand isDC-balance to enhance signal qualityand supportsAC coupling. The Des can attainlocktoa datastreamwithouttheuse ofa separatereferenceclocksource,whichsimplifies system complexityand overallcost.The Des also synchronizesto the Ser regardlessof the data pattern, deliveringtrueautomatic“plugand lock”performance.Itcan locktotheincomingserialstreamwithouttheneed ofspecialtrainingpatternsorsync characters.The Des recoverstheclockand databy extractingtheembedded clockinformation,validatingand thendeserializingtheincomingdatastreamprovidinga parallelChannel Link LVDS bus tothedisplay,ASIC,orFPGA. The DS92LV0411 / DS92LV0412 chipsetcan operatewithup to 24 bitsof raw data withthreeslowerspeed controlbitsencoded withintheserialdatastream.For applicationsthatrequirelessthemaximum 24 pclkspeed bitspaces,theuserwillneed toensurethatallunused bitspacesorparallelLVDS channelsaresettovalidlogic states,as allparallellanesand 27 bitspaceswillalwaysbe sampled. BlockDiagramsforthechipsetareshown atthebeginningofthisdatasheet. PARALLEL LVDS DATA TRANSFER The DS92LV0411/DS92LV0412 can be configuredto accept/transmit24-bitdata with 2 differentmapping schemes: The normalChannel LinkLVDS format(MSBs on LVDS channel3)can be selectedby configuringthe MAPSEL pintoHIGH. See Figure15 forthenormalChannel LinkLVDS mapping.An alternatemapping scheme isavailable(LSBs on LVDS channel3)by configuringtheMAPSEL pintoLOW. See Figure16 forthealternate LVDS mapping.The mapping schemes can alsobe selectedby registercontrol. The alternatemapping scheme isusefulinsome applicationswhere the receivingsystem,typicallya display, requiresthattheLSBs forthe24-bitcolordatabe senton LVDS channel3. SERIAL DATA TRANSFER The DS92LV0411 transmitsa 24–bitword ofdatainthefollowingformat:C1 and C0 representtheembedded clockintheserialstream.C1 isalwaysHIGH and C0 isalwaysLOW. b[23:0]containthescrambledRGB data, plustwo additionalbitsforencodingoverhead.The controlsignals(VS,HS,DE) are alsoencoded withinthese two additionalbits.This coding scheme is generated by the DS92LV0411 and decoded by the paring deserializer,such as theDS92LV0412, automatically. The DS92LV0412 receivesa 24 bitword ofdataintheformatas describedabove.Italsosynchronizestothe serializerregardlessofthedatapattern,deliveringtrueautomatic“plugand lock”performance.itcan locktothe incomingserialstream withoutthe need forspecialtrainingpatternsor sync characters.The DS92LV0412 recoverstheclockand databy extractingtheembedded clockinformation,validatingand thendeserializingthe incomingdatastream. Figure21 illustratestheserialstreamperPCLK cycle. Figure21. Channel LinkIISerialStream

24 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 OPERATING MODES AND BACKWARD COMPATIBILITY (CONFIG[1:0]) The DS92LV0411 and DS92LV0412 are backward compatiblewith previous generationsof Ser/Des. Configurationmodes are providedforbackwards compatibilitywiththe DS90C241/DS90C124 and also the DS90UR241/DS90UR124 and DS99R241/DS99R124 by settingtherespectivemode withtheCONFIG[1:0]pins as shown inTable2 and Table3.The selectionalsodeterminewhethertheVideoControlSignalfilterfeatureis enabledordisabledinNormal mode. Backward compatibilitymodes areselectablethroughthecontrolpinsonly. The ControlSignalFiltercan be selectedby pinorthroughregisterprogramming. Table2. DS92LV0411 ConfigurationModes CON CON Mode Des Device FIG1 FIG0 L L Normal Mode, ControlSignalFilterdisabled DS92LV0412, DS92LV2412 L H Normal Mode, ControlSignalFilterenabled DS92LV0412, DS92LV2412 H L Backwards Compatible DS90UR124, DS99R124 H H Backwards Compatible DS90C124 Table3. DS92LV0412 ConfigurationModes CON CON Mode Des Device FIG1 FIG0 L L Normal Mode, ControlSignalFilterdisabled DS92LV0411, DS92LV2411 L H Normal Mode, ControlSignalFilterenabled DS92LV0411, DS92LV2411 H L Backwards Compatible DS90UR241, DS99R421 H H Backwards Compatible DS90C241 BIT MAPPING SELECT The DS92LV0411 and DS92LV0412 can be configuredtoaccepttheLVDS paralleldatawith2 differentmapping schemes: LSBs on RxIN[3]shown inFigure22 orMSBs on RxIN[3]shown inFigure23.The userselectswhich mapping scheme iscontrolledby MAPSEL pinorby Register. NOTE WhiletheLVDS interfacehas 28 bitsdefined,only27 bitsare recoveredby theSer and senttotheDes. Thissupports24 bitRGB plusthethreevideocontrolsignals.The 28th bitisnotsampled,sentorrecovered. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:DS92LV0411 DS92LV0412

R[6] (bit 21) R[7] (bit 22) R[0] (bit 0) R[1] (bit 1) R[2] (bit 2) R[3] (bit 3) R[4] (bit 4) R[5] (bit 5) G[6] (bit 23) G[7] (bit 24) G[0] (bit 6) G[1] (bit 7) G[2] (bit 8) G[3] (bit 9) G[4] (bit 10) G[5] (bit 11) B[6] (bit 25) B[7] (bit 26) B[0] (bit 12) B[1] (bit 13) B[2] (bit 14) B[3] (bit 15) B[4] (bit 16) B[5] (bit 17) HS (bit 18) VS (bit 19) DE (bit 20) Previous cycle Current cycle RxCLKIN +/- RxIN3 +/- RxIN2 +/- RxIN1 +/- RxIN0 +/- R[0] (bit 21) R[1] (bit 22) R[2] (bit 0) R[3] (bit 1) R[4] (bit 2) R[5] (bit 3) R[6] (bit 4) R[7] (bit 5) G[0] (bit 23) G[1] (bit 24) G[2] (bit 6) G[3] (bit 7) G[4] (bit 8) G[5] (bit 9) G[6] (bit 10) G[7] (bit 11) B[0] (bit 25) B[1] (bit 26) B[2] (bit 12) B[3] (bit 13) B[4] (bit 14) B[5] (bit 15) B[6] (bit 16) B[7] (bit 17) HS (bit 18) VS (bit 19) DE (bit 20) Previous cycle Current cycle RxCLKIN +/- RxIN3 +/- RxIN2 +/- RxIN1 +/- RxIN0 +/- DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com Figure22. 8–bitChannel LinkMapping: LSB 's on RxIN3 Figure23. 8–bitChannel LinkMapping: MSB 's on RxIN3

26 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 VIDEO CONTROL SIGNAL FILTER The threecontrolbitscan be used tocommunicate any low speed signal.The most common use forthesebitsis inthedisplayormachine visionapplications.Ina displayapplicationthesebitsaretypicallyassignedas:Bit26 – DE, Bit24 – HS, Bit25 – VS. Inthemachine visionstandard,Camera Link,thesebitsaretypicallyassigned:Bit 26 – DVAL, Bit24 – LVAL, Bit25 – FVAL. When operatingthe devicesin Normal Mode, the Video ControlSignals(DE, HS, VS) have the following restrictions:

Normal Mode withControlSignalFilterEnabled: – DE and HS — Only 2 transitionsper 130 clockcyclesare transmitted,the transitionpulsemust be 3 PCLK orlonger.
Normal Mode withControlSignalFilterDisabled: – DE and HS — Only 2 transitionsper130 clockcyclesaretransmitted,no restrictionon minimum transition pulse.
VS — Only1 transitionper130 clockcyclesaretransmitted,minimum pulsewidthis130 clockcycles. Video ControlSignalsare definedas low frequencysignalswithlimitedtransitions.Glitchesofa controlsignal can cause a visualdisplayerror.Thisfeatureallowsforthechipsettovalidateand filteroutany highfrequency noiseon thecontrolsignals.See Figure24. Figure24. Video ControlSignalFilterWavefrom SERIALIZER FUNCTIONAL DESCRIPTION The Ser convertsa Channel LinkLVDS clockand databus (4LVDS datachannels+ 1 LVDS clock)toa single serialoutputdatastream,and alsoactsas a signalgeneratorforthechipsetBuiltInSelfTest(BIST)mode. The devicecan be configuredviaexternalpinsorthroughtheoptionalserialcontrolbus.The Ser featuresenhanced signalqualityon thelinkby supporting:a selectableVOD level,a selectablede-emphasissignalconditioningand alsotheChannel LinkIIdatacodingthatprovidesrandomization,scrambling,and DC Balanacingofthedata. The Ser includesmultiplefeaturestoreduceEMI associatedwithdisplaydatatransmission.Thisincludesthe randomizationand scramblingoftheserialdataand alsothesystem spreadspectrumclocksupport.The Ser featurespower savingfeatureswitha sleepmode, auto stop clockfeature,and optional1.8 V or 3.3V I/O compatibility. See alsotheFunctionalDescriptionofthechipset'sserialcontrolbus and BIST modes. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com EMI REDUCTION FEATURES Data Randomization & Scrambling Channel LinkIISer /Des featurea 3 stepencodingprocesswhichenablestheuse ofAC coupledinterconnects and also helps to manage EMI. The serializerfirstpasses the paralleldata througha scramblerwhich randomizesthedata.The randomizeddataisthenDC balanced.The DC balancedand randomizeddatathen goes througha bitshufflingcircuitand istransmittedout on the serialline.This encodingprocesshelpsto preventstaticdata patternson the serialstream.The resultingfrequencycontentof the serialstream ranges from the parallelclockfrequencyto the nyquistrate.For example,ifthe Ser / Des chipsetisoperatingat a parallelclockfrequencyof50 MHz, theresultingfrequencycontentofserialstreamrangesfrom50 MHz to700 MHz (50 MHz *28bits= 1.4Gbps /2 = 700 MHz ). Ser — Spread Spectrum Compatibility The RxCLKIN of the Channel Linkinputiscapableof trackingspread spectrumclocking(SSC) from a host source.The RxCLKIN willaccept spread spectrum trackingup to 35kHz modulationand ±0.5,±1 or ±2% deviations(centerspread).The maximum conditionsforthe RxCLKIN inputare:a modulationfrequencyof 35kHz and amplitudedeviationsof±2% (4% total). SER — INTEGRATED SIGNAL CONDITIONING FEATURES Ser — VOD Select(VODSEL) The DS92LV0411 differentialoutputvoltagemay be increasedby settingtheVODSEL pinHigh.When VODSEL isLow, theDC VOD isatthestandard(default)level.When VODSEL isHigh,theDC VOD isincreasedinlevel. The increasedVOD is usefulin extremelyhigh noise environmentsand also on extralong cable length applications.When using de-emphasis itis recommended to set VODSEL = H to avoid excessivesignal attenuationespeciallywiththelargerde-emphasissettings.Thisfeaturemay be controlledby theexternalpinor by register. Table4. Ser — DifferentialOutput Voltage Input Effect VOD VODVODSEL mV mVp-p H ±450 900 L ±300 600 Ser — De-Emphasis (De-Emph) The De-Emph pincontrolstheamount ofde-emphasisbeginningone fullbittimeaftera logictransitionthatthe devicedrives.Thisisusefultocounteractloadingeffectsoflongorlossycables.Thispinshouldbe leftopen for standardswitchingcurrents(node-emphasis)orifcontrolledby register.De-emphasisisselectedby connecting a resistoron thispintoground,withR valuebetween 0.5kΩ to1 M Ω,or by registersetting.When usingDe- Emphasis itisrecommended tosetVODSEL = H. Table5. De-Emphasis ResistorValue ResistorValue (kΩ) De-Emphasis Setting Open Disabled 0.6 -12 dB 1.0 -9 dB 2.0 -6 dB 5.0 -3 dB

28 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

1.0E+02 R VALUE - LOG SCALE (:) -14.00 -12.00 -10.00 -8.00 -6.00 -4.00 -2.00 0.00 DE-EMPH (dB) VDD = 1.8V, TA = 25oC DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 Figure25. De-Emph vs.R value POWER SAVING FEATURES Ser — Power Down Feature(PDB) The DS92LV0411 has a PDB inputpintoENABLE or POWER DOWN thedevice.Thispiniscontrolledby the hostand isused tosave power,disablingthelinkwhen thedisplayisnotneeded.InthePOWER DOWN mode, thehigh-speeddriveroutputsare bothpulledtoVDD and presenta 0V VOD state.Note – inPOWER DOWN, theoptionalSerialBus ControlRegistersareRESET . Ser — Stop Clock Feature The DS92LV0411 willentera low power SLEEP statewhen the RxCLKIN isstopped.A STOP conditionis detectedwhen theinputclockfrequencyislessthan3 MHz. The clockshouldbe heldata staticLow or high state.When theRxCLKIN startsagain,thedevicewillthenlocktothevalidinputRxCLKIN and thentransmits theRGB datatothedesializer.Note – inSTOP CLOCK SLEEP, theoptionalSerialBus ControlRegistersvalues areRETAINED . 1.8Vor 3.3VVDDIO Operation The DS92LV0411 parallelcontrolpinbus can operatewith1.8V or 3.3V levels(VDDIO ) forhostcompatibility. The 1.8V levelswilloffera systempower savings. OPTIONAL SERIAL BUS CONTROL Pleasesee thefollowingsectionon theOptionalSerialBus ControlInterface. OPTIONAL BIST MODE Pleasesee thefollowingsectionon thechipsetBIST Mode fordetails. Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com DeserializerFunctionalDescription The Des convertsa singleinputserialdata stream to a wide paralleloutputbus,and alsoprovidesa signal check forthechipsetBuiltInSelfTest(BIST)mode. The devicecan be configuredviaexternalpinsand strap pinsor throughthe optionalserialcontrolbus. The Des featuresenhance signalqualityon the linkwithan integratedequalizeron the serialinputand Channel Link IIdata encoding which providesrandomization, scrambling,and DC balanacingofthedata.The Des includesmultiplefeaturestoreduceEMI associatedwith datatransmission.Thisincludestherandomizationand scramblingofthedata,theoutputspreadspectrumclock generation(SSCG) support.The Des featurespower savingfeatureswitha power down mode, and optional LVCMOS (1.8V) interfacecompatibility. OSCILLATOR OUTPUT — OPTIONAL The DS92LV0412 providesan optionalTxCLKOUT when theinputclock(serialstream)has been lost.Thisis based on an internaloscillator.The frequencyoftheoscillatormay be selected.Thisfeaturemay be controlled by theexternalpinorthroughtheregisters. Clock-DATA RECOVERY STATUS FLAG (LOCK), OUTPUT ENABLE (OEN) and OUTPUT STATE SELECT (OSS_SEL) When PDB isdrivenHIGH, theCDR PLL beginslockingtotheserialinput,LOCK isLOW and theChannel Link interfacestateisdeterminedby thestateoftheOSS_SEL pin. Afterthe DS92LV0412 completesitslocksequence to the inputserialdata,the LOCK outputisdrivenHIGH, indicatingvaliddata and clockrecoveredfrom the serialinputisavailableon the Channel Linkoutputs.The TxCLKOUT outputisheldatitscurrentstateatthechange fromOSC_CLK (ifthisisenabledviaOSC_SEL) to the recoveredclock(orviceversa).Note thatthe Channel Linkoutputsmay be heldinan inactivestate(Tri- State® )throughtheuse oftheOutputEnablepin(OEN). Ifthereisa lossof clockfrom the inputserialstream,LOCK isdrivenLOW and the stateof the outputsare based on theOSS_SEL setting(configurationpinorregister). Table6. Des Output StateTable INPUTS OUTPUTS PDB OEN OSS_SEL LOCK OTHER OUTPUTS L X X X TxCLKOUT isTri-State TxOUT[3:0]areTri-State PASS isTri-State L X L L TxCLKOUT isTri-State TxOUT[3:0]areTri-State PASS isHIGH H L H L TxCLKOUT isTri-State TxOUT[3:0]areTri-State PASS isTri-State H H H L TxCLKOUT isTri-StateorOSC OutputthroughRegisterbit TxOUT[3:0]areTri-State PASS isTri-State H L X H TxCLKOUT isTri-State TxOUT[3:0]areTri-State PASS isHIGH H H X H TxCLKOUT isActive TxOUT[3:0]areActive PASS isActive (Normaloperatingmode)

30 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 DES — INTEGRATED SIGNAL CONDITIONING FEATURES — DES Des — Common Mode FilterPin (CMF) — Optional The Des providesaccesstothecentertapoftheinternaltermination.A capacitormay be placedon thispinfor additionalcommon-mode filteringof the differentialpair.This can be usefulin high noiseenvironmentsfor additionalnoiserejectioncapability.A 0.1μF capacitormay be connectedtothispintoGround. Des — InputEqualizerGain (EQ) The Des can enablereceiverinputequalizationoftheserialstreamtoincreasetheeye openingtotheDes input. Note thisfunctioncannot be seen at the RxIN+/-input.The equalizationfeaturemay be controlledby the externalpinorby register. Table7. ReceiverEqualizationConfigurationTable EQ (StrapOption) Effect L ~1.5dB H ~13 dB EMI REDUCTION FEATURES Des — VOD Select(VODSEL) The differentialoutputvoltageoftheChannelLinkinterfaceiscontrolledby theVODSEL input. Table8. Des — DifferentialOutput VoltageTable VODSEL Result L VOD is250 mV TYP (500mVp-p) H VOD is400 mV TYP (800mVp-p) Des — SSCG Generation— Optional The Des providesan internallygeneratedspreadspectrumclock(SSCG) tomodulateitsoutputs.Both clockand dataoutputsaremodulated.Thiswillaidtolowersystem EMI. OutputSSCG deviationsto±2% (4% total)atup to 100 kHz modulationsisavailable.See SwitchingCharacteristicsTable. Thisfeaturemay be controlledby externalSTRAP pinsorby register.The LFMODE settingshouldbe setappropriatelyiftheSSCG isbeingused. Set LFMODE HIGH ifthe clockfrequencyisbetween 5 MHz and 20 MHz. Set LFMODE LOW ifteh clock frequencyisbetween 20 MHz and 50 MHz. Table9. SSCG Configuration(LF_MODE = L)— Des Output SSC[2:0]Inputs Result LF_MODE = L (20— 55 MHz) SSC2 SSC1 SSC0 fdev(%) fmod (kHz) L L L OFF OFF L L H ±0.9 CLK/2168 L H L ±1.2 L H H ±1.9 H L L ±2.3 H L H ±0.7 CLK/1300 H H L ±1.3 H H H ±1.7 Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:DS92LV0411 DS92LV0412

fdev(max)FPCLK+ Frequency Time FPCLK- FPCLK fdev(min) 1/fmod DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com Table10. SSCG Configuration(LF_MODE = H) — Des Output SSC[2:0]Inputs Result LF_MODE = H (5— 20 MHz) SSC2 SSC1 SSC0 fdev(%) fmod (kHz) L L L OFF OFF L L H ±0.7 CLK/625 L H L ±1.3 L H H ±1.8 H L L ±2.2 H L H ±0.7 CLK/385 H H L ±1.2 H H H ±1.7 Figure26. SSCG Waveform Power Saving Features Des — Power Down Feature(PDB) The DS92LV0412 has a PDB inputpintoENABLE or POWER DOWN thedevice.Thispiniscontrolledby the hostand isused tosave power,disablingtheDes when thedisplayisnotneeded.An autodetectmode isalso available.Inthismode, thePDB pinistiedHIGH and theDes willenterPOWER DOWN when theserialstream stops.When theserialstreamstartsup again,theDes willlocktotheinputstreamand asserttheLOCK pinand outputvaliddata.InthePOWER DOWN mode, theLVDS dataand clockoutputstatesare determinedby the OSS_SEL status.Note – inPOWER DOWN, theoptionalSerialBus ControlRegistersareRESET . Des — Stop Stream SLEEPFeature The DS92LV0412 willentera lowpower SLEEP statewhen theinputserialstreamisstopped.A STOP condition isdetectedwhen theembedded clockbitsarenotpresent.When theserialstreamstartsagain,theDes willthen lockto the incomingsignaland recoverthe data.Note – in STOP CLOCK SLEEP, the optionalSerialBus ControlRegistersvaluesareRETAINED . 1.8Vor 3.3VVDDIO Operation The DS92LV0412 parallelcontrolbus can operatewith1.8V or 3.3V levels(VDDIO ) forhostcompatibility.The 1.8V levelswilloffera systempower savings.

32 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

Step 1: SER in BIST Step 2: Wait, DES in BIST Step 3: DES in Normal Mode - check PASS Step 4: SER in Normal BIST Wait BIST Start BIST Stop DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 BuiltInSelfTest(BIST) An optionalAt-SpeedBuiltInSelfTest(BIST)featuresupportsthetestingofthehigh-speedseriallink.Thisis usefulintheprototypestage,equipmentproduction,in-systemtestand alsoforsystem diagnostics.IntheBIST mode onlya inputclockisrequiredalongwithcontroltotheSer and Des BISTEN inputpins.The Ser outputsa testpattern(PRBS7) and drivesthelinkatspeed.The Des detectsthePRBS7 patternand monitorsitforerrors. A PASS outputpintogglestoflagany payloadsthatare receivedwith1 to24 errors.Upon completionofthe test,theresultofthetestisheldon thePASS outputuntilreset(new BIST testorPower Down).A highon PASS indicatesNO ERRORS were detected.A Low on PASS indicatesone ormore errorswere detected.The duration ofthetestiscontrolledby thepulsewidthappliedtotheDes BISTEN pin. Inter-operabilityissupportedbetween thisChannel LinkIIdeviceand allreversecompatibledevices— see respectivedatasheetsfordetailson enteringBIST mode and control. Sample BIST Sequence See Figure27 fortheBIST mode flowdiagram. Step 1: Place the serializerin BIST Mode by settingSer BISTEN = H. The BIST Mode isenabled viathe BISTEN pin.An RxCLKIN isrequiredforallthe Ser options.When the deserializerdetectsthe BIST mode patternand command theparalleldataand controlsignaloutputsareshutoff. Step 2:PlacethedeserializerinBIST mode by settingtheBISTEN = H. The Des isnow intheBIST mode and checkstheincomingserialpayloadsforerrors.Ifan errorinthepayload(1to24)isdetected,thePASS pinwill switchlow forone halfoftheclockperiod.DuringtheBIST test,thePASS outputcan be monitoredand counted todeterminethepayloaderrorrate. Step 3: To Stop theBIST mode, thedeserializerBISTEN pinissetLow. The deserializerstopscheckingthe dataand thefinaltestresultisheldon thePASS pin.Ifthetestranerrorfree,thePASS outputwillbe High.If therewas one ormore errorsdetected,thePASS outputwillbe Low. The PASS outputstateishelduntila new BIST isrun,thedeviceisRESET, orPowered Down. The BIST durationisusercontrolledby thedurationofthe BISTEN signal. Step 4: To returnthelinktonormaloperation,theserand des BISTEN inputare setLow. The Linkreturnsto normaloperation. Figure28 shows thewaveform diagramofa typicalBIST testfortwo cases.Case 1 iserrorfree,and Case 2 shows one withmultipleerrors.Inmost cases itisdifficulttogenerateerrorsdue totherobustnessofthelink (differentialdatatransmissionetc.),thustheymay be introducedby greatlyextendingthecablelength,faulting theinterconnect,reducingsignalconditionenhancements (De-Emphasis,VODSEL, ordeserializerEqualization). Figure27. BIST Mode Flow Diagram Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:DS92LV0411 DS92LV0412

(Diff.) BISTEN (Deserializer) PASS DATA (internal) PASS BIST Duration Prior Result BIST Result Held PASS FAIL X = bit error(s) BISTEN (DS90UR907Q) TxOUT[3:0] (Diff.) DATA (internal) Case 1 - Pass Case 2 - Fail Prior Result Normal PRBS BIST Test Normal Deserializer Outputs DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com BER Calculations ItispossibletocalculatetheapproximateBitErrorRate (BER).The followingisrequired:

PixelClockFrequency(MHz)
BIST Duration(seconds)
BIST testResult(PASS) The BER islessthanorequaltoone overtheproductof24 timestheRxCLKIN ratetimesthetestduration.Ifwe assume a 65MHz RxCLKIN, a 10 minute(600second)test,and a PASS, theBERT is≤ 1.07X 10E-12 The BIST mode runsa check on thedatapayloadbits.The LOCK pinalsoprovidesa linkstatus.Ittherecovery of the C0 and C1 bitsdoes not reconstructthe expectedclocksignal,the LOCK pin willswitchLow. The combinationof the LOCK and At-Speed BIST PASS pin providesa powerfultoolforsystem evaluationand performancemonitoring. Figure28. BIST Waveforms

34 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

START condition, or START repeat condition STO P condition HOST DS92LV0411/ DS92LV0412 SCL SDA 4.7k 4.7k 10k R ID SCL SDA To other Devices ID[X] 1.8V 3.3V DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 OptionalSerialBus Control The DS92LV0411 and DS92LV0412 may be configuredby theuse ofa serialcontrolbus thatisI2C protocol compatible.By default,theI2C reg_0x00'hissetto00'hand allconfigurationissetby control/strappins.A write of01'htoreg_0x00'hwillenable/allowconfigurationby registers;thiswilloverridethecontrol/strappins.Multiple devicesmay sharetheserialcontrolbus sincemultipleaddressesaresupported.See Figure29. The serialbus iscomprisedofthreepins.The SCL isa SerialBus ClockInput.The SDA istheSerialBus Data Input/ Output signal.Both SCL and SDA signalsrequirean externalpullup resistorto VDDIO . For most applicationsa 4.7kΩ pullup resistorto3.3V may be used.The resistorvaluemay be adjustedforcapacitive loadingand dataraterequirements.The signalsareeitherpulledHigh,ordrivenLow. Figure29. SerialControlBus Connection The thirdpinistheID[X]pin.Thispinsetsone offourpossibledeviceaddresses.Threedifferentconnectionsare possible.The pinmay be pulledtoVDD (1.8V,NOT VDDIO ))witha 10 kΩ resistor.Or a 10 kΩ pullup resistor(to VDD 1.8V,NOT VDDIO ))and a pulldown resistoroftherecommended valuetosetotherthreepossibleaddresses may be used.See Table11. The SerialBus protocoliscontrolledby START, START-Repeated, and STOP phases.A START occurswhen SCL transitionsLow whileSDA isHigh.A STOP occurswhen SDA transitionHigh whileSCL isalsoHIGH. See Figure30. Figure30. START and STOP Conditions Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:DS92LV0411 DS92LV0412

Slave Address Register Address Data S 0 ac k ac k ac k P A A A Slave Address Register Address Slave Address Data S 0 1 ac k ac k ac k ac kS P A A A A A A DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com To communicate witha remote device,the hostcontroller(master)sends the slaveaddressand listensfora responsefrom the slave.Thisresponseisreferredto as an acknowledge bit(ACK).Ifa slaveon the bus is addressedcorrectly,itAcknowledges (ACKs) the master by drivingthe SDA bus low.Ifthe addressdoesn't match a device'sslaveaddress,itNot-acknowledges(NACKs) themasterby lettingSDA be pulledHigh.ACKs alsooccuron the bus when data isbeingtransmitted.When the master iswritingdata,the slaveACKs after everydata byteissuccessfullyreceived.When the master isreadingdata,the master ACKs aftereverydata byteisreceivedto letthe slaveknow itwants to receiveanotherdata byte.When the master wants to stop reading,itNACKs afterthelastdatabyteand createsa stopconditionon thebus.Allcommunicationon thebus beginswitheithera Startconditionora Repeated Startcondition.Allcommunicationon thebus ends witha Stop condition.A READ isshown inFigure31 and a WRITE isshown inFigure32. IftheSerialBus isnotrequired,thethreepinsmay be leftopen (NC). Table11. ID[x]ResistorValue – DS92LV0411 Resistor Address Address RID kΩ 7'b 8'b 0 appended (WRITE) 0.47 7b'110 1001 (h'69) 8b'1101 0010 (h'D2) 2.7 7b'110 1010 (h'6A) 8b'1101 0100 (h'D4) 8.2 7b'110 1011 (h'6B) 8b'1101 0110 (h'D6) Open 7b'110 1110 (h'6E) 8b'1101 1100 (h'DC) Table12. ID[x]ResistorValue – DS92LV0412 Resistor Address Address RID kΩ 7'b 8'b 0 appended (WRITE) 0.47 7b'111 0001 (h'71) 8b'1110 0010 (h'E2) 2.7 7b'111 0010 (h'72) 8b'1110 0100 (h'E4) 8.2 7b'111 0011 (h'73) 8b'1110 0110 (h'E6) Open 7b'111 0110 (h'76) 8b'1110 1100 (h'EC) Figure31. SerialControlBus — READ Figure32. SerialControlBus — WRITE

36 SubmitDocumentationFeedback Copyright© 2010–2013,Texas InstrumentsIncorporated

ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 Table13. DS92LV0411 SERIALIZER — SerialBus ControlRegisters ADD ADD RegisterName Bit(s) R/W Defau Function Description (dec) (hex) lt (bin) 0 0 Ser Config1 7 R/W 0 Reserved Reserved

6 R/W 0 MAPSEL 0:LSB on RxIN3

1:MSB on RxIN3

5 R/W 0 VODSEL 0:Low

1:High 4 0 Reserved Reserved 3:2 R/W 00 CONFIG 00:ControlSignalFilterDisabled 01:ControlSignalFilterEnabled 10:Reserved 11:Reserved

1 R/W 0 SLEEP Note – notthesame functionas PowerDown (PDB)

0:normalmode 1:SleepMode – Registersettingsretained.

0 R/W 0 REG 0:Configurationssetfromcontrolpins

1:Configurationsetfromregisters(exceptI2C_ID) 1 1 DeviceID 7 R/W 0 REG ID 0:AddressfromID[X]Pin 1:AddressfromRegister 6:0 R/W 11010 ID[X] SerialBus DeviceID,IDsare: 00 7b '1101001 (h'69) 7b '1101010 (h'6A) 7b '1101011 (h'6B) 7b '1101110 (h'6E) AllotheraddressesareReserved. 2 2 De-Emphasis 7:5 R/W 000 De-E Setting 000:setby externalResistor Control 001:-1dB 010:-2dB 011:-3.3dB 100:-5dB 101:-6.7dB 110:-9dB 111:-12dB

4 R/W 0 De-E EN 0:De-Emphasis Enabled

DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com Table14. DS92LV0412 DESERIALIZER — SerialBus ControlRegisters ADD ADD RegisterName Bit(s) R/W Defau Function Description (dec) (hex) lt (bin) 0 0 Des Config1 7 R/W 0 LFMODE SSCG Mode — lowfrequencysupport 0:20 to65 MHz Operation 1:10 to20 MHz Operation

6 R/W 0 MAPSEL ChannelLinkMap Select

0:LSB on TxOUT3+/- 1:MSB on TxOUT3+/-

5 R/W 0 Reserved Reserved

4 R/W 0 Reserved Reserved

3:2 R/W 00 CONFIG 00:ControlSignalFilterDisabled 01:ControlSignalFilterEnabled 10:Reserved 11:Reserved 0:normalmode 1:SleepMode – Registersettingsretained.

0 R/W 0 REG Control 0:Configurationssetfromcontrolpins

1:Configurationsetfromregisters(exceptI2C_ID) 1 1 DeviceID 7 R/W 0 REG ID 0:AddressfromID[X]Pin 1:AddressfromRegister 6:0 R/W 11100 ID[X] SerialBus DeviceID,IDsare: 00 7b'111 0001 (h'71) 7b'111 0010 (h'72) 7b'111 0011 (h'73) 7b'111 0110 (h'76) AllotheraddressesareReserved. 2 2 Des Features1 7 R/W 0 OEN OutputEnableInput (See Table6)

6 R/W 0 OSS_SEL OutputSleepStateSelect

(See Table6) 5:4 R/W 00 Reserved Reserved

3 R/W 0 VODSEL LVDS DriverOutputVoltageSelect

0:LVDS VOD is±250 mV, 500 mVp-p (typ) 1:LVDS VOD is±400 mV, 800 mVp-p (typ) 2:0 R/W 000 OSC_SEL 000:OFF 001:RESERVED 010:25 MHz ±40% 011:16.7MHz ±40% 100:12.5MHz ±40% 101:10 MHz ±40% 110:8.3MHz ±40% 111:6.3MHz ±40%

ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 Table14. DS92LV0412 DESERIALIZER — SerialBus ControlRegisters(continued) ADD ADD RegisterName Bit(s) R/W Defau Function Description (dec) (hex) lt (bin) 3 3 Des Features2 7:5 R/W 000 EQ Gain 000:~1.625dB 001:~3.25dB 010:~4.87dB 011:~6.5dB 100:~8.125dB 101:~9.75dB 110:11.375dB 111:13 dB

4 R/W 0 EQ Enable 0:EQ = disabled

1:EQ = enabled

3 R/W 0 Reserved Reserved

2:0 R/W 000 SSC IFLFMODE = 0 then: 000:SSCG OFF 001:fdev= ±0.9%,fmod = CLK/2168 010:fdev= ±1.2%,fmod = CLK/2168 011:fdev= ±1.9%,fmod = CLK/2168 100:fdev= ±2.3%,fmod = CLK/2168 101:fdev= ±0.7%,fmod = CLK/21300 110:fdev= ±1.3%,fmod = CLK/1300 111:fdev= ±1.57%,fmod = CLK/1300 IFLFMODE = 1,then: 001:fdev= ±0.7%,fmod = CLK/625 010:fdev= ±1.3%,fmod = CLK/625 011:fdev= ±1.8%,fmod = CLK/625 100:fdev= ±2.2%,fmod = CLK/625 101:fdev= ±0.7%,fmod = CLK/385 110:fdev= ±1.2%,fmod = CLK/385 111:fdev= ±1.7%,fmod = CLK/385 Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:DS92LV0411 DS92LV0412

DAP (GND) VDDP VDDHS VDDTX VDDIO 1.8VDS92LV0411 C12 C5 NOTE: C1-C2 = 0.1 PF (50 WV) C3-C9 = 0.1 PF C10-C12 = 4.7 PF C13 = >10 PF R = 10 k: R1 (cable insertion loss specific) RID (see ID[x] Resistor Value Table) FB1-FB5: Impedance = 1 k:, low DC resistance (<1:) Channel Link Interface LVDS 100:Terminations Serial Channel Link II Interface BISTEN CONFIG1 CONFIG0 MAPSEL VODSEL SCL SDA ID[X] VDDIO RES2 RES1 RES0 C13 Host Control VDDIO C9C8C10 C11FB1 FB2 FB3 FB4 VDDRX C7 FB5 R 1.8V RID 10k RES3 RES4 RES5 RES6 RES7 DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com APPLICATIONS INFORMATION DISPLAY APPLICATION The DS92LV0411 and DS92LV0412 chipsetisintendedforinterfacebetween a host(graphicsprocessor)and a Display.Itsupportsan 24-bitcolordepth (RGB888) and up to 1024 X 768 displayformats.In a RGB888 application,24 colorbits(R[7:0],G[7:0],B[7:0]),PixelClock(PCLK) and threecontrolbits(VS,HS and DE) are supportedacrosstheseriallinkwithPCLK ratesfrom5 to50 MHz. The chipsetmay alsobe used in18-bitcolor applications.Inthisapplicationthreetosixgeneralpurposesignalsmay alsobe sentfromhosttodisplay. DS92LV0411 TYPICAL APPLICATION CONNECTION Figure33 shows a typicalapplicationof the DS92LV0411 fora 50 MHz 24-bitColorDisplayApplication.The LVDS inputsrequireexternal100 ohm differentialterminationresistors.The CML outputsrequire0.1 μF AC couplingcapacitorstotheline.The linedriverincludesinternaltermination.Bypass capacitorsare placednear thepower supplypins.At a minimum, four0.1µF capacitorsand a 4.7 µF capacitorshouldbe used forlocal devicebypassing.System GPO (GeneralPurpose Output)signalscontrolthe PDB and BISTEN pins.The applicationassumes the companion deserializer(DS92LV0412) thereforethe configurationpinsare alsoboth tiedLow. Inthisexample thecableislong,thereforetheVODSEL pinistiedHigh and a De-Emphasis valueis selectedby the resistorR1. The interfaceto the host iswith1.8 V LVCMOS levels,thus the VDDIO pin is connectedalsotothe1.8V rail.The OptionalSerialBus Controlisnotused inthisexample,thustheSCL, SDA and ID[x]pinsare leftopen.A delaycap isplacedon thePDB signaltodelaytheenablingofthedeviceuntil power isstable.Bypass capacitorsareplacednearthepower supplypins.Ferritebeads areplacedon thepower linesforeffectivenoisesuppression. Figure33. DS92LV0411 TypicalConnection Diagram

ProductFolderLinks:DS92LV0411 DS92LV0412

DAP (GND) ID[X] SDA SCL RIN+ RIN- VDDA VDDTX VDDIO 3.3VDS92LV0412 VDDL BISTEN GND 1.8V C1 - C2 = 0.1 PF (50 WV) C3 ± C10, C15 = 0.1 PF C11 - C13 = 4.7 PF C14 = >10 PF R = 10 k: RID (See ID[x] Resistor Value Table) FB1 - FB5: Impedance = 1 k: Low DC resistance ( <1:) Serial Channel Link II Interface PASS CMF VDDP VDDSC VDDSC VDDA C15 Host Control Channel Link Interface LOCK OEN VODSEL OSS_SEL LFMODE SSC[2] SSC[1] SSC[0] VDDL VDDIO FB1 FB3 FB2 C8 C9 C10 C11 C12 C13 PDB C14 R 1.8V RID 10k TxOUT3+ TxOUT3- MAPSEL CONFIG1 CONFIG0 DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 DS92LV0412 TYPICAL APPLICATION CONNECTION Figure34 shows a typicalapplicationof the DS92LV0412 fora 50 MHz 24-bitColorDisplayApplication.The CML inputsrequire0.1 μF AC couplingcapacitorsto the line.The linedriverincludesinternaltermination. Bypass capacitorsare placednear thepower supplypins.At a minimum, four0.1µF capacitorsand a 4.7µF capacitorshouldbe used forlocaldevicebypassing.System GPO (GeneralPurpose Output)signalscontrolthe PDB and BISTEN pins.The applicationassumes the companion deserializer(DS92LV0412) thereforethe configurationpinsarealsobothtiedLow. The interfacetothehostiswith1.8V LVCMOS levels,thustheVDDIO pinisconnectedalsotothe1.8V rail.The OptionalSerialBus Controlisnotused inthisexample,thustheSCL, SDA and ID[x]pinsare leftopen.A delaycap isplacedon thePDB signaltodelaytheenablingofthedevice untilpower isstable.Bypass capacitorsareplacednearthepower supplypins.Ferritebeads areplacedon the power linesforeffectivenoisesuppression. Figure34. DS92LV0412 TypicalConnection Diagram Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com POWER UP REQUIREMENTS AND PDB PIN The VDD (VDDn and VDDIO )supplyramp shouldbe fasterthan1.5ms witha monotonicrise.Ifslowerthen1.5ms then a capacitoron the PDB pin is needed to ensure PDB arrivesafterallthe VDD have settledto the recommended operatingvoltage.When PDB pinispulledtoVDDIO ,itisrecommended touse a 10 kΩ pull-upand a 22 uF cap toGND todelaythePDB inputsignal. TRANSMISSION MEDIA The DS92LV0411 /DS92LV0412 and theircompanion deserializer/serializerchipsetisintendedtobe used ina point-to-pointconfiguration,througha PCB trace,twistedpairor coaxialcables.The DS92LV0411 requires externalparallelLVDS termination,but providesinternalseriallaneterminationsto providea cleansignaling environment.The interconnectforLVDS shouldpresenta differentialimpedance of100 Ohms. The interconnect forthe Channel LinkIIinterfaceshouldpresenta differentialimpedance of 100 Ohms or when configuredfor coaxialcablestheinterconnectshouldpresentan impedance of50 Ohms. Use cablesand connectorsthathave matched impedance to minimizeimpedance discontinuities.Shieldedor un-shieldedcables may be used dependingupon thenoiseenvironmentand applicationrequirements. LIVE LINK INSERTION The serializerand deserializerdevicessupportlivelinkor cablehot plugapplications.The automaticreceiver locktorandom data“plug& go”hotinsertioncapabilityallowstheDS92LV0412 toattainlocktotheactivedata streamduringa livecableinsertionevent. ALTERNATE COLOR /DATA MAPPING Color Mapped data Pin names are providedto specifya recommended mapping for 24-bitand 18-bit Applications.When connectingto earliergenerationsof Channel LinkIIdeserializerdevices,a colormapping reviewisrecommended toensurethecorrectconnectivityisobtained.Table15 providesexamplesforinterfacing between DS92LV0411 and differentdeserializers.

ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 Table15. SerializerAlternateColor/Data Mapping Channel Link BitNumber RGB (LSB DS92LV2412 DS90UR124 DS99R124Q DS90C124 Example) Bit26 B1 B1 Bit25 B0 B0 Bit24 G1 G1 RxIN3 N/A Bit23 G0 G0 Bit22 R1 R1 Bit21 R0 R0 Bit20 DE DE ROUT20 ROUT20 Bit19 VS VS ROUT19 ROUT19 Bit18 HS HS ROUT18 ROUT18 RxIN2 Bit17 B7 B7 ROUT17 TxOUT2 ROUT17 Bit16 B6 B6ROUT10 ROUT16 ROUT16 Bit15 B5 B5 ROUT15 ROUT15 Bit14 B4 B4 ROUT14 ROUT14 Bit13 B3 B3 ROUT13 ROUT13 Bit12 B2 B2 ROUT12 ROUT12 Bit11 G7 G7 ROUT11 ROUT11 RxIN1 Bit10 G6 G6 ROUT10 TxOUT1 ROUT10 Bit9 G5 G5 ROUT9 ROUT9 Bit8 G4 G4 ROUT8 ROUT8 Bit7 G3 G3 ROUT7 ROUT7 Bit6 G2 G2 ROUT6 ROUT6 Bit5 R7 R7 ROUT5 ROUT5 Bit4 R6 R6 ROUT4 ROUT4 RxIN0 Bit3 R5 R5 ROUT3 TxOUT0 ROUT3 Bit2 R4 R4 ROUT2 ROUT2 Bit1 R3 R3 ROUT1 ROUT1 Bit0 R2 R2 ROUT0 ROUT0 ROUT23 OS2 ROUT23 N/A N/A ROUT22 OS1 ROUT22 ROUT21 OS0 ROUT21 DS92LV0411 CONFIG [1:0]= CONFIG [1:0]=MAPSEL = 0 CONFIG [1:0]= 10Settings 00 11 Copyright© 2010–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com Table16. DeserializerAlternateColor/Data Mapping Channel Link BitNumber RGB (LSB DS92LV2411 DS90UR241 DS99R421Q DS90C241 Example) Bit26 B1 B1 Bit25 B0 B0 Bit24 G1 G1 TxOUT3 N/A Bit23 G0 G0 Bit22 R1 R1 Bit21 R0 R0 Bit20 DE DE DIN20 DIN20 Bit19 VS VS DIN19 DIN19 Bit18 HS HS DIN18 DIN18 TxOUT2 Bit17 B7 B7 DIN17 RxIN2 DIN17 Bit16 B6 B6ROUT10 DIN16 DIN16 Bit15 B5 B5 DIN15 DIN15 Bit14 B4 B4 DIN14 DIN14 Bit13 B3 B3 DIN13 DIN13 Bit12 B2 B2 DIN12 DIN12 Bit11 G7 G7 DIN11 DIN11 TxOUT1 Bit10 G6 G6 DIN10 RxIN1 DIN10 Bit9 G5 G5 DIN9 DIN9 Bit8 G4 G4 DIN8 DIN8 Bit7 G3 G3 DIN7 DIN7 Bit6 G2 G2 DIN6 DIN6 Bit5 R7 R7 DIN5 DIN5 Bit4 R6 R6 DIN4 DIN4 TxOUT0 Bit3 R5 R5 DIN3 RxIN0 DIN3 Bit2 R4 R4 DIN2 DIN2 Bit1 R3 R3 DIN1 DIN1 Bit0 R2 R2 DIN0 DIN0 DIN923 OS2 DIN923 N/A N/A DIN922 OS1 DIN922 DIN921 OS0 DIN921 DS92LV0412 CONFIG [1:0]= CONFIG [1:0]=MAPSEL = 0 CONFIG [1:0]= 10Settings 00 11

ProductFolderLinks:DS92LV0411 DS92LV0412

DS92LV0411,DS92LV0412 www.ti.com SNLS331B –MAY 2010–REVISED APRIL 2013 PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuitboard layoutand stack-upfortheLVDS devicesshouldbe designedtoprovidelow-noisepower feedto thedevice.Good layoutpracticewillalsoseparatehighfrequencyor high-levelinputsand outputstominimize unwanted straynoisepickup,feedbackand interference.Power systemperformancemay be greatlyimprovedby usingthindielectrics(2to4 mils)forpower /groundsandwiches.Thisarrangementprovidesplanecapacitance forthe PCB power system with low-inductanceparasitics,which has proven especiallyeffectiveat high frequencies,and makes the valueand placementof externalbypass capacitorslesscritical.Externalbypass capacitorsshouldincludebothRF ceramicand tantalumelectrolytictypes.RF capacitorsmay use valuesinthe tantalumcapacitorsshouldbe atleast5X thepower supplyvoltagebeingused. Surfacemount capacitorsarerecommended due totheirsmallerparasitics.When usingmultiplecapacitorsper supplypin,locatethesmallervalueclosertothepin.A largebulkcapacitorisrecommend atthepointofpower entry.This is typicallyin the 50uF to 100uF range and willsmooth low frequencyswitchingnoise.Itis recommended toconnectpower and groundpinsdirectlytothepower and groundplaneswithbypass capacitors connectedtotheplanewithviaon bothends ofthecapacitor.Connectingpower or ground pinstoan external bypasscapacitorwillincreasetheinductanceofthepath. A smallbody sizeX7R chipcapacitor,such as 0603,isrecommended forexternalbypass.Itssmallbody size reducesthe parasiticinductanceof the capacitor.The user must pay attentionto the resonancefrequencyof theseexternalbypass capacitors,usuallyinthe range of 20-30 MHz. To provideeffectivebypassing,multiple capacitorsare oftenused toachievelow impedance between thesupplyrailsoverthefrequencyofinterest.At highfrequency,itisalsoa common practicetouse two viasfrompower and groundpinstotheplanes,reducing theimpedance athighfrequency. Some devicesprovideseparatepower and groundpinsfordifferentportionsofthecircuit.Thisisdone toisolate switchingnoiseeffectsbetween differentsectionsof the circuit.Separateplaneson the PCB are typicallynot required.PIN DESCRIPTIONS tablestypicallyprovideguidanceon whichcircuitblocksareconnectedtowhich power pinpairs.Insome cases,an externalfiltermany be used toprovidecleanpower tosensitivecircuitssuch as PLLs. Use atleasta fourlayerboard witha power and ground plane.LocateLVCMOS signalsaway from theLVDS linesto preventcouplingfrom the LVCMOS linesto the LVDS lines.Closely-coupleddifferentiallinesof 100 Ohms aretypicallyrecommended forLVDS interconnect.The closelycoupledlineshelptoensurethatcoupled noisewillappear as common-mode and thusisrejectedby the receivers.The tightlycoupledlineswillalso radiateless. Informationon theWQFN stylepackage isprovidedinApplicationNote:AN-1187 (SNOA401 ). LVDS INTERCONNECT GUIDELINES See AN-1108 (SNLA008 )and AN-905 (SNLA035 )forfulldetails.

Use 100Ω coupleddifferentialpairs
Use theS/2S/3Sruleinspacings – S = space between thepair – 2S = space between pairs – 3S = space toLVCMOS signal
Minimizethenumber ofvias
Ifviasareused,be suretoplaceviastogroundadjacenttothesignalviastoensurea constantreturnpath forthesignal
Use differentialconnectorswhen operatingabove 500Mbps linespeed
Maintainbalanceofthetraces
Minimizeskew withinthepair

DS92LV0411,DS92LV0412 SNLS331B –MAY 2010–REVISED APRIL 2013 www.ti.com

REVISION HISTORY

Changes from RevisionA (April2013)toRevisionB Page

ProductFolderLinks:DS92LV0411 DS92LV0412

www.ti.com 16-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples DS92LV0411SQ/NOPB ACTIVE WQFN NJK 36 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LV0411SQ DS92LV0411SQE/NOPB ACTIVE WQFN NJK 36 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LV0411SQ DS92LV0411SQX/NOPB ACTIVE WQFN NJK 36 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LV0411SQ DS92LV0412SQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LV0412SQ DS92LV0412SQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LV0412SQ DS92LV0412SQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 LV0412SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

www.ti.com 16-Apr-2013 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2014 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV0411SQ/NOPB WQFN NJK 36 1000 367.0 367.0 38.0 DS92LV0411SQE/NOPB WQFN NJK 36 250 213.0 191.0 55.0 DS92LV0411SQX/NOPB WQFN NJK 36 2500 367.0 367.0 38.0 DS92LV0412SQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0 DS92LV0412SQE/NOPB WQFN RHS 48 250 213.0 191.0 55.0 DS92LV0412SQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2014 Pack Materials-Page 2

www.ti.com SQA36A (Rev A)

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic”are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated

Product Information