DS92LV040ATLQA/NO.A

DS92LV040A TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 24

Technical content

Copyright © 2018, Texas Instruments Incorporated DIN1 DE1 RO1 DIN2 RO2 DIN3 DE2 RO3 DIN4 RO4 RE1 RE2 DO1+/RI1+ DO1-/RI1- DO2+/RI2+ DO2-/RI2- DO3+/RI3+ DO3-/RI3- DO4+/RI4+ DO4-/RI4- Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS92LV040A SNOS521E –JANUARY 2001–REVISED JANUARY 2018 DS92LV040A4ChannelBusLVDSTransceiver

1 Features

1• Bus LVDS Signaling

• Propagation Delay: Driver 2.3 ns Max, Receiver 3.2 ns Max
• Low power CMOS Design
• 100% Transition Time 1 ns Driver Typical, 1.3 ns Receiver Typical
• High Signaling Rate Capability (above 155 Mbps)
• 0.1 V to 2.3 V Common Mode Range for VID = 200 mV
• 70 mV Receiver Sensitivity
• Supports Open and Terminated Failsafe on Port Pins
• 3.3-V Operation
• Glitch Free Power up/down (Driver & Receiver Disabled)
• Light Bus Loading (5 pF Typical) per Bus LVDS Load
• Balanced Output Impedance
• Product Offered in 44 Pin WQFN Package
• High Impedance Bus Pins on Power Off (VCC = 0 V)

2 Applications

Designed for Double Termination Applications

3 Description

The DS92LV040A is one in a series of Bus LVDS transceivers designed specifically for high speed, low power backplane or cable interfaces. The device operates from a single 3.3-V power supply and includes four differential line drivers and four receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver translates 3-V LVTTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation while consuming minimal power and reducing EMI. In addition, the differential signaling provides common mode noise rejection greater than ±1 V. The receiver threshold is less than +0/−70 mV. The receiver translates the differential Bus LVDS to standard (LVTTL/LVCMOS) levels. (See the Application Information Section for more details.) Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DS92LV040A WQFN (44) 7.00 mm x 7.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Functional Diagram

SNOS521E –JANUARY 2001–REVISED JANUARY 2018 www.ti.com Product Folder Links: DS92LV040A Submit Documentation Feedback Copyright © 2001–2018, Texas Instruments Incorporated Table of Contents

12.2 Receiving Notification of Documentation Updates 19

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (April 2013) to Revision E Page

• Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Changes from Revision C (April 2013) to Revision D Page

43 RO4

13DO4 íRI4í 2NC 32 NC

42 DIN4

31 GND

41 RO3

15DO3 íRI3í 4GND

30 VCC

40 DIN3

29 RE12

39 GND

28 GND

38 RO2

18DO2 íRI2í 7AVCC

27 AVCC

37 DIN2

26 DE12

36 RO1

20DO1 íRI1í 9AGND

25 AGND

35 DIN1

www.ti.com SNOS521E –JANUARY 2001–REVISED JANUARY 2018 Product Folder Links: DS92LV040A Submit Documentation FeedbackCopyright © 2001–2018, Texas Instruments Incorporated

5 Pin Configuration and Functions

WQFN (44 Pin) Top View Pin Functions PIN NAME PIN # INPUT/ OUTPUT DESCRIPTIONS DO+/RI+ 14, 16, 19, 21 I/O True Bus LVDS Driver Outputs and Receiver Inputs. DO−/RI− 13, 15, 18, 20 I/O Complimentary Bus LVDS Driver Outputs and Receiver Inputs. DIN 35, 37, 40, 42 I LVTTL Driver Input. No pull up or pull down is attached to this pin RO 36, 38, 41, 43 O LVTTL Receiver Output. RE12 29 I Receiver Enable LVTTL Input (Active Low). This pin, when low, configures receiver outputs, RO1 and RO2 active. When this pin is high, RO1 and RO2 are TRI-STATE. If this pin is floating, a weak current source to VCC causes RO1 and RO2 to be TRI-STATE RE34 5 I Receiver Enable LVTTL Input (Active Low). This pin, when low, configures receiver outputs, RO3 and RO4 active. When this pin is high, RO3 and RO4 are TRI-STATE. If this pin is floating, a weak current source to VCC causes RO3 and RO4 to be TRI-STATE DE12 26 I Driver Enable LVTTL Input (Active High). This pin, when high, configures driver outputs, DO1+/RIN1+, DO1−/RIN1− and DO2+/RIN2+, DO2−/RIN2− active. When this pin is low, driver outputs 1 and 2 are TRI-STATE. If this pin is floating, a weak current source to VCC causes driver outputs 1 and 2 to be active DE34 8 I Driver Enable LVTTL Input (Active High). This pin, when high, configures driver outputs, DO3+/RIN3+, DO3−/RIN3− and DO4+/RIN4+, DO4−/RIN4− active. When this pin is low, driver outputs 3 and 4 are TRI-STATE. If this pin is floating, a weak current source to VCC causes driver outputs 3 and 4 to be active GND 4, 28, 31, 39 Ground Ground for digital circuitry (must connect to GND on PC board). These pins connected internally. VCC 3, 6, 30 Power VCC for digital circuitry (must connect to VCC on PC board). These pins connected internally. AGND 9, 17, 25 Ground Ground for analog circuitry (must connect to GND on PC board). These pins connected internally. AVCC 7, 10, 22, 27 Power Analog VCC (must connect to VCC on PC board). These pins connected internally. NC 1, 2, 11, 12, 23, 24, 32, 33, 34, 44 N/A Reserved for future use, leave open circuit. DAP GND Must connect to GND plane through vias to achieve the theta ja specified under Absolute Maximum Ratings. The DAP (die attach pad) is the heat transfer material that is centered on the bottom of the WQFN package. Refer to application note AN-1187 () for attachment details.

SNOS521E –JANUARY 2001–REVISED JANUARY 2018 www.ti.com Product Folder Links: DS92LV040A Submit Documentation Feedback Copyright © 2001–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (3) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified except VOD, ΔVOD and VID.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)ccr(3) MIN MAX UNIT Supply Voltage, VCC 4 V Enable Input Voltage (DE, RE) −0.3 VCC +0.3 V V Driver Input Voltage (DIN) −0.3 VCC +0.3 V V Driver Short Circuit Current Duration Continuous Receiver Output Voltage ( ROUT) −0.3 VCC +0.3 V V Bus Pin Voltage (DO±/RI±) −0.3 3.9 V Storage temperature, Tstg −65 150 °C (1) All typicals are given for VCC = +3.3 V and TA = +25°C, unless otherwise stated. (2) ESD Rating: HBM (1.5 kΩ, 100 pF) > 4 kV EIAJ (0 Ω, 200 pF) > 250. (3) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (4) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

V(ESD) Electrostatic discharge(1)(2) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(3) ±2000 VCharged-device model (CDM), per JEDEC specification JESD22- C101(4) ±1000 (1) Generator waveforms for all tests unless otherwise specified: f = 25 MHz, ZO = 50 Ω, tr, tf = <1 ns (0%–100%). To ensure fastest propagation delay and minimum skew, data input edge rates should be equal to or faster than 1 ns/V; control signals equal to or faster than 3 ns/V. In general, the faster the input edge rate, the better the AC performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Supply Voltage 3 3.6 V Receiver Input Voltage 0 2.4 V TA Ambient Free Air Temperature −40 85 °C Slowest Input Edge Rate, Δt/ΔV (20% to 80%)(1) Data 1 ns/V Control 3 ns/V (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Package must be mounted to pc board in accordance with AN-1187 (SNOA401) to achieve thermals.

6.4 Thermal Information

THERMAL METRIC(1) DS92LV040A UNITNJN (WQFN)

44 PINS

RθJA Junction-to-ambient thermal resistance (2) 25.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 25.5 °C/W

www.ti.com SNOS521E –JANUARY 2001–REVISED JANUARY 2018 Product Folder Links: DS92LV040A Submit Documentation FeedbackCopyright © 2001–2018, Texas Instruments Incorporated (1) The DS92LV040A functions within datasheet specification when a resistive load is applied to the driver outputs. (2) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified except VOD, ΔVOD and VID. (3) All typicals are given for VCC = +3.3 V and TA = +25°C, unless otherwise stated. (4) VOH fail-safe terminated test performed with 27 Ω connected between RI+ and RI− inputs. No external voltage is applied. (5) Propagation delays, transition times, and receiver threshold are ensured by design and characterization.

6.5 DC Electrical Characteristics(1)

Over recommended operating supply voltage and temperature ranges unless otherwise specified.(2)(3) PARAMETER TEST CONDITIONS PIN MIN TYP MAX UNIT VOD Output Differential Voltage RL = 27Ω, Figure 1 DO+/RI+, DO−/RI− 200 300 460 mV ΔVOD VOD Magnitude Change 5 27 mV VOS Offset Voltage 1.1 1.3 1.5 V ΔVOS Offset Magnitude Change 5 10 mV VOHD Driver Output High Voltage RL = 27Ω 1.4 1.65 V VOLD Driver Output Low Voltage RL = 27Ω 0.95 1.1 V IOSD Driver Output Short Circuit Current VOD = 0V, DE = VCC, Driver outputs shorted together |30| | 45| mA VOHR Receiver Voltage Output High(4) VID = +300 mV IOH = −4 mA ROUT VCC−0.2 V Inputs Open VCC−0.2 V Inputs Terminated, RL = 27Ω VCC−0.2 V VOLR Receiver Voltage Output Low IOL = 4.0 mA, VID = −300 mV 0.05 0.100 V IOD Receiver Output Dynamic Current VID = 300mV, VOUT = VCC−1.0V −50 |33| mA VID = −300mV, VOUT = 1.0V |36| 60 mA VTH Input Threshold High(5) DE = 0V, Over common mode range DO+/RI+, DO−/RI− −40 0 mV VTL Input Threshold Low(5) −70 −40 mV VCMR Receiver Common Mode Range |VID|/2 2.4 − |VID|/2 V IIN Input Current DE = 0V, RE = 2.4V, VIN = +2.4V or 0V −20 ±1 +20 µA VCC = 0V, VIN = +2.4V or 0V −20 ±1 +20 µA VIH Minimum Input High Voltage DIN, DE, RE

2.0 VCC V

VIL Maximum Input Low Voltage GND 0.8 V IIH Input High Current VIN = VCC or 2.4V −20 ±2.5 +20 µA IIL Input Low Current VIN = GND or 0.4V −20 ±2.5 +20 µA VCL Input Diode Clamp Voltage ICLAMP = −18 mA −1.5 −0.8 V ICCD Power Supply Current Drivers Enabled, Receivers Disabled No Load, DE = RE = VCC, DIN = VCC or GND VCC 20 40 mA ICCR Power Supply Current Drivers Disabled, Receivers Enabled DE = RE = 0V, VID = ±300mV 27 40 mA ICCZ Power Supply Current, Drivers and Receivers TRI-STATE DE = 0V; RE = VCC, DIN = VCC or GND 28 40 mA ICC Power Supply Current, Drivers and Receivers Enabled DE = VCC; RE = 0V, DIN = VCC or GND, RL = 27Ω 70 100 mA IOFF Power Off Leakage Current VCC = 0V or OPEN, DIN, DE, RE = 0V or OPEN, VAPPLIED = 3.6V (Port Pins) DO+/RI+, DO−/RI− −20 +20 µA COUTPUT Capacitance at Bus Pins DO+/RI+, DO−/RI− 5 pF cOUTPUT Capacitance at ROUT ROUT 5 pF

than 3ns/V. In general, the faster the input edge rate, the better the AC performance. (2) CL includes probe and fixture capacitance. (3) Propagation delays, transition times, and receiver threshold are ensured by design and characterization. (4) tSKD1 |tPHLD–tPLHD| is the worst case pulse skew (measure of duty cycle) over recommended operation conditions. (5) Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.

6.6 AC Electrical Characteristics

7 Parameter Measurement Information

7.1 Test Circuits and Timing Waveforms

Figure 1. Differential Driver DC Test Circuit

Copyright © 2018, Texas Instruments Incorporated DIN1 DE1 RO1 DIN2 RO2 DIN3 DE2 RO3 DIN4 RO4 RE1 RE2 DO1+/RI1+ DO1-/RI1- DO2+/RI2+ DO2-/RI2- DO3+/RI3+ DO3-/RI3- DO4+/RI4+ DO4-/RI4- DS92LV040A www.ti.com SNOS521E –JANUARY 2001–REVISED JANUARY 2018 Product Folder Links: DS92LV040A Submit Documentation FeedbackCopyright © 2001–2018, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

BLVDS drivers and receivers are intended to be used in a differential backplane configuration. Transceivers or receivers are connected to the driver through a balanced media such as differential PCB traces. Typically, the characteristic differential impedance of the media (ZO) is in the range of 50 Ω to 100 Ω. Two termination resistors of ZO Ω each are placed at the ends of the transmission line backplane. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. The effects of mid-stream connector(s), cable stub(s), and other impedance discontinuity as well as ground shifting, noise margin limits, and total termination loading must be taken into account.

8.2 Functional Block Diagram

8.3 Feature Description

The DS92LV040A differential line driver is a balanced current mode design. A current mode driver, generally speaking has a high output impedance (100 Ω) and supplies a reasonably constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). The current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state.

power state when the transmission of data is not required.

8.4 Device Functional Modes

Table 1. Functional Table Table 2. Transmitter Mode Table 3. Receiver Mode

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The DS92LV040A is a Bus LVDS transceiver intended to be used in a differential backplane configuration. Transceivers or receivers are connected to the driver through a balanced media such as differential PCB traces. margin limits, and total termination loading must be taken into account. state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 600 mV.

9.2 Typical Application

9.2.1 Multipoint Communications

situation creates contention issues that need not be addressed with point-to-point or multidrop systems. transmission line is now necessary. signal drivers with controlled signal edges are the keys to error-free signal transmissions in multipoint topologies. Figure 10. Bidirectional Half-Duplex Point-to-Point Applications

Figure 11. Multi-Point Bus Applications

9.2.2 Design Requirements

For this design example, use the parameters listed in Table 4. Table 4. Design Parameters

9.2.3 Detailed Design Procedure

9.2.3.1 Supply Voltage

9.2.3.2 Supply Bypass Capacitance

installed locally next to the integrated circuit.

www.ti.com SNOS521E –JANUARY 2001–REVISED JANUARY 2018 Product Folder Links: DS92LV040A Submit Documentation FeedbackCopyright © 2001–2018, Texas Instruments Incorporated

9.2.3.3 Termination Resistors

Multipoint LVDS communication channel employs a current source driving a transmission line which is terminated with two resistive loads. These loads serve to convert the transmitted current into a voltage at the receiver input. To ensure good signal integrity, the termination resistors should be matched to the characteristic impedance of the transmission line. The designer should ensure that the termination resistors are within 10% of the nominal media characteristic impedance. If the transmission line is targeted for 100-Ω impedance, the termination resistors should be between 90 Ω and 110 Ω. The line termination resistors are typically placed at the ends of the transmission line.

9.2.3.4 Interconnecting Media

The backplane and connectors should have a matched differential impedance. Use controlled impedance traces which match the differential impedance of your transmission medium (ie. backplane or cable) and termination resistor(s). Run the differential pair trace lines as close together as possible as soon as they leave the IC. This helps eliminate reflections and ensure noise is coupled as common-mode. In fact, it has been determined that differential signals which are 1 mm apart radiate far less noise than traces 3 mm apart since magnetic field cancellation is much better with the closer traces. Plus, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result. Stub lengths should be kept to a minimum. The typical transition time of the DS92LV040A Bus LVDS output is the electrical length of a trace is greater than 1/5 of the transition edge, then the trace is considered a transmission line. For example, 1.25 ns/5 is 250 picoseconds. Let velocity equal 160 ps per inch for a typical loaded backplane. Then maximum stub length is 250 ps/160 ps/in or 1.56 inches. To determine the maximum stub for the backplane, determine the propagation velocity for the actual conditions (refer to application notes AN 905 and AN 808)

10 Power Supply Recommendations

The driver and receivers in this data sheet are designed to operate from a single power supply. Both drivers and receivers operate with supply voltages in the range of 3 V to 3.6 V. In a typical application, a driver and a receiver may be on separate boards, or even separate equipment. In these cases, separate supplies would be used at each location. The expected ground potential difference between the driver power supply and the receiver power supply would be less than ±1 V. Board level and local device level bypass capacitance should be used and are covered Supply Bypass Capacitance.

(3) Clyde F. Coombs, Jr. Ed, Printed Circuits Handbook, McGraw Hill, ISBN number 0070127549.

11 Layout

11.1 Layout Guidelines

stripline. Microstrips are traces on the outer layer of a PCB, as shown in Figure 12. Figure 12. Microstrip Topology Figure 13. Stripline Topology

11.1.2 Dielectric Type and Board Construction

• Copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz

• All exposed circuitry should be solder-plated (60/40) to 7.62 μm or 0.0003 in (minimum).
• Copper plating should be 25.4 μm or 0.001 in (minimum) in plated-through-holes.
• Solder mask over bare copper with solder hot-air leveling

11.1.3 Recommended Stack Layout

signal planes as shown in Figure 14. Figure 14. Four-Layer PCB Board One of the most common stack configurations is the six-layer board, as shown in Figure 15. Figure 15. Six-Layer PCB Board layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6.

11.1.4 Separation Between Traces

problems with skew and signal reflection. traces are edge-coupled or broad-side-coupled.

Figure 16. 3-W Rule for Single-Ended and Differential Traces (Top View) signal path. Using successive 45° turns tends to minimize reflections.

11.1.5 Crosstalk and Ground Bounce Minimization

field strength. Discontinuities in the ground plane increase the return path inductance and should be avoided.

11.1.6 Decoupling

to the top of the board reduces the effective via length and its associated inductance. Figure 17. Low Inductance, High-Capacitance Power Connection plane through vias tangent to the pads of the capacitor as shown in Figure 18(a).

at a separation of 2 to 3 mils. With a 2-mil FR4 dielectric, there is approximately 500 pF per square inch of PCB. may flow from the pad and into the via barrel. This results in a poor solder connection. Figure 18. Typical Decoupling Capacitor Layouts

11.2 Layout Example

Figure 19. Staggered Trace Layout

additional capacitance. For example, a typical via has a lumped capacitance effect of 1/2 pF to 1 pF in FR4. Figure 20. Ground Via Location (Side View) discontinuities that increase returning current loop areas. same area, as opposed to mixing them together, helps reduce susceptibility issues.

www.ti.com SNOS521E –JANUARY 2001–REVISED JANUARY 2018 Product Folder Links: DS92LV040A Submit Documentation FeedbackCopyright © 2001–2018, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

General application guidelines and hints may be found in the following application notes: ), A). For related documentation see the following:

• AN-808 (SNLA028)
• AN-977 (SNLA166
• AN-971 (SNLA165)
• AN-903 (SNLA034

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. Rogers is a trademark of Rogers Corporation. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS92LV040ATLQA/NO.A Active Production WQFN (NJN) | 44 250 | SMALL T&R Yes SN Level-2-260C-1 YEAR -40 to 85 LV040A DS92LV040ATLQA/NOPB Active Production WQFN (NJN) | 44 250 | SMALL T&R Yes SN Level-2-260C-1 YEAR -40 to 85 LV040A DS92LV040ATLQAX/NO.A Active Production WQFN (NJN) | 44 2500 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 85 LV040A DS92LV040ATLQAX/NOPB Active Production WQFN (NJN) | 44 2500 | LARGE T&R Yes SN Level-2-260C-1 YEAR -40 to 85 LV040A (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 31-Oct-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant DS92LV040ATLQAX/ NOPB Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 31-Oct-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV040ATLQA/NOPB WQFN NJN 44 250 208.0 191.0 35.0 DS92LV040ATLQAX/ NOPB WQFN NJN 44 2500 356.0 356.0 36.0 Pack Materials-Page 2

www.ti.com LQA44A (REV B)

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated