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www.ti.com SNLS007E –MAY 1998–REVISED APRIL 2013 DS92LV010ABusLVDS3.3/5.0VSingleTransceiver Check forSamples: DS92LV010A 1FEATURES DESCRIPTION The DS92LV010A isone ina seriesof transceivers 2• Bus LVDS Signaling(BLVDS) designedspecificallyforthe high speed, low power• Designed forDouble TerminationApplications proprietarybus backplane interfaces.The device

Balanced Output Impedance operatesfrom a single3.3V or 5.0V power supply and includesone differentiallinedriverand one• LiteBus Loading 5pF Typical receiver.To minimizebus loadingthe driveroutputs• GlitchFree Power Up/Down (DriverDisabled) and receiverinputsare internallyconnected.The
3.3Vor 5.0VOperation logicinterfaceprovidesmaximum flexibilityas 4 separate linesare provided (DIN, DE, RE, and• ±1V Common Mode Range ROUT). The devicealsofeaturesflowthroughwhich• ±100mV ReceiverSensitivity allowseasy PCB routingforshortstubsbetween the• High SignalingRate Capability(Above 100 bus pinsand the connector.The driverhas 10 mA Mbps) drivecapability,allowingitto driveheavilyloaded backplanes,withimpedance as lowas 27 Ohms.• Low Power CMOS Design
Product Offeredin8 Lead SOIC Package The drivertranslatesbetween TTL levels(single- ended) to Low VoltageDifferentialSignalinglevels.• IndustrialTemperature Range Operation This allows for high speed operation,while consuming minimal power with reduced EMI. In additionthe differentialsignalingprovidescommon mode noiserejectionof±1V. The receiverthresholdis ±100mV over a ±1V common mode range and translatesthe low voltage differentiallevelstostandard(CMOS/TTL) levels. CONNECTION DIAGRAM Figure1. SOIC Package See Package Number D0008A BLOCK DIAGRAM Figure2. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1998–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS007E –MAY 1998–REVISED APRIL 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. ABSOLUTE MAXIMUM RATINGS (1)(2)(3) SupplyVoltage(VCC ) 6.0V EnableInputVoltage(DE,RE) −0.3Vto(VCC + 0.3V) DriverInputVoltage(DIN) −0.3Vto(VCC + 0.3V) ReceiverOutputVoltage (ROUT ) −0.3Vto(VCC + 0.3V) Bus PinVoltage(DO/RI±) −0.3Vto+ 3.9V DriverShortCircuitCurrent Continuous ESD (HBM 1.5kΩ,100 pF) >2.0kV Maximum Package Power Dissipationat25°C SOIC 1025 mW DerateSOIC Package 8.2mW/ °C JunctionTemperature +150°C StorageTemperatureRange −65°C to+150°C Lead Temperature (Soldering,4 sec.) 260°C (1) Allcurrentsintodevicepinsarepositive;allcurrentsoutofdevicepinsarenegative.Allvoltagesarereferencedtodevicegroundexcept VOD ,VID,VTH and VTL unlessotherwisespecified. (2) AbsoluteMaximum Ratingsarethesebeyond whichthesafetyofthedevicecannotbe ensured.They arenotmeant toimplythatthe deviceshouldbe operatedattheselimits.The tableof“ElectricalCharacteristics”providesconditionsforactualdeviceoperation. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. RECOMMENDED OPERATING CONDITIONS Min Max Units SupplyVoltage(VCC ),or 3.0 3.6 V SupplyVoltage(VCC ) 4.5 5.5 V ReceiverInputVoltage 0.0 2.9 V OperatingFreeAirTemperature −40 +85 °C

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www.ti.com SNLS007E –MAY 1998–REVISED APRIL 2013 3.3VDC ELECTRICAL CHARACTERISTICS (1)(2) TA = −40°C to+85°C unlessotherwisenoted,VCC = 3.3V± 0.3V Parameter TestConditions Pin Min Typ Max Units VOD OutputDifferentialVoltage R L = 27Ω,See Figure3 DO+/RI+, 140 250 360 mV DO −/RI−ΔVOD VOD MagnitudeChange 3 30 mV VOS OffsetVoltage 1 1.25 1.65 V ΔVOS OffsetMagnitudeChange 5 50 mV IOSD OutputShortCircuitCurrent VO = 0V,DE = VCC −12 −20 mA VOH VoltageOutputHigh VID = +100 mV IOH = −400 µA R OUT 2.8 3 V InputsOpen 2.8 3 V InputsShorted 2.8 3 V InputsTerminated,R L = 27Ω 2.8 3 V VOL VoltageOutputLow IOL = 2.0mA, VID = −100 mV 0.1 0.4 V IOS OutputShortCircuitCurrent VOUT = 0V,VID = +100 mV −5 −35 −85 mA VTH InputThresholdHigh DE = 0V DO+/RI+, +100 mV DO −/RI−VTL InputThresholdLow −100 mV IIN InputCurrent DE = 0V,VIN = +2.4V,or0V −20 ±1 +20 µA VCC = 0V,VIN = +2.4V,or0V −20 ±1 +20 µA VIH Minimum InputHighVoltage DIN, 2.0 VCC V DE,REVIL Maximum InputLow Voltage GND 0.8 V IIH InputHighCurrent VIN = VCC or2.4V ±1 ±10 µA IIL InputLow Current VIN = GND or0.4V ±1 ±10 µA VCL InputDiodeClamp Voltage ICLAMP = −18 mA −1.5 −0.8 V ICCD Power SupplyCurrent DE = RE = VCC ,R L = 27Ω V CC 13 20 mA ICCR DE = RE = 0V 5 8 mA ICCZ DE = 0V,RE = VCC 3 7.5 mA ICC DE = VCC ,RE = 0V,R L = 27Ω 16 22 mA C output Capacitance@ BUS Pins DO+/RI+, 5 pF DO −/RI− (1) Allcurrentsintodevicepinsarepositive;allcurrentsoutofdevicepinsarenegative.Allvoltagesarereferencedtodevicegroundexcept VOD ,VID,VTH and VTL unlessotherwisespecified. (2) AlltypicalsaregivenforVCC = +3.3V or5.0V and TA = +25°C, unlessotherwisestated. Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS92LV010A

SNLS007E –MAY 1998–REVISED APRIL 2013 www.ti.com 5V DC ELECTRICAL CHARACTERISTICS (1)(2) TA = −40°C to+85°C unlessotherwisenoted,VCC = 5.0V± 0.5V Parameter TestConditions Pin Min Typ Max Units VOD OutputDifferentialVoltage R L = 27Ω,See Figure3 DO+/RI+, 145 270 390 mV DO −/RI−ΔVOD VOD MagnitudeChange 3 30 mV VOS OffsetVoltage 1 1.35 1.65 V ΔVOS OffsetMagnitudeChange 5 50 mV IOSD OutputShortCircuitCurrent VO = 0V,DE = VCC −12 −20 mA VOH VoltageOutputHigh VID = +100 mV IOH = −400 µA R OUT 4.3 5.0 V InputsOpen 4.3 5.0 V InputsShorted 4.3 5.0 V InputsTerminated,R L = 27Ω 4.3 5.0 V VOL VoltageOutputLow IOL = 2.0mA, VID = −100 mV 0.1 0.4 V IOS OutputShortCircuitCurrent VOUT = 0V,VID = +100 mV −35 −90 −130 mA VTH InputThresholdHigh DE = 0V DO+/RI+, +100 mV DO −/RI−VTL InputThresholdLow −100 mV IIN InputCurrent DE = 0V,VIN = +2.4V,or0V −20 ±1 +20 µA VCC = 0V,VIN = +2.4V,or0V −20 ±1 +20 µA VIH Minimum InputHighVoltage DIN,DE, 2.0 VCC V REVIL Maximum InputLow Voltage GND 0.8 V IIH InputHighCurrent VIN = VCC or2.4V ±1 ±10 µA IIL InputLow Current VIN = GND or0.4V ±1 ±10 µA VCL InputDiodeClamp Voltage ICLAMP = −18 mA −1.5 −0.8 V ICCD Power SupplyCurrent DE = RE = VCC ,R L = 27Ω V CC 17 25 mA ICCR DE = RE = 0V 6 10 mA ICCZ DE = 0V,RE = VCC 3 8 mA ICC DE = VCC ,RE = 0V,R L = 27Ω 20 25 mA C output Capacitance@ BUS Pins DO+/RI+, 5 pF DO −/RI− (1) Allcurrentsintodevicepinsarepositive;allcurrentsoutofdevicepinsarenegative.Allvoltagesarereferencedtodevicegroundexcept VOD ,VID,VTH and VTL unlessotherwisespecified. (2) AlltypicalsaregivenforVCC = +3.3V or5.0V and TA = +25°C, unlessotherwisestated.

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www.ti.com SNLS007E –MAY 1998–REVISED APRIL 2013 3.3VAC ELECTRICAL CHARACTERISTICS (1) TA = −40°C to+85°C, VCC = 3.3V± 0.3V Parameter TestConditions Min Typ Max Units DIFFERENTIAL DRIVER TIMING REQUIREMENTS tPHLD DifferentialProp.DelayHighto R L = 27Ω,See Figure4 and Figure5 1.0 3.0 5.0 ns Low C L = 10 pF tPLHD DifferentialProp.DelayLow to 1.0 2.8 5.0 ns High tSKD DifferentialSKEW |tPHLD - 0.2 1.0 ns tPLHD | tTLH TransitionTime Low toHigh 0.3 2.0 ns tTHL TransitionTime HightoLow 0.3 2.0 ns tPHZ DisableTime HightoZ R L = 27Ω,See Figure6 and Figure7 0.5 4.5 9.0 ns C L = 10 pFtPLZ DisableTime Low toZ 0.5 5.0 10.0 ns tPZH EnableTime Z toHigh 2.0 5.0 7.0 ns tPZL EnableTime Z toLow 1.0 4.5 9.0 ns DIFFERENTIAL RECEIVER TIMING REQUIREMENTS tPHLD DifferentialProp.DelayHighto See Figure8 and Figure9 2.5 5.0 12.0 ns Low C L = 10 pF tPLHD DifferentialProp.DelayLow to 2.5 5.5 10.0 ns High tSKD DifferentialSKEW |tPHLD - 0.5 2.0 ns tPLHD | tr RiseTime 1.5 4.0 ns tf FallTime 1.5 4.0 ns tPHZ DisableTime HightoZ R L = 500Ω,See Figure10 and Figure11 2.0 4.0 6.0 ns C L = 10 pF (2) tPLZ DisableTime Low toZ 2.0 5.0 7.0 ns tPZH EnableTime Z toHigh 2.0 7.0 13.0 ns tPZL EnableTime Z toLow 2.0 6.0 10.0 ns (1) Generatorwaveformsforalltestsunlessotherwisespecified:f= 1MHz, ZO = 50Ω,tr,tf≤ 6.0ns(0%–100%) on controlpinsand ≤ 1.0ns forRI inputs. (2) Forreceivertri-statedelays,theswitchissettoVCC fortPZL ,and tPLZ and toGND fortPZH ,and tPHZ . Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS92LV010A

SNLS007E –MAY 1998–REVISED APRIL 2013 www.ti.com 5V AC ELECTRICAL CHARACTERISTICS (1) TA = −40°C to+85°C, VCC = 5.0V± 0.5V Parameter TestConditions Min Typ Max Units DIFFERENTIAL DRIVER TIMING REQUIREMENTS tPHLD DifferentialProp.DelayHighto R L = 27Ω,See Figure4 and Figure5 0.5 2.7 4.5 ns Low C L = 10 pF tPLHD DifferentialProp.DelayLow to 0.5 2.5 4.5 ns High tSKD DifferentialSKEW |tPHLD - 0.2 1.0 ns tPLHD | tTLH TransitionTime Low toHigh 0.3 2.0 ns tTHL TransitionTime HightoLow 0.3 2.0 ns tPHZ DisableTime HightoZ R L = 27Ω,See Figure6 and Figure7 0.5 3.0 7.0 ns C L = 10 pFtPLZ DisableTime Low toZ 0.5 5.0 10.0 ns tPZH EnableTime Z toHigh 2.0 4.0 7.0 ns tPZL EnableTime Z toLow 1.0 4.0 9.0 ns DIFFERENTIAL RECEIVER TIMING REQUIREMENTS tPHLD DifferentialProp.DelayHighto See Figure8 and Figure9 2.5 5.0 12.0 ns Low C L = 10 pF tPLHD DifferentialProp.DelayLow to 2.5 4.6 10.0 ns High tSKD DifferentialSKEW |tPHLD - 0.4 2.0 ns tPLHD | tr RiseTime 1.2 2.5 ns tf FallTime 1.2 2.5 ns tPHZ DisableTime HightoZ R L = 500Ω,See Figure10 and Figure11 2.0 4.0 6.0 ns C L = 10 pF (2) tPLZ DisableTime Low toZ 2.0 4.0 6.0 ns tPZH EnableTime Z toHigh 2.0 5.0 9.0 ns tPZL EnableTime Z toLow 2.0 5.0 7.0 ns (1) Generatorwaveformsforalltestsunlessotherwisespecified:f= 1MHz, ZO = 50Ω,tr,tf≤ 6.0ns(0%–100%) on controlpinsand ≤ 1.0ns forRI inputs. (2) Forreceivertri-statedelays,theswitchissettoVCC fortPZL ,and tPLZ and toGND fortPZH ,and tPHZ . TEST CIRCUITS AND TIMING WAVEFORMS Figure3. DifferentialDriverDC TestCircuit

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20% 80%80% 20% DO+ DO- 1.5V 1.5V Differential0V 0V tTLH tTHL VDIFF = (DO+) - (DO-) tPHLD tPLHD D IN DO+, DO- (DO+) - (DO-) DS92LV010A www.ti.com SNLS007E –MAY 1998–REVISED APRIL 2013 Figure4. DifferentialDriverPropagationDelay and TransitionTime TestCircuit Figure5. DifferentialDriverPropagationDelay and TransitionTime Waveforms Figure6. DriverTRI-STATE Delay TestCircuit Figure7. DriverTRI-STATE Delay Waveforms Copyright© 1998–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS92LV010A

SNLS007E –MAY 1998–REVISED APRIL 2013 www.ti.com Figure8. ReceiverPropagationDelay and TransitionTime TestCircuit Figure9. ReceiverPropagationDelay and TransitionTime Waveforms Figure10. ReceiverTRI-STATE Delay TestCircuit Figure11. ReceiverTRI-STATE Delay Waveforms TRI-STATE Delay Waveforms TYPICAL BUS APPLICATION CONFIGURATIONS Figure12. Bi-DirectionalHalf-DuplexPoint-to-PointApplications

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APPLICATION INFORMATION

There are a few common practiceswhich should be impliedwhen designingPCB forBLVDS signaling. Recommended practicesare:

Use atleast4 layerPCB board(BLVDS signals,ground,power and TTL signals).
Keep driversand receiversas closetothe(BLVDS portside)connectoras possible.
Bypass each BLVDS deviceand alsouse distributedbulkcapacitance.Surfacemount capacitorsplaced closetopower and groundpinswork best.Two orthreemulti-layerceramic(MLC) surfacemount capacitors (0.1µF,and 0.01µF inparallelshouldbe used between each VCC and ground.The capacitorsshouldbe as closeas possibletotheVCC pin.
Use theterminationresistorwhichbestmatches thedifferentialimpedance ofyourtransmissionline.
Leave unused LVDS receiverinputsopen (floating) Table1.FunctionalTable MODE SELECTED DE RE DRIVER MODE H H RECEIVER MODE L L TRI-STATE MODE L H LOOP BACK MODE H L Table2.TransmitterMode (1) INPUTS OUTPUTS DE DI DO+ DO − H L L H H H H L H 2 > & > 0.8 X X L X Z Z (1) L = Low state H = Highstate Table3.ReceiverMode (1) INPUTS OUTPUT RE (RI+)-(RI−) L L (< −100 mV) L L H (> +100 mV) H L 100 mV > & > −100 mV X H X Z (1) X = HighorLow logicstate Z = Highimpedance state L = Low state H = Highstate Table4.Device Pin Descriptions Pin Name Pin No. Input/Output Description DIN 2 I TTL DriverInput DO ±/RI± 6,7 I/O LVDS DriverOutputs/LVDSReceiverInputs R OUT 3 O TTL ReceiverOutput RE 5 I ReceiverEnableTTL Input(ActiveLow) DE 1 I DriverEnableTTL Input(ActiveHigh) GND 4 NA Ground VCC 8 NA Power Supply

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www.ti.com SNLS007E –MAY 1998–REVISED APRIL 2013

REVISION HISTORY

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS92LV010ATM/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 LV010 ATM DS92LV010ATM/NOPB.A Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 LV010 ATM DS92LV010ATMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LV010 ATM DS92LV010ATMX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 LV010 ATM (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

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PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92LV010ATMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DS92LV010ATM/NOPB D SOIC 8 95 495 8 4064 3.05 DS92LV010ATM/NOPB.A D SOIC 8 95 495 8 4064 3.05 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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Product Information

DS92LV010ATMX/NOPB.A specifications and overview.

Summary

DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver REVISED APRIL 2013

Description

DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver REVISED APRIL 2013

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