DS92LV010A

DS92LV010A NSC | Alldatasheet

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Features

n Bus LVDS Signaling (BLVDS) n Designed for Double Termination Applications n Balanced Output Impedance n Lite Bus Loading 5pF typical n Glitch free power up/down (Driver disabled) n 3.3V or 5.0V Operation n ±1V Common Mode Range n ±100mV Receiver Sensitivity n High Signaling Rate Capability (above 100 Mbps) n Low Power CMOS design n Product offered in 8 lead SOIC package n Industrial Temperature Range Operation Connection Diagram Block Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. DS100052-1 Order Number DS92LV010ATM See NS Package Number M08A DS100052-2 May 1998 DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver © 1998 National Semiconductor Corporation DS100052 www.national.com

Absolute Maximum Ratings(Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC ) 6.0V Enable Input Voltage (DE, RE) −0.3V to (VCC + 0.3V) Driver Input Voltage (DIN) −0.3V to (VCC + 0.3V) Receiver Output Voltage (ROUT ) −0.3V to (VCC + 0.3V) Bus Pin Voltage (DO/RI±) −0.3V to + 3.9V Driver Short Circuit Current Continuous ESD (HBM 1.5 kΩ , 100 pF) >2.0 kV Maximum Package Power Dissipation at 25˚C SOIC 1025 mW Derate SOIC Package 8.2 mW/˚C Storage Temperature Range −65˚C to +150˚C Lead Temperature (Soldering, 4 sec.) 260˚C Recommended Operating Conditions Min Max Units Supply Voltage (VCC ), or 3.0 3.6 V Supply Voltage (VCC ) 4.5 5.5 V Receiver Input Voltage 0.0 2.9 V Operating Free Air Temperature −40 +85 ˚C TA = −40˚C to +85˚C unless otherwise noted, VCC = 3.3V± 0.3V Symbol Parameter Conditions Pin Min Typ Max Units VOD Output Differential Voltage R L =2 7Ω ,Figure 1 DO+/RI+, DO−/RI− 140 250 360 mV ΔVOD VOD Magnitude Change 33 0 m V VOS Offset Voltage 1 1.25 1.65 V ΔVOS Offset Magnitude Change 55 0 m V IOSD Output Short Circuit Current VO = 0V, DE = VCC −12 −20 mA VOH Voltage Output High V ID = +100 mV I OH = −400 µA R OUT 2.8 3 V Inputs Open 2.8 3 V Inputs Shorted 2.8 3 V Inputs Terminated, R L =2 7Ω 2.8 3 V VOL Voltage Output Low I OL = 2.0 mA, VID = −100 mV 0.1 0.4 V IOS Output Short Circuit Current VOUT = 0V, VID = +100 mV −5 −35 −85 mA VTH Input Threshold High DE = 0V DO+/RI+, DO−/RI− +100 mV VTL Input Threshold Low −100 mV IIN Input Current DE = 0V, V IN = +2.4V, or 0V −20 ±1 +20 µA VCC = 0V, VIN = +2.4V, or 0V −20 ±1 +20 µA VIH Minimum Input High Voltage DIN, DE, RE

2.0 V CC V

GND 0.8 V IIH Input High Current V IN =V CC or 2.4V ±1 ±10 µA IIL Input Low Current V IN = GND or 0.4V ±1 ±10 µA VCL Input Diode Clamp Voltage ICLAMP = −18 mA −1.5 −0.8 V ICCD Power Supply Current DE = RE = V CC ,R L =2 7Ω V CC 13 20 mA ICCR D E=R E=0 V 58 m A ICCZ DE = 0V, RE = VCC 3 7.5 mA ICC D E=V CC ,R E=0 V ,RL =2 7Ω 16 22 mA www.national.com 2

TA = −40˚C to +85˚C unless otherwise noted, VCC = 3.3V± 0.3V Symbol Parameter Conditions Pin Min Typ Max Units C output Capacitance@ BUS Pins DO+/RI+, DO−/RI− 5p F TA = −40˚C to +85˚C unless otherwise noted, VCC = 5.0V± 0.5V Symbol Parameter Conditions Pin Min Typ Max Units VOD Output Differential Voltage R L =2 7Ω ,Figure 1 DO+/RI+, DO−/RI− 145 270 390 mV ΔVOD VOD Magnitude Change 33 0 m V VOS Offset Voltage 1 1.35 1.65 V ΔVOS Offset Magnitude Change 55 0 m V IOSD Output Short Circuit Current VO = 0V, DE = VCC −12 −20 mA VOH Voltage Output High V ID = +100 mV I OH = −400 µA R OUT 4.3 5.0 V Inputs Open 4.3 5.0 V Inputs Shorted 4.3 5.0 V Inputs Terminated, R L =2 7Ω 4.3 5.0 V VOL Voltage Output Low I OL = 2.0 mA, VID = −100 mV 0.1 0.4 V IOS Output Short Circuit Current VOUT = 0V, VID = +100 mV −35 −90 −130 mA VTH Input Threshold High DE = 0V DO+/RI+, DO−/RI− +100 mV VTL Input Threshold Low −100 mV IIN Input Current DE = 0V, V IN = +2.4V, or 0V −20 ±1 +20 µA VCC = 0V, VIN = +2.4V, or 0V −20 ±1 +20 µA VIH Minimum Input High Voltage DIN, DE, RE GND 0.8 V IIH Input High Current V IN =V CC or 2.4V ±1 ±10 µA IIL Input Low Current V IN = GND or 0.4V ±1 ±10 µA VCL Input Diode Clamp Voltage ICLAMP = −18 mA −1.5 −0.8 V ICCD Power Supply Current DE = RE = V CC ,R L =2 7Ω V CC 17 25 mA ICCR D E=R E=0 V 61 0 m A ICCZ DE = 0V, RE = VCC 38 m A ICC D E=V CC ,R E=0 V ,RL =2 7Ω 20 25 mA C output Capacitance@ BUS Pins DO+/RI+, DO−/RI− 5p F Note 1:“Absolute Maximum Ratings” are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2:All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground except VOD ,VID,VTH and VTL unless otherwise specified. Note 3:All typicals are given for VCC = +3.3V or 5.0 V and TA = +25˚C, unless otherwise stated. Note 4:ESD Rating: HBM (1.5 kΩ , 100 pF)> 2.0 kV EAT (0Ω , 200 pF)> 300V. Note 5:C L includes probe and fixture capacitance. Note 6:Generator waveforms for all tests unless otherwise specified: f = 1MHz, ZO = 50Ω ,t r ,t f≤ 6.0ns (0% –100% ) on control pins and≤ 1.0ns for RI inputs. Note 7:The DS92LV010A is a current mode device and only function with datasheet specification when a resistive load is applied between the driver outputs. Note 8:For receiver TRI-STATE® delays, the switch is set to VCC for tPZL , and tPLZ and to GND for tPZH , and tPHZ . www.national.com3

TA = −40˚C to +85˚C, VCC = 3.3V± 0.3V Symbol Parameter Conditions Min Typ Max Units DIFFERENTIAL DRIVER TIMING REQUIREMENTS t PHLD Differential Prop. Delay High to Low R L =2 7Ω ,Figures 2, 3 C L =1 0p F 1.0 3.0 5.0 ns tPLHD Differential Prop. Delay Low to High 1.0 2.8 5.0 ns tSKD Differential SKEW |tPHLD -tPLHD | 0.2 1.0 ns tTLH Transition Time Low to High 0.3 2.0 ns tTHL Transition Time High to Low 0.3 2.0 ns tPHZ Disable Time High to Z R L =2 7Ω ,Figures 4, 5 C L =1 0p F 0.5 4.5 9.0 ns tPLZ Disable Time Low to Z 0.5 5.0 10.0 ns tPZH Enable Time Z to High 2.0 5.0 7.0 ns tPZL Enable Time Z to Low 1.0 4.5 9.0 ns DIFFERENTIAL RECEIVER TIMING REQUIREMENTS t PHLD Differential Prop. Delay High to Low Figures 6, 7 C L =1 0p F 2.5 5.0 12.0 ns tPLHD Differential Prop. Delay Low to High 2.5 5.5 10.0 ns tSKD Differential SKEW |tPHLD -tPLHD | 0.5 2.0 ns tr Rise Time 1.5 4.0 ns tf Fall Time 1.5 4.0 ns tPHZ Disable Time High to Z R L = 500Ω ,Figures 8, 9 C L = 10 pF (Note 8) 2.0 4.0 6.0 ns tPLZ Disable Time Low to Z 2.0 5.0 7.0 ns tPZH Enable Time Z to High 2.0 7.0 13.0 ns tPZL Enable Time Z to Low 2.0 6.0 10.0 ns TA = −40˚C to +85˚C, VCC = 5.0V± 0.5V Symbol Parameter Conditions Min Typ Max Units DIFFERENTIAL DRIVER TIMING REQUIREMENTS t PHLD Differential Prop. Delay High to Low R L =2 7Ω ,Figures 2, 3 C L =1 0p F 0.5 2.7 4.5 ns tPLHD Differential Prop. Delay Low to High 0.5 2.5 4.5 ns tSKD Differential SKEW |tPHLD -tPLHD | 0.2 1.0 ns tTLH Transition Time Low to High 0.3 2.0 ns tTHL Transition Time High to Low 0.3 2.0 ns tPHZ Disable Time High to Z R L =2 7Ω ,Figures 4, 5 C L =1 0p F 0.5 3.0 7.0 ns tPLZ Disable Time Low to Z 0.5 5.0 10.0 ns tPZH Enable Time Z to High 2.0 4.0 7.0 ns tPZL Enable Time Z to Low 1.0 4.0 9.0 ns DIFFERENTIAL RECEIVER TIMING REQUIREMENTS t PHLD Differential Prop. Delay High to Low Figures 6, 7 C L =1 0p F 2.5 5.0 12.0 ns tPLHD Differential Prop. Delay Low to High 2.5 4.6 10.0 ns tSKD Differential SKEW |tPHLD -tPLHD | 0.4 2.0 ns tr Rise Time 1.2 2.5 ns tf Fall Time 1.2 2.5 ns www.national.com 4

• Bypass each BLVDS device and also use distributed bulk capacitance. Surface mount capacitors placed close to power and ground pins work best. Two or three multi- layer ceramic (MLC) surface mount capacitors (0.1 µF, and 0.01 µF in parallel should be used between each V CC and ground. The capacitors should be as close as pos- sible to the V CC pin.
• Use the termination resistor which best matches the dif- ferential impedance of your transmission line.
• Leave unused LVDS receiver inputs open (floating)

TABLE 1. Functional Table TABLE 2. Transmitter Mode TABLE 3. Receiver Mode TABLE 4. Device Pin Description

Physical Dimensionsinches (millimeters) unless otherwise noted LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail- ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 Order Number DS92LV010ATM See NS Package Number M08A DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.