Logic IC

DS92CK16TMTC

Texas Instruments

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver REVISED APRIL 2013

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www.ti.com SNAS044C –NOVEMBER 1999–REVISED APRIL 2013 DS92CK163VBLVDS1to6ClockBuffer/BusTransceiver Check forSamples: DS92CK16 1FEATURES DESCRIPTION The DS92CK16 1 to6 ClockBuffer/BusTransceiver 2• Master/SlaveClock Selectionina Backplane is a one to sixCMOS differentialclockdistributionApplication deviceutilizingBus Low VoltageDifferentialSignaling• 125 MHz Operation(Typical) (BLVDS) technology.Thisclockdistributiondeviceis

100 ps Duty Cycle Distortion(Typical) designed forapplicationsrequiringultralow power dissipation,low noise,and high data rates.The• 50 ps Channel toChannel Skew (Typical) BLVDS sideisa transceiverwitha separatechannel• 3.3VPower Supply Design actingas a return/sourceclock.
Glitch-freePower on atCLKI/O Pins The DS92CK16 accepts LVDS (300 mV typical)• Low Power Design (20mA @ 3.3VStatic) differentialinputlevels,and translatesthem to 3V
Accepts Small Swing (300mV Typical) CMOS outputlevels.An outputenablepinOE ,when high,forcesallCLK OUT pinshigh.DifferentialSignalLevels
IndustrialTemperature OperatingRange (-40°C The devicecan be used as a source synchronous to+85°C) driver.The selectionof the source drivingis controlledby theCrdCLK IN and DE pins.Thisdevice• Availablein24-pinTSSOP Packaging can be the master clock,drivingthe inputsof other clock I/O pins in a multipointenvironment.Easy master/slaveclock selectionis achieved along a backplane. FunctionDiagram and TruthTable Table1.Receive Mode TruthTable INPUT OUTPUT OE DE CrdCLK IN (CLKI/O+)–(CLKI/O−) CLK OUT H H X X H L H X VID≥ 0.07V H L H X VID≤ −0.07V L Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1999–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNAS044C –NOVEMBER 1999–REVISED APRIL 2013 www.ti.com Table2.DriverMode TruthTable INPUT OUTPUT OE DE CrdCLK IN CLK/I/O+ CLKI/O− CLK OUT L L L L H L L L H H L H H L L L H H H L H H L H H H X Z Z H Connection Diagram See Package Number PW (R-PDSO-G24) TSSOP PACKAGE PIN DESCRIPTIONS Pin Name Pin # Type Description CLKI/O+ 6 I/O True(Positive)sideofthedifferentialclockinput. CLKI/O− 7 I/O Complementary(Negative)sideofthedifferentialclockinput. OE 2 I OE; thispinisactiveLow. When High,thispinforcesallCLK OUT pinsHigh.When Low, CLK OUT pinslogicstateisdeterminedby eithertheCrdCLK IN ortheVID attheCLK/I/Opins withrespecttothelogiclevelattheDE pin.Thispinhas a weak pullupdevicetoVCC .IfOE isfloating,thenallCLK OUT pinswillbe High. DE 11 I DE; thispinisactiveLOW. When Low, thispinenablestheCardCLK IN signaltotheCLKI/O pinsand CLK OUT pins.When High,theDriverisTRI-STATE, theCLKI/O pinsareinputsand determinethestateoftheCLK OUT pins.Thispinhas a weak pullupdevicetoVCC .IfDE is floating,thenCLKI/O pinsareTRI-STATE. CLK OUT 13,15,17, O 6 Bufferedclock(CMOS) outputs. 19,21,23 CrdCLK IN 9 I InputclockfromCard (CMOS levelorTTL level). VCC 16,20,24 Power VCC ;AnalogVCCA (InternallyseparatefromVCC ,connectexternallyoruse separatepower supplies).No specialpower sequencingrequired.EitherVCCA orVCC can be appliedfirst,or simultaneouslyapplybothpower supplies. GND 1,12,14,18, Ground GND VCCA 4 Power AnalogVCCA (InternallyseparatefromVCC ,connectexternallyoruse separatepower supplies).No specialpower sequencingrequired.EitherVCCA orVCC can be appliedfirst,or simultaneouslyapplybothpower supplies. GNDA 5,8 Ground AnalogGround (InternallyseparatefromGround must be connectedexternally). NC 3,10 No Connects

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www.ti.com SNAS044C –NOVEMBER 1999–REVISED APRIL 2013 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings (1)(2) SupplyVoltage(VCC ) −0.3Vto+4V EnableInputVoltage (DE, OE, CrdCLK IN) −0.3Vto+4V Voltage(CLKOUT ) −0.3Vto(VCC + 0.3V) Voltage(CLKI/O±) −0.3Vto+4V DriverShortCircuitCurrent momentary ReceiverShortCircuitCurrent momentary Maximum Package Power Dissipationat+25°C DeratePW Package 8.2mW/ °C above +25°C θJA 95°C/W θJC 30°C/W StorageTemperatureRange −65°C to+150°C Lead TemperatureRange (Soldering,4 sec.) 260°C ESD Ratings:HBM (3) >3000V CDM (3) >1000V Machine Model (3) >200V (1) “AbsoluteMaximum Ratings”arethosevaluesbeyond whichthesafetyofthedevicecannotbe verified.These ratingsarenotmeant to implythatthedevicesshouldbe operatedattheselimits.The tableof“ElectricalCharacteristics”specifiesconditionsofdevice operation. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. (3) ESD Rating:ESD qualificationisperformedperthefollowing:HBM (1.5kΩ,100 pF),Machine Model (250V,0Ω),IEC 1000-4-2.AllVCC pinsconnectedtogether,allgroundpinsconnectedtogether. Recommended OperatingConditions Min Typ Max Units SupplyVoltage(VCC ) +3.0 +3.3 +3.6 V CrdCLK IN,DE, OE InputVoltage 0 VCC V OperatingFreeAir Temperature(TA) −40 25 +85 °C DC ElectricalCharacteristics Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified(1)(2). Symbol Parameter Conditions Pin Min Typ Max Units VTH InputThresholdHigh CLKI/O+, 25 +70 mV CLKI/O−VTL InputThresholdLow −70 -35 mV VCMR Common Mode Voltage VID = 250 mV pk topk |VID|/2 2.4-|VID|/2 VRange (3) IIN InputCurrent VIN = 0V toVCC ,DE = VCC ,OE = −20 ±5 +20 µAVCC ,OtherInput= 1.2V± 50 mV (1) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Allvoltagesarereferencedtoground exceptVID,VOD, VTH, and VTL. (2) Alltypicalsaregivenfor:VCC = +3.3V and TA = +25°C. (3) The VCMR rangeisreducedforlargerVID.Example:IfVID=400 mV, thenVCMR is0.2Vto2.2VA VID up to|VCC –0V|may be applied between theCLKI/O+ and CLKI/O− inputs,withtheCommon Mode settoVCC /2. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS92CK16

SNAS044C –NOVEMBER 1999–REVISED APRIL 2013 www.ti.com DC ElectricalCharacteristics(continued) Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified(1)(2). Symbol Parameter Conditions Pin Min Typ Max Units VOH1R OutputHighVoltage VID = 250 mV, IOH = −1.0mA CLK OUT VCC −0.4 2.9 V VOH2R OutputHighVoltage VID = 250 mV, IOH = −6 mA VCC −0.8 2.5 V VOL1R OutputLow Voltage IOL = 1.0mA, VID = −250 mV 0.06 0.3 V VOL2R OutputLow Voltage IOL = 6 mA, VID = −250 mV 0 0.4 V IODHR CLK OUT Dynamic Output VID = +250 mV, VOUT = VCC −1V −8 -16 -30 mACurrent(4) IODLR CLK OUT Dynamic Output VID = −250 mV, VOUT = 1V 10 21 35 mACurrent(4) VIH InputHighVoltage DE, OE, 2.0 VCC V CrdCLK INVIL InputLow Voltage GND 0.8 V IIH InputHighCurrent VIN = VCC or2.4V OE, DE −10 −2 +10 µA IIL InputLow Current VIN = GND or0.4V −20 −5 +20 µA IINCRD InputCurrent VIN = 0V toVCC ,OE = VCC CrdCLK IN −5 +5 µA VCL InputVoltageClamp IOUT = −1.5mA OE, DE, −0.8 VCrdCLK IN ICC No Load SupplyCurrent OE = DE = 0V, VCC OutputsEnabled,No VID CrdCLK IN = VCC orGND, 13 mAApplied CLKI/O (±)= Open CLK OUT (0:5)= Open Circuit ICC1 No Load SupplyCurrent OE = GND OutputsEnabled,VID over DE = VCC Common Mode Voltage CrdCLK IN = VCC orGND, 10 mARange VID = 250 mV (0.125VVCM 2.275V), CLK OUT (0:5)= Open Circuit ICCD DriverLoaded Supply DE = OE = 0V, Current CrdCLK IN = VCC orGND, R L = 37.5Ω between CLKI/O+ and 20 25 mA CLKI/O−, CLK OUT (0:5)= Open Circuit VOD DriverOutputDifferential R L = 37.5Ω,Figure5 CLKI/O+, 250 350 450 mVVoltage DE = 0V CLKI/O− ΔVOD DriverVOD Magnitude 10 20 mVChange VOS DriverOffsetVoltage 1.1 1.29 1.5 V ΔVOS DriverOffsetVoltage 5 20 mVMagnitudeChange VOHD DriverOutputHigh 1.35 1.8 V VOLD DriverOutputLow 0.80 1.05 V IOS1D DriverDifferentialShort CrdCLK IN = VCC orGND, VOD = 0V, |30| |50| mACircuitCurrent(5) (outputsshortedtogether)DE = 0V IOS2D DriverOutputShortCircuit CrdCLK IN = GND, DE = 0V,CLKI/O+ 36 70 mACurrenttoVCC (5) = VCC IOS3D DriverOutputShortCircuit CrdCLK IN = VCC ,DE = 0V,CLKI/O− 34 70 mACurrenttoVCC (5) = VCC IOS4D DriverOutputShortCircuit CrdCLK IN = VCC ,DE = 0V,CLKI/O+ −47 −70 mACurrenttoGND (5) = 0V IOS5D DriverOutputShortCircuit CrdCLK IN = GND, DE = 0V,CLKI/O− −50 −70 mACurrenttoGND (5) = 0V IOFF Power OffLeakage Current VCC = 0V orOpen, ±20 µAVAPPLIED = 3.6V (4) Onlyone outputshouldbe momentarilyshortedata time.Do notexceed package power dissipationrating. (5) Onlyone outputshouldbe momentarilyshortedata time.Do notexceed package power dissipationrating.

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www.ti.com SNAS044C –NOVEMBER 1999–REVISED APRIL 2013 SwitchingCharacteristics Over SupplyVoltageand OperatingTemperatureranges,unlessotherwisespecified(1)(2). Symbol Parameter Conditions Min Typ Max Units DIFFERENTIAL RECEIVER CHARACTERISTICS tPHLDR DifferentialPropagationDelayHightoLow. CLKI/O toCLK OUT C L = 15 pF 1.3 2.8 3.8 ns VID = 250 mVtPLHDR DifferentialPropagationDelayLow toHigh.CLKI/O toCLK OUT 1.3 2.9 3.8 nsFigure1 Figure2 tSK1R DutyCycleDistortion(3) (pulseskew) 100 400 ps |tPLH –tPHL | tSK2R ChanneltoChannelSkew; Same Edge (4) 30 80 ps tSK3R ParttoPartSkew (5) 2.5 ns tTLHR TransitionTime Low toHigh (6) tTHLR TransitionTime HightoLow (6) tPLHOER PropagationDelayLow toHigh C L = 15 pF 1.0 3 4.5 ns(OEto CLK OUT ) Figure3 Figure4 tPHLOER PropagationDelayHightoLow 1.0 3 4.5 ns(OE toCLK OUT ) fMAX Maximum OperatingFrequency(7) 100 125 MHz DIFFERENTIAL DRIVER TIMING REQUIREMENTS Figure6 Figure7tPLHDD DifferentialPropagationDelayLow toHigh.CrdCLK IN to 0.5 1.8 2.5 nsCLKI/O tPHLCrd CrdCLK IN toCLK OUT PropagationDelayHightoLow C L = 15 pF 2.0 4.5 6.0 ns Figure8 Figure9tPLHCrd CrdCLK IN toCLK OUT PropagationDelayLow toHigh 2.0 4.5 6.0 ns tSK1D DutyCycleDistortion(pulseskew) 600 ps|tPLH –tPHL |(8) tSK2D DifferentialPart-to-PartSkew (9) 2.0 ns tTLHD DifferentialTransitionTime (6) tTHLD DifferentialTransitionTime (6) tPHZD TransitionTime HightoTRI-STATE. DE toCLKI/O 10 ns tPLZD TransitionTime Low toTRI-STATE. DE toCLKI/O VIN = 0V toVCC 10 ns C L = 15 pF,tPZHD TransitionTime TRI-STATE toHigh.DE toCLKI/O 32 nsR L = 37.5Ω tPZLD TransitionTime TRI-STATE toLow. DE toCLKI/O 32 nsFigure10 Figure11 fMAX Maximum OperatingFrequency(7) 100 125 MHz (1) C L includesprobeand fixturecapacitance. (2) Generatorwaveform foralltestsunlessotherwisespecified:f= 25 MHz, Zo = 50Ω,tr = 1 ns,tf= 1 ns (10%–90%).To ensurefastest propagationdelayand minimum skew,clockinputedge ratesshouldnotbe slowerthan1 ns/V;controlsignalsnotslowerthan3 ns/V. Ingeneral,thefastertheinputedge rate,thebettertheAC performance. (3) tSK1R isthedifferenceinreceiverpropagationdelay(|tPLH –tPHL |)ofone device,and isthedutycycledistortionoftheoutputatany given temperatureand VCC .The propagationdelayspecificationisa devicetodeviceworstcase overprocess,voltageand temperature. (4) tSK2R isthedifferenceinreceiverpropagationdelaybetween channelsinthesame deviceofany outputsswitchinginthesame direction.Thisparameterisspecifiedby designand characterization. (5) tSK3R, part-to-partskew,isthedifferenceinreceiverpropagationdelaybetween devicesofany outputsswitchinginthesame direction. Thisspecificationappliestodevicesoverrecommended operatingtemperatureand voltageranges,and acrossprocessdistribution. TSK3R isdefinedas Max –Min differentialpropagationdelay.Thisparameterisspecifiedby designand characterization. (6) Alldeviceoutputtransitiontimesarebased on characterizationmeasurements and arespecifiedby design. (7) Generatorinputconditions:tr/tf< 1 ns,50% dutycycle,differential(1.10Vto1.35Vpk-pk).OutputCriteria:60%/40% dutycycle, VOL (max)0.4V,VOH (min)2.7V,Load = 7 pF (strayplusprobes). (8) tSK1D isthedifferenceindriverpropagationdelay(|tPLH –tPHL |)and isthedutycycledistortionoftheCLKI/O outputs. (9) tSK2D part-to-partskew,isthedifferenceindriverpropagationdelaybetween devicesofany outputsswitchinginthesame direction. Thisspecificationappliestodevicesoverrecommended operatingtemperatureand voltageranges,and acrossprocessdistribution. tSK2D isdefinedas Max –Min differentialpropagationdelay. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS92CK16

SNAS044C –NOVEMBER 1999–REVISED APRIL 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION Figure1. ReceiverPropagationDelay and TransitionTime TestCircuit Generatorwaveform foralltestunlessotherwisespecified:f= 25 MHz, 50% DutyCycle,Zo = 50Ω,tTLH = 1 ns,tTHL = 1 ns. Figure2. ReceiverPropagationDelay and TransitionTime Waveforms Figure3. Output Enable (OE) Delay TestCircuit Figure4. Output Enable (OE) Delay Waveforms

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www.ti.com SNAS044C –NOVEMBER 1999–REVISED APRIL 2013 Figure5. DifferentialDriverDC Test Figure6. DriverPropagationDelay TestCircuit Figure7. DriverPropagationDelay and TransitionTime Waveforms Figure8. CrdCLK IN PropagationDelay Time TestCircuit Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS92CK16

SNAS044C –NOVEMBER 1999–REVISED APRIL 2013 www.ti.com Figure9. CrdCLK IN PropagationDelay Time Waveforms Figure10. DriverTRI-STATE TestCircuit Figure11. DriverTRI-STATE Waveforms

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www.ti.com SNAS044C –NOVEMBER 1999–REVISED APRIL 2013 APPLICATIONS INFORMATION Generalapplicationguidelinesand hintsforBLVDS/LVDS transceivers,driversand receiversmay be foundin thefollowingapplicationnotes:LVDS Owner'sManual,AN805(SNOA233 ),AN807(SNLA027 ),AN808(SNLA028 ), AN903(SNLA034 ),AN905(SNLA035 ),AN916(SNLA219 ),AN971(SNLA165 ),AN977(SNLA166 ). BLVDS driversand receiversare intendedtobe used ina differentialbackplaneconfiguration.Transceiversor receiversare connectedtothedriverthrougha balancedmedia such as differentialPCB traces.Typically,the characteristicdifferentialimpedance ofthemedia (Zo)isintherangeof50Ω to100Ω.Two terminationresistorsof ZoΩ each are placedat the ends of the transmissionlinebackplane.The terminationresistorconvertsthe currentsourced by the driverintoa voltagethatis detectedby the receiver.The effectsof mid-stream connector(s),cablestub(s),and otherimpedance discontinuitiesas wellas ground shifting,noisemarginlimits, and totalterminationloadingmust be takenintoaccount. The DS92CK16 differentiallinedriverisa balancedcurrentsource design.A currentmode driver,generally speakinghas a high outputimpedance (100 ohms) and suppliesa constantcurrentfora range of loads(a voltagemode driveron the otherhand suppliesa constantvoltagefora range of loads).Currentisswitched throughtheloadinone directiontoproducea logicstateand intheotherdirectiontoproducetheotherlogic state.The outputcurrentistypically9.330mA. The currentchanges as a functionofloadresistor.The current mode requires(as discussedabove) thata resistiveterminationbe employed to terminatethe signaland to complete the loop.Unterminatedconfigurationsare not allowed.The 9.33 mA loop currentwilldevelop a differentialvoltageof about 350mV across37.5Ω (doubleterminated75Ω differentialtransmissionbackplane) effectiveresistance,which the receiverdetectswitha 280 mV minimum differentialnoisemargin neglecting resistivelinelosses(drivensignalminus receiverthreshold(350mV – 70 mV = 280 mV)).The signaliscentered around+1.2V (DriverOffset,VOS )withrespecttoground.Note thatthesteady-statevoltage(VSS )peak-to-peak swingistwicethedifferentialvoltage(VOD )and istypically700 mV. The currentmode driverprovidessubstantialbenefitsovervoltagemode drivers,such as an RS-422 driver.Its quiescentcurrentremainsrelativelyflatversusswitchingfrequency.Whereas theRS-422 voltagemode driver increasesexponentiallyinmost case between 20 MHz –50 MHz. Thisisdue to the overlapcurrentthatflows between therailsofthedevicewhen theinternalgatesswitch.Whereas thecurrentmode driverswitchesa fixed currentbetween itsoutputwithoutany substantialoverlapcurrent.This is similarto some ECL and PECL devices,but withoutthe heavy staticICC requirementsof the ECL/PECL designs.LVDS requires> 80% less currentthansimilarPECL devices.AC specificationsforthedriverarea tenfoldimprovementoverotherexisting RS-422 drivers. The TRI-STATE functionallowsthedriveroutputstobe disabled,thusobtainingan even lowerpower statewhen thetransmissionofdataisnotrequired. POWER DECOUPLING RECOMMENDATIONS Bypass capacitorsmust be used on power pins.High frequencyceramic(surfacemount isrecommended) 0.1µF inparallelwith0.01µF,inparallelwith0.001µF atthepower supplypinas wellas scatteredcapacitorsoverthe printedcircuitboard.Multipleviasshouldbe used toconnectthedecouplingcapacitorstothepower planes.A 4.7µF (35V)or greatersolidtantalumcapacitorshouldbe connectedat the power entrypointon the printed circuitboard. PC BOARD CONSIDERATIONS Use atleast4 PCB layers(toptobottom);BLVDS signals,ground,power,TTL signals. IsolateTTL signalsfrom BLVDS signals,otherwisetheTTL may coupleontotheBLVDS lines.Itisbesttoput TTL and BLVDS signalson differentlayerswhichareisolatedby a power/groundplane(s). Keep driversand receiversas closeto the (BLVDS portside)connectorsas possibleto createshortstub lengths. Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS92CK16

SNAS044C –NOVEMBER 1999–REVISED APRIL 2013 www.ti.com DIFFERENTIAL TRACES Use controlledimpedance traceswhich match the differentialimpedance of your transmissionmedium (ie. backplaneorcable)and terminationresistor(s).Run thedifferentialpairtracelinesas closetogetheras possible as soon as theyleavetheIC .Thiswillhelpeliminatereflectionsand ensurenoiseiscoupledas common-mode. Infact,we have seen thatdifferentialsignalswhichare1mm apartradiatefarlessnoisethantraces3mm apart sincemagneticfieldcancellationismuch betterwiththe closertraces.Plus,noiseinducedon the differential linesismuch more likelytoappearas common-mode whichisrejectedby thereceiver. Match electricallengthsbetween tracesto reduce skew. Skew between the signalsof a pairmeans a phase differencebetween signalswhichdestroysthemagneticfieldcancellationbenefitsofdifferentialsignalsand EMI willresult.(Notethe velocityof propagation,v = c/Erwhere c (thespeed of light)= 0.2997mm/ps or 0.0118 in/ps).Do notrelysolelyon theautoroutefunctionfordifferentialtraces.Carefullyreviewdimensionstomatch differentialimpedance and provideisolationforthe differentiallines.Minimizethe number or viasand other discontinuitieson theline. Avoid90° turns(thesecause impedance discontinuities).Use arcsor45° bevels. Withina pairof traces,the distancebetween the two tracesshouldbe minimizedto maintaincommon-mode rejectionof the receivers.On the printedcircuitboard, thisdistanceshould remain constantto avoid discontinuitiesindifferentialimpedance.Minorviolationsatconnectionpointsareallowable. STUB LENGTH Stub lengthsshouldbe kepttoa minimum. The typicaltransitiontimeoftheDS92CK16 BLVDS outputis0.75ns a traceisgreaterthan1/5ofthetransitionedge,thenthetraceisconsidereda transmissionline.For example, 1.25ns/5is250 picoseconds.Letvelocityequal160ps per inchfora typicalloadedbackplane.Then maximum stublengthis250ps/160ps/inor 1.56inches.To determinethemaximum stubforyourbackplane,you need to know the propagationvelocityforthe actualconditions(referto applicationnotes AN – 905(SNLA035 ) and AN –808(SNLA028 )). TERMINATION Use a resistorwhich bestmatches thedifferentialimpedance ofyourloadedtransmissionline.Remember that thecurrentmode outputsneed theterminationresistortogeneratethedifferentialvoltage.BLVDS willnotwork withoutresistortermination. Surfacemount 1% to2% resistorsarebest. PROBING BLVDS TRANSMISSION LINES Always use highimpedance (> 100kΩ),low capacitance(< 2pF) scope probeswitha wide bandwidth(1GHz) scope.Improperprobingwillgivedeceivingresults. CABLES AND CONNECTORS, GENERAL COMMENTS Use controlledimpedance media.The connectorsyou use shouldhave a matched differentialimpedance of aboutZo Ω.They shouldnotintroducemajorimpedance discontinuities. Balanced cables(e.g.twistedpair)are usuallybetterthan unbalancedcables(ribboncable,simplecoax.)for noisereductionand signalquality.BalancedcablestendtogeneratelessEMI due tofieldcancelingeffectsand alsotendtopickup electromagneticradiationa common-mode (notdifferentialmode) noisewhichisrejectedby thereceiver.For cabledistances< 0.5M,most cablescan be made towork effectively.For distances0.5M ≤ d ≤ 10M, CAT 3 (category3)twistedpaircableworkswell,isreadilyavailableand relativelyinexpensive.

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www.ti.com SNAS044C –NOVEMBER 1999–REVISED APRIL 2013

REVISION HISTORY

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS92CK16TMTC Obsolete Production TSSOP (PW) | 24 - - Call TI Call TI -40 to 85 DS92CK16T MTC DS92CK16TMTC/NOPB Active Production TSSOP (PW) | 24 61 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 DS92CK16T MTC DS92CK16TMTC/NOPB.A Active Production TSSOP (PW) | 24 61 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 DS92CK16T MTC DS92CK16TMTCX/NOPB Active Production TSSOP (PW) | 24 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 DS92CK16T MTC DS92CK16TMTCX/NOPB.A Active Production TSSOP (PW) | 24 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 DS92CK16T MTC (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 23-May-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92CK16TMTCX/NOPB TSSOP PW 24 2500 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DS92CK16TMTC/NOPB PW TSSOP 24 61 495 8 2514.6 4.06 DS92CK16TMTC/NOPB.A PW TSSOP 24 61 495 8 2514.6 4.06 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 22X 0.65 7.15 24X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 7.9 7.7 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 12 13 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 12 13

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Product Information

DS92CK16TMTC specifications and overview.

Summary

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver REVISED APRIL 2013

Description

DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver REVISED APRIL 2013

Source title DS92CK16TMTC Datasheet(PDF) - Texas Instruments

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