DS92CK16

DS92CK16_06 NSC | Alldatasheet

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n Master/Slave clock selection in a backplane application n 125 MHz operation (typical) n 100 ps duty cycle distortion (typical) n 50 ps channel to channel skew (typical) n 3.3V power supply design n Glitch-free power on at CLKI/O pins n Low Power design (20 mA@ 3.3V static) n Accepts small swing (300 mV typical) differential signal levels n Industrial temperature operating range (-40˚C to +85˚C) n Available in 24-pin TSSOP Packaging Function Diagram and Truth Table 10108201 Receive Mode Truth Table INPUT OUTPUT OE DE CrdCLKIN (CLKI/O+)–(CLKI/O−) CLK OUT HH X X H L H X VID ≥ 0.07V H L H X VID ≤ −0.07V L L = Low Logic State H = High Logic State X = Irrelevant Z = TRI-STATE Driver Mode Truth Table INPUT OUTPUT OE DE CrdCLKIN CLK/I/O+ CLKI/O− CLK OUT LL L L H L LL H H L H HL L L H H HL H H L H HH X Z Z H TRI-STATE® is a registered trademark of National Semiconductor Corporation. April 2006 DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver © 2006 National Semiconductor Corporation DS101082 www.national.com

See NS Package Number MTC24 Pin Name Pin # Type Description CLKI/O+ 6 I/O True (Positive) side of the differential clock input. CLKI/O− 7 I/O Complementary (Negative) side of the differential clock input. OE 2 I OE; this pin is active Low. When High, this pin forces all CLK OUT pins High. When Low, CLKOUT pins logic state is determined by either the CrdCLKIN or the VID at the CLK/I/O pins with respect to the logic level at the DE pin. This pin has a weak pullup device to VCC.I fO Ei s floating, then all CLKOUT pins will be High. DE 11 I DE; this pin is active LOW. When Low, this pin enables the CardCLKIN signal to the CLKI/O pins and CLKOUT pins. When High, the Driver is TRI-STATE® , the CLKI/O pins are inputs and determine the state of the CLKOUT pins. This pin has a weak pullup device to VCC. If DE is floating, then CLKI/O pins are TRI-STATE. CLKOUT 13, 15, 17, 19, 21, 23 O 6 Buffered clock (CMOS) outputs. CrdCLKIN 9 I Input clock from Card (CMOS level or TTL level). VCC 16, 20, 24 Power V CC; Analog VCCA (Internally separate from VCC, connect externally or use separate power supplies). No special power sequencing required. Either V CCA or VCC can be applied first, or simultaneously apply both power supplies. GND 1, 12, 14, 18, 22 Ground GND V CCA 4 Power Analog V CCA (Internally separate from VCC, connect externally or use separate power supplies). No special power sequencing required. Either V CCA or VCC can be applied first, or simultaneously apply both power supplies. GNDA 5, 8 Ground Analog Ground (Internally separate from Ground must be connected externally). NC 3, 10 No Connects DS92CK16 www.national.com 2

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC) −0.3V to +4V Enable Input Voltage (DE, OE, CrdCLKIN) −0.3V to +4V Voltage (CLKOUT) −0.3V to (V CC + 0.3V) Voltage (CLKI/O±) −0.3V to +4V Driver Short Circuit Current momentary Receiver Short Circuit Current momentary Maximum Package Power Dissipation at +25˚C Derate TSSOP Package 8.2 mW/˚C above +25˚C θ JA 95˚C/W θJC 30˚C/W Storage Temperature Range −65˚C to +150˚C Lead Temperature Range (Soldering, 4 sec.) 260˚C ESD Ratings: HBM (Note 2) >3000V CDM (Note 2) >1000V Machine Model (Note 2) >200V Recommended Operating Conditions Min Typ Max Units Supply Voltage (VCC) +3.0 +3.3 +3.6 V CrdCLKIN, DE, OE Input Voltage 0 V CC V Operating Free Air Temperature (TA) −40 25 +85 ˚C Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 3, 4). Symbol Parameter Conditions Pin Min Typ Max Units VTH Input Threshold High CLKI/O+, CLKI/O− 25 +70 mV VTL Input Threshold Low −70 -35 mV VCMR Common Mode Voltage Range (Note 5) VID = 250 mV pk to pk |VID|/2 2.4 - |VID|/2 V IIN Input Current V IN =0 Vt oVCC,D E=V CC,O E= VCC, Other Input = 1.2V± 50 mV −20 ±5 +20 µA VOH1R Output High Voltage VID = 250 mV, I OH = −1.0 mA CLK OUT VCC−0.4 2.9 V VOH2R Output High Voltage VID = 250 mV, I OH =− 6m A V CC−0.8 2.5 V VOL1R Output Low Voltage I OL = 1.0 mA, VID = −250 mV 0.06 0.3 V VOL2R Output Low Voltage I OL = 6 mA, VID = −250 mV 0 0.4 V IODHR CLKOUT Dynamic Output Current (Note 6) VID = +250 mV, VOUT =V CC−1V −8 -16 -30 mA IODLR CLKOUT Dynamic Output Current (Note 6) VID = −250 mV, VOUT =1 V 10 21 35 mA VIH Input High Voltage DE, OE, CrdCLKIN

2.0 V CC V

VIL Input Low Voltage GND 0.8 V IIH Input High Current V IN =V CC or 2.4V OE, DE −10 −2 +10 µA IIL Input Low Current V IN = GND or 0.4V −20 −5 +20 µA IINCRD Input Current V IN =0 Vt oVCC,O E=V CC CrdCLKIN −5 +5 µA VCL Input Voltage Clamp I OUT = −1.5 mA OE, DE, CrdCLKIN −0.8 V DS92CK16 www.national.com3

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 3, 4). Symbol Parameter Conditions Pin Min Typ Max Units ICC No Load Supply Current Outputs Enabled, No VID Applied O E=D E=0 V , CrdCLKIN =V CC or GND, CLKI/O (±) = Open CLKOUT (0:5) = Open Circuit VCC 13 mA ICC1 No Load Supply Current Outputs Enabled, VID over Common Mode Voltage Range OE = GND D E=V CC CrdCLKIN =V CC or GND, VID = 250 mV (0.125V VCM 2.275V), CLK OUT (0:5) = Open Circuit 10 mA ICCD Driver Loaded Supply Current D E=O E=0 V , CrdCLKIN =V CC or GND, RL = 37.5Ω between CLKI/O+ and CLKI/O−, CLK OUT (0:5) = Open Circuit 20 25 mA VOD Driver Output Differential Voltage RL = 37.5Ω, Figure 5 D E=0 V CLKI/O+, CLKI/O− 250 350 450 mV ∆VOD Driver VOD Magnitude Change 10 20 mV VOS Driver Offset Voltage 1.1 1.29 1.5 V ∆VOS Driver Offset Voltage Magnitude Change 52 0 m V VOHD Driver Output High 1.35 1.8 V VOLD Driver Output Low 0.80 1.05 V IOS1D Driver Differential Short Circuit Current (Note 6) CrdCLKIN =V CC or GND, VOD = 0V, (outputs shorted together) D E=0 V |30| |50| mA IOS2D Driver Output Short Circuit Current to VCC (Note 6) CrdCLKIN = GND, DE = 0V, CLKI/O+ = VCC 36 70 mA IOS3D Driver Output Short Circuit Current to VCC (Note 6) CrdCLKIN =V CC,D E=0 V , CLKI/O− = VCC 34 70 mA IOS4D Driver Output Short Circuit Current to GND (Note 6) CrdCLK IN =V CC,D E=0 V , CLKI/O+ = 0V −47 −70 mA IOS5D Driver Output Short Circuit Current to GND (Note 6) CrdCLK IN = GND, DE = 0V, CLKI/O− = 0V −50 −70 mA IOFF Power Off Leakage Current VCC = 0V or Open, VAPPLIED = 3.6V ±20 µA DS92CK16 www.national.com 4

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 7, 8). Symbol Parameter Conditions Min Typ Max Units DIFFERENTIAL RECEIVER CHARACTERISTICS t PHLDR Differential Propagation Delay High to Low. CLKI/O to CLKOUT CL =1 5p F VID = 250 mV Figures 1, 2 1.3 2.8 3.8 ns t PLHDR Differential Propagation Delay Low to High. CLKI/O to CLKOUT 1.3 2.9 3.8 ns tSK1R Duty Cycle Distortion(Note 10) (pulse skew) PLH–tPHL| 100 400 ps tSK2R Channel to Channel Skew; Same Edge (Note 11) 30 80 ps tSK3R Part to Part Skew (Note 12) 2.5 ns tTLHR Transition Time Low to High (Note 9) (20% to 80% ) 0.4 1.4 2.4 ns tTHLR Transition Time High to Low(Note 9) (80% to 20% ) 0.4 1.3 2.2 ns tPLHOER Propagation Delay Low to High ( OEto CLKOUT) CL =1 5p F Figures 3, 4 1.0 3 4.5 ns tPHLOER Propagation Delay High to Low (OE to CLKOUT) 1.0 3 4.5 ns fMAX Maximum Operating Frequency (Note 15) 100 125 MHz DIFFERENTIAL DRIVER TIMING REQUIREMENTS t PHLDD Differential Propagation Delay High to Low. CrdCLKIN to CLKI/O CL =1 5p F RL = 37.5Ω Figures 6, 7 0.5 1.8 2.5 ns tPLHDD Differential Propagation Delay Low to High. CrdCLKIN to CLKI/O 0.5 1.8 2.5 ns tPHLCrd CrdCLKIN to CLKOUT Propagation Delay High to Low C L =1 5p F Figures 8, 9 2.0 4.5 6.0 ns tPLHCrd CrdCLKIN to CLKOUT Propagation Delay Low to High 2.0 4.5 6.0 ns tSK1D Duty Cycle Distortion (pulse skew) |tPLH–tPHL| (Note 13) 600 ps tSK2D Differential Part-to-Part Skew (Note 14) 2.0 ns tTLHD Differential Transition Time (Note 9) (20% to 80% ) 0.4 0.75 1.4 ns tTHLD Differential Transition Time (Note 9) (80% to 20% ) 0.4 0.75 1.4 ns tPHZD Transition Time High to TRI-STATE. DE to CLKI/O 10 ns tPLZD Transition Time Low to TRI-STATE. DE to CLKI/O VIN =0 Vt oVCC CL =1 5p F , RL = 37.5Ω Figures 10, 11 10 ns tPZHD Transition Time TRI-STATE to High. DE to CLKI/O 32 ns tPZLD Transition Time TRI-STATE to Low. DE to CLKI/O 32 ns fMAX Maximum Operating Frequency (Note 15) 100 125 MHz Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. These ratings are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: ESD Rating: ESD qualification is performed per the following: HBM (1.5 kΩ, 100 pF), Machine Model (250V, 0Ω), IEC 1000-4-2. All VCC pins connected together, all ground pins connected together. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VID, VOD, VTH, and VTL. Note 4: All typicals are given for: VCC = +3.3V and TA = +25˚C. Note 5: The VCMR range is reduced for larger VID. Example: If VID=400 mV, then VCMR is 0.2V to 2.2V A VID up to |VCC–0V| may be applied between the CLKI/O+ and CLKI/O− inputs, with the Common Mode set to VCC/2. Note 6: Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating. Note 7: CL includes probe and fixture capacitance. Note 8: Generator waveform for all tests unless otherwise specified:f=2 5 MHz, Zo = 50Ω,t r = 1 ns, tf = 1 ns (10%–90%). To ensure fastest propagation delay and minimum skew, clock input edge rates should not be slower than 1 ns/V; control signals not slower than 3 ns/V. In general, the faster the input edge rate,the better the AC performance. Note 9: All device output transition times are based on characterization measurements and are guaranteed by design. DS92CK16 www.national.com5

General application guidelines and hints for BLVDS/LVDS transceivers, drivers and receivers may be found in the following application notes: LVDS Owner’s Manual (lit #550062-001), AN805, AN807, AN808, AN903, AN905, AN916, AN971, AN977 . BLVDS drivers and receivers are intended to be used in a differential backplane configuration. Transceivers or receiv- ers are connected to the driver through a balanced media such as differential PCB traces. Typically, the characteristic differential impedance of the media (Zo) is in the range of 50Ω to100Ω. Two termination resistors of ZoΩ each are placed at the ends of the transmission line backplane. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. The effects of mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. The DS92CK16 differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance (100 ohms) and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The output current is typically 9.330 mA. The current changes as a function of load resistor. The current moderequires (as discussed above) that a resistive termination be employed to terminate the signal and to com- plete the loop. Unterminated configurations are not allowed. The 9.33 mA loop current will develop a differential voltage of about 350mV across 37.5Ω (double terminated 75Ω differ- ential transmission backplane) effective resistance, which the receiver detects with a 280 mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (350 mV – 70 mV = 280 mV)). The signal is centered around +1.2V (Driver Offset, V OS) with respect to ground. Note that the steady-state voltage (VSS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 700 mV. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quies- cent current remains relatively flat versus switching fre- quency. Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static I CC requirements of the ECL/PECL designs. LVDS requires > 80% less current than similar PECL devices. AC specifi- cations for the driver are a tenfold improvement over other existing RS-422 drivers. The TRI-STATE function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. POWER DECOUPLING RECOMMENDATIONS Bypass capacitors must be used on power pins. High fre- quency ceramic (surface mount is recommended) 0.1µF in parallel with 0.01µF, in parallel with 0.001µF at the power supply pin as well as scattered capacitors over the printed circuit board. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 4.7µF (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board. PC BOARD CONSIDERATIONS Use at least 4 PCB layers (top to bottom); BLVDS signals, ground, power, TTL signals. Isolate TTL signals from BLVDS signals, otherwise the TTL may couple onto the BLVDS lines. It is best to put TTL and BLVDS signals on different layers which are isolated by a power/ground plane(s). Keep drivers and receivers as close to the (BLVDS port side) connectors as possible to create short stub lengths. DIFFERENTIAL TRACES Use controlled impedance traces which match the differen- tial impedance of your transmission medium (ie. backplane or cable) and termination resistor(s). Run the differential pair trace lines as close together as possible as soon as they leave the IC . This will help eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancella- tion is much better with the closer traces. Plus, noise in- duced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver. Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase differ- ence between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will re- sult. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not rely solely on the autoroute function for differential traces. Care- fully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the num- ber or vias and other discontinuities on the line. Avoid 90˚ turns (these cause impedance discontinuities). Use arcs or 45˚ bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allow- able. STUB LENGTH Stub lengths should be kept to a minimum. The typical transition time of the DS92CK16 BLVDS output is 0.75ns For a general approximation, if the electrical length of a trace is greater than 1/5 of the transition edge, then the trace is considered a transmission line. For example, 1.25ns/5 is 250 picoseconds. Let velocity equal 160ps per inch for a typical loaded backplane. Then maximum stub length is 250ps/ 160ps/in or 1.56 inches. To determine the maximum stub for your backplane, you need to know the propagation velocity for the actual conditions (refer to application notes AN– 905 and AN–808). TERMINATION Use a resistor which best matches the differential impedance of your loaded transmission line. Remember that the current mode outputs need the termination resistor to generate the differential voltage. BLVDS will not work without resistor termination. DS92CK16 www.national.com 10

Applications Information (Continued) Surface mount 1% to 2% resistors are best. PROBING BLVDS TRANSMISSION LINES Always use high impedance (> 100kΩ), low capacitance (< 2pF) scope probes with a wide bandwidth (1GHz) scope. Improper probing will give deceiving results. CABLES AND CONNECTORS, GENERAL COMMENTS Use controlled impedance media. The connectors you use should have a matched differential impedance of about Zo Ω. They should not introduce major impedance disconti- nuities. Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for noise reduction and signal quality. Balanced cables tend to gener- ate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not dif- ferential mode) noise which is rejected by the receiver. For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M≤ d ≤ 10M, CAT 3 (category 3) twisted pair cable works well, is readily available and rela- tively inexpensive. DS92CK16 www.national.com11

Physical Dimensions inches (millimeters) unless otherwise noted 24-Pin TSSOP Package Drawing Dimensions shown in millimeters Order Number DS92CK16TMTC National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. Leadfree products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com DS92CK16 3V BLVDS 1 to 6 Clock Buffer/Bus Transceiver