DS92001 TI | Alldatasheet
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www.ti.com SNLS147F –JUNE 2002–REVISED APRIL 2013 DS920013.3VB/LVDS-BLVDSBuffer Check forSamples: DS92001 1FEATURES DESCRIPTION The DS92001 B/LVDS-BLVDS Buffertakesa BLVDS 2• Single+3.3V Supply inputsignaland providesa BLVDS outputsignal.In• ReceiverInputsAccept LVDS/CML/LVPECL many largesystems,signalsare distributedacrossSignals backplanes.One of the limitingfactorsforsystem
- TRI-STATE Outputs speed isthe "stublength"or the distancebetween thetransmissionlineand theunterminatedreceivers• ReceiverInputThreshold< ±100 mV on individualcards. Although it is generally• FastPropagationDelay of1.4ns (typ) recognizedthatthisdistanceshouldbe as shortas
- Low Jitter400 Mbps FullyDifferentialData possibletomaximizesystem performance,real-world Path packagingconcernsoftenmake itdifficulttomake the stubsas shortas thedesignerwouldlike.• Compatible withBLVDS 10-bitSerDes (40MHz) The DS92001 has edge transitionsoptimizedfor• Compatible withANSI/TIA/EIA-644-ALVDS multidropbackplaneswhere the switchingfrequencyStandard isinthe200 MHz rangeorless.The outputedge rate• AvailableinSOIC and Space Saving WSON iscriticalinsome systems where longstubsmay bePackage present,and utilizinga slow transitionallowsfor
- IndustrialTemperature Range longerstublengths. The DS92001, availableinthe WSON package,will allowthe receiverinputsto be placedverycloseto the main transmissionline,thus improvingsystem performance. A wide inputdynamic range allowsthe DS92001 to receivedifferentialsignalsfrom LVPECL, CML as wellas LVDS sources.Thiswillallowthe deviceto also fillthe roleof an LVPECL-BLVDS or CML- BLVDS translator. Connection and Block Diagrams Figure1.SOIC Package Number D0008A Figure2.WSON Package Number NGK0008A Top View Top View Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2002–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SNLS147F –JUNE 2002–REVISED APRIL 2013 www.ti.com Table1.FunctionalOperation BLVDS Inputs BLVDS Outputs [IN+]− [IN−] OUT+ OUT − VID ≥ 0.1V H L VID ≤ −0.1V L H −0.1V≤ VID ≤ 0.1V Undefined Undefined These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) SupplyVoltage(VCC ) −0.3Vto+4V LVCMOS/LVTTL InputVoltage(EN) −0.3Vto(VCC + 0.3V) B/LVDS ReceiverInputVoltage(IN+,IN−) −0.3Vto+4V BLVDS DriverOutputVoltage(OUT+, OUT −) −0.3Vto+4V BLVDS OutputShortCircuitCurrent Continuous JunctionTemperature +150°C StorageTemperatureRange −65°C to+150°C Lead TemperatureRange Soldering(4sec.) +260°C Maximum Package Power Dissipationat D Package 726 mW 25°C DerateD Package 5.8mW/ °C above +25°C DerateNGK Package 19.49mW/ °C above +25°C ESD Ratings (HBM, 1.5kΩ,100pF) ≥2.5kV (EIAJ,0Ω,200pF) ≥250V (1) “AbsoluteMaximum Ratings”arethosevaluesbeyond whichthesafetyofthedevicecannotbe ensured.They arenotmeant toimply thatthedeviceshouldbe operatedattheselimits.The tableof“ElectricalCharacteristics”specifiesconditionsofdeviceoperation. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingConditions Min Typ Max Units SupplyVoltage(VCC ) 3.0 3.3 3.6 V ReceiverDifferentialInputVoltage(VID)withVCM =1.2V 0.1 2.4 |V| OperatingFreeAirTemperature −40 +25 +85 °C B/LVDS InputRise/Fall20% to80% 2 20 ns
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www.ti.com SNLS147F –JUNE 2002–REVISED APRIL 2013 ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units LVCMOS/LVTTL DC SPECIFICATIONS (EN) VIH HighLevelInputVoltage 2.0 VCC V VIL Low LevelInputVoltage GND 0.8 V IIH HighLevelInputCurrent VIN = VCC or2.0V +7 +20 μA IIL Low LevelInputCurrent VIN = GND or0.8V −10 ±1 +10 μA VCL InputClamp Voltage ICL = −18 mA −0.6 −1.5 V BLVDS OUTPUT DC SPECIFICATIONS (OUT) |VOD | DifferentialOutputVoltage(1) R L = 27Ω 250 350 500 mV R L = 50Ω 350 450 600 mV ΔVOD Change inMagnitudeofVOD forComplimentaryOutput RL = 27Ω or50Ω See Figure3 and Figure4 20 mV States VOS OffsetVoltage R L = 27Ω orR L = 50Ω 1.1 1.25 1.375 V ΔVOS Change inMagnitudeofVOS See Figure3 forComplimentaryOutput 2 20 mV States IOZ OutputTRI-STATE Current EN = 0V,VOUT = VCC orGND −20 ±5 +20 μA IOFF Power-OffLeakage Current VCC = 0V orOpen Circuit,VOUT = 3.6V −20 ±5 +20 μA IOS1 OutputShortCircuit EN = VCC ,VCM = 1.2V,VID = 200mV, VOUT+ = 0V,or −30 −60 mACurrent(3) VID = −200mV, VCM = 1.2V,VOUT − = 0V VID = −200mV, VCM = 1.2V,VOUT+ = VCC ,or 53 80 mAVID = 200mV, VCM =1.2V,VOUT − = VCC IOSD DifferentialOutputShort EN = VCC ,VID = |200mV|,VCM .= 1.2V,VOD = 0V CircuitCurrent(3) (connecttrueand complement outputsthrougha |30| |42| mA currentmeter) B/LVDS RECEIVER DC SPECIFICATIONS (IN) VTH DifferentialInputHigh VCM = +0.05V,+1.2V or+3.25V −30 −5 mV Threshold(4) VTL DifferentialInputLow −70 −30 mV Threshold(4) VCMR Common Mode Voltage |VID|/2 VCC V Range (4) −|VID|/2 IIN InputCurrent VIN = VCC VCC = 3.6Vor0V |1.5| |20| μA VIN = 0V |1.5| |20| μA ΔIIN Change inMagnitudeofIIN VIN = VCC 1 6 μA VIN = 0V 1 6 μA SUPPLY CURRENT ICCD TotalDynamic Supply EN = VCC ,R L = 27Ω or50Ω,C L = 15 pF, 50 65 mA Current(includesload Freq.= 200MHz 50% dutycycle, current) VID = 200mV, VCM = 1.2V ICCZ TRI-STATE SupplyCurrent EN = 0V,Freq.= 200MHz 50% dutycycle, 36 46 mA VID = 200mV, VCM = 1.2V (1) Currentintodevicepinsisdefinedas positive.Currentoutofdevicepinsisdefinedas negative.Allvoltagesarereferencedtoground exceptVID,VOD ,VTH ,VTL,and ΔVOD .VOD has a valueand direction.Positivedirectionmeans OUT+ isa more positivevoltagethan OUT −. (2) AlltypicalaregivenforVCC = +3.3V and TA = +25°C, unlessotherwisestated. (3) Outputshortcircuitcurrent(IOS )isspecifiedas magnitudeonly,minus signindicatesdirectiononly. (4) The parametersarespecifiedby design.The limitsarebased on statisticalanalysisofthedeviceperformanceoverthePVT (process, voltageand temperature)range. Copyright© 2002–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS92001
SNLS147F –JUNE 2002–REVISED APRIL 2013 www.ti.com AC ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1) Symbol Parameter Conditions Min Typ Max Units LVDS OUTPUT AC SPECIFICATIONS (OUT) tPHLD DifferentialPropagationDelayHigh VID = 200mV, VCM = 1.2V, 1.0 1.4 2.0 ns toLow (2) R L = 27Ω or50Ω,C L = 15pF See Figure5 and Figure6tPLHD DifferentialPropagationDelayLow 1.0 1.4 2.0 ns toHigh(2) tSKD1 PulseSkew |tPLHD − tPHLD | 0 20 200 ps (measureofdutycycle)(3)(4) tSKD3 Part-to-PartSkew (3)(5) 0 200 300 ps tSKD4 Part-to-PartSkew (3)(6) 0 1 ns tLHT RiseTime(3)(2) R L = 50Ω or27Ω,C L = 15pF 0.350 0.6 1.0 ns 20% to80% points See Figure5 and Figure7 tHLT FallTime(3)(2) 0.350 0.6 1.0 ns 80% to20% points tPHZ DisableTime (ActiveHightoZ) R L = 50Ω,C L = 15pF See Figure8 and Figure9 3 25 ns tPLZ DisableTime (ActiveLow toZ) 3 25 ns tPZH EnableTime (ZtoActiveHigh) 100 120 ns tPZL EnableTime (ZtoActiveLow) 100 120 ns tDJ LVDS Data Jitter,Deterministic VID = 300mV; PRBS = 223 − 1 data;VCM = 1.2Vat 78 ps(Peak-to-Peak)(7) 400Mbps (NRZ) tRJ LVDS ClockJitter,Random (7) VID = 300mV; VCM = 1.2Vat200MHz clock 36 ps fMAX Maximum specifiedfrequency(8) VID = 200mV, VCM = 1.2V 200 300 MHz (1) AlltypicalaregivenforVCC = +3.3V and TA = +25°C, unlessotherwisestated. (2) Propagationdelay,riseand falltimesarespecifiedby designand characterizationto200MHz. Generatorforthesetests:50MHz ≤ f≤ 200MHz, Zo = 50Ω,tr,tf≤ 0.5ns.Generatorused was HP8130A (300MHz capability). (3) The parametersarespecifiedby design.The limitsarebased on statisticalanalysisofthedeviceperformanceoverthePVT (process, voltageand temperature)range. (4) tSKD1 ,|tPLHD − tPHLD |,isthemagnitudedifferenceindifferentialpropagationdelaytimebetween thepositivegoingedge and thenegative goingedge ofthesame channel(ameasure ofdutycycle). (5) tSKD3 ,ParttoPartSkew, isdefinedas thedifferencebetween theminimum and maximum specifieddifferentialpropagationdelays.This specificationappliestodevicesatthesame VCC and within5°C ofeach otherwithintheoperatingtemperaturerange.Thisparameter specifiedby designand characterization. (6) tSKD4 ,ParttoPartSkew, isthedifferentialchannel-to-channelskew ofany eventbetween devices.Thisspecificationappliestodevices overrecommended operatingtemperatureand voltageranges,and acrossprocessdistribution.tSKD4 isdefinedas |Max − Min| differentialpropagationdelay. (7) The parametersarespecifiedby design.The limitsarebased on statisticalanalysisofthedeviceperformanceoverthePVT rangewith thefollowingtestequipmentsetup:Agilent86130A used as stimulus,5 feetofRG142B cablewithDUT testboardand Agilent86100A (digitalscope mainframe)withAgilent86122A (20GHz scope module).Data inputjitterpk topk = 22 picoseconds;Clockinputjitter= 24 picoseconds;tDJ measured 100 picoseconds,tRJ measured 60 picoseconds. (8) fMAX test:Generator(HP8133A orequivalent),Inputdutycycle= 50%. Outputcriteria:VOD ≥ 200mV, DutyCyclebetterthan45/55%. Thisspecificationisspecifiedby designand characterization.A minimum isspecified,whichmeans thatthedevicewilloperateto specifiedconditionsfromDC totheminimum specifiedAC frequency.The typicalvalueisalwaysgreaterthantheminimum specification.
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www.ti.com SNLS147F –JUNE 2002–REVISED APRIL 2013 DC TestCircuits Figure3. DifferentialDriverDC TestCircuit Figure4. DifferentialDriverFullLoad DC TestCircuit AC TestCircuitsand Timing Diagrams Figure5. BLVDS Output Load Figure6. PropagationDelay Low-to-Highand High-to-Low Figure7. BLVDS Output TransitionTime Copyright© 2002–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS92001
SNLS147F –JUNE 2002–REVISED APRIL 2013 www.ti.com Figure8. TRI-STATE Delay TestCircuit Figure9. Output activetoTRI-STATE and TRI-STATE toactiveoutputtime PIN DESCRIPTIONS Input/OutpPin Name Pin # Descriptionut GND 1 P Ground IN − 2 I InvertingreceiverB/LVDS inputpin IN+ 3 I Non-invertingreceiverB/LVDS inputpin N/C 4 NA "NO CONNECT" pin VCC 5 P Power Supply,3.3V± 0.3V. OUT+ 6 O Non-invertingdriverBLVDS outputpin OUT - 7 O InvertingdriverBLVDS outputpin EN 8 I Enablepin.When EN isLOW, thedriverisdisabledand theBLVDS outputs areinTRI-STATE. When EN isHIGH, thedriverisenabled.LVCMOS/LVTTL levels.
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connector connector connector Redundant Serializer DS92001 www.ti.com SNLS147F –JUNE 2002–REVISED APRIL 2013 TypicalApplications Figure10. Backplane Stub-HiderApplication Figure11. Cable RepeaterApplication Copyright© 2002–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS92001
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APPLICATION INFORMATION
The DS92001 can be used as a "stub-hider."Inmany systems,signalsare distributedacrossbackplanes,and one ofthelimitingfactorsforsystem speed isthe"stublength"orthedistancebetween thetransmissionlineand theunterminatedreceiverson theindividualcards.See Figure10.Althoughitisgenerallyrecognizedthatthis distanceshouldbe as shortas possibletomaximize system performance,real-worldpackagingconcernsand PCB designsoftenmake itdifficultto make the stubsas shortas the designerwould like.The DS92001, availableinthe WSON package,can improvesystem performanceby allowingthe receiverto be placedvery closeto the main transmissionlineeitheron the backplaneitselfor verycloseto the connectoron the card. LongertracestotheLVDS receivermay be placedaftertheDS92001. ThisverysmallWSON package isa 75% space savingsovertheSOIC package. The DS92001 may alsobe used as a repeateras shown inFigure11.The signalisrecoveredand redrivenatfull strengthdown thefollowingsegment.The DS92001 may alsobe used as a leveltranslator,as itacceptsLVDS, BLVDS, and LVPECL inputs. POWER DECOUPLING RECOMMENDATIONS Bypass capacitorsmust be used on power pins.Use highfrequencyceramic(surfacemount isrecommended) 0.1μF and 0.01μF capacitorsinparallelatthepower supplypinwiththesmallestvaluecapacitorclosesttothe devicesupplypin.Additionalscatteredcapacitorsovertheprintedcircuitboardwillimprovedecoupling.Multiple viasshouldbe used to connectthe decouplingcapacitorsto the power planes.A 10μF (35V)or greatersolid tantalumcapacitorshouldbe connectedatthepower entrypointon theprintedcircuitboardbetween thesupply and ground. PC BOARD CONSIDERATIONS Use atleast4 PCB boardlayers(toptobottom):LVDS signals,ground,power,TTL signals. IsolateTTL signalsfromLVDS signals,otherwisetheTTL signalsmay coupleontotheLVDS lines.Itisbestto putTTL and LVDS signalson differentlayerswhichareisolatedby a power/groundplane(s). Keep driversand receiversas closetothe(LVDS portside)connectorsas possible. For PC board considerationsforthe WSON package, please referto applicationnote AN-1187 “Leadless Leadframe Package” (LiteratureNumber SNOA401). Itis importantto note thatto optimizesignalintegrity (minimizejitterand noisecoupling),theWSON thermallandpad,whichisa metal(normallycopper)rectangular regionlocatedunderthepackage as seen inFigure12,shouldbe attachedtogroundand match thedimensions oftheexposed pad on thePCB (1:1ratio). Figure12. WSON Thermal Land Pad and Pin Pads DIFFERENTIAL TRACES Use controlledimpedance traceswhichmatch thedifferentialimpedance ofyourtransmissionmedium (ie.cable) and terminationresistor.Run thedifferentialpairtracelinesas closetogetheras possibleas soon as theyleave the IC (stubsshouldbe < 10mm long).This willhelp eliminatereflectionsand ensure noiseiscoupledas common-mode. Infact,we have seen thatdifferentialsignalswhich are 1mm apartradiatefarlessnoisethan traces3mm apartsincemagneticfieldcancellationismuch betterwiththe closertraces.In addition,noise induced on the differentiallinesis much more likelyto appear as common-mode which is rejectedby the receiver.
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www.ti.com SNLS147F –JUNE 2002–REVISED APRIL 2013 Match electricallengthsbetween tracesto reduce skew. Skew between the signalsof a pairmeans a phase differencebetween signalswhichdestroysthemagneticfieldcancellationbenefitsofdifferentialsignalsand EMI willresult.Do not relysolelyon the auto-routefunctionfordifferentialtraces.Carefullyreviewdimensionsto match differentialimpedance and provideisolationforthe differentiallines.Minimizethe number of viasand otherdiscontinuitieson theline. Avoid90° turns(thesecause impedance discontinuities).Use arcsor45° bevels. Withina pairof traces,the distancebetween the two tracesshouldbe minimizedto maintaincommon-mode rejectionof the receivers.On the printedcircuitboard, thisdistanceshould remain constantto avoid discontinuitiesindifferentialimpedance.Minorviolationsatconnectionpointsareallowable. TERMINATION Use a terminationresistorwhichbestmatches thedifferentialimpedance oryourtransmissionline.The resistor should be between 90Ω and 130Ω forpoint-to-pointlinks.Multidrop(driverin the middle)or multipoint configurationsare typicallyterminatedat both ends. The terminationvaluemay be lowerthan 100Ω due to loadingeffectsand inthe50Ω to100Ω range.Remember thatthecurrentmode outputsneed thetermination resistortogeneratethedifferentialvoltage. Surface mount 1% - 2% resistorsare the best.PCB stubs,component lead,and the distancefrom the terminationtothereceiverinputsshouldbe minimized.The distancebetween theterminationresistorand the receivershouldbe < 10mm (12mm MAX). PROBING LVDS TRANSMISSION LINES Always use highimpedance (> 100kΩ),low capacitance(< 2 pF) scope probeswitha wide bandwidth(1 GHz) scope.Improperprobingwillgivedeceivingresults. Copyright© 2002–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS92001
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REVISION HISTORY
Changes from RevisionE (April2013)toRevisionF Page
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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS92001TLD/NOPB Active Production WSON (NGK) | 8 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 92001 DS92001TLD/NOPB.A Active Production WSON (NGK) | 8 1000 | SMALL T&R Yes SN Level-3-260C-168 HR -40 to 85 92001 DS92001TMA/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 92001 TMA DS92001TMA/NOPB.A Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 92001 TMA DS92001TMAX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 92001 TMA DS92001TMAX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 92001 TMA (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1
www.ti.com 23-May-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS92001TLD/NOPB WSON NGK 8 1000 367.0 367.0 35.0 DS92001TMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DS92001TMA/NOPB D SOIC 8 95 495 8 4064 3.05 DS92001TMA/NOPB.A D SOIC 8 95 495 8 4064 3.05 Pack Materials-Page 3
www.ti.com LDA08A (Rev C)
www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800
www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM
www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5
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