DS92001_06 NSC | Alldatasheet

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Technical content

Features

n Single +3.3 V Supply n B/LVDS receiver inputs accept LVPECL signals n TRI-STATE outputs n Loss of Signal (LOS) pin detects a non-driven bus n Receiver input threshold < ±100 mV n Fast propagation delay of 1.4 ns (typ) n Low jitter 400 Mbps fully differential data path n Compatible with BLVDS 10-bit SerDes (40MHz) n Compatible with ANSI/TIA/EIA-644-A LVDS standard n Available in SOIC and space saving LLP package n Industrial Temperature Range Connection and Block Diagrams SOIC - Top View 20024705 LLP - Top View 20024743 20024702 Functional Operation BLVDS Inputs BLVDS Outputs [IN+] − [IN−] OUT+ OUT− VID ≥ 0.1V H L VID ≤ −0.1V L H Full Fail-safe OPEN/SHORTor Terminated HL

Ordering Information

Order Number NS Pkg. No. Pkg. Type DS92001TMA M08A SOIC DS92001TLD LDA08A LLP September 2006 DS92001 3.3V B/LVDS-BLVDS Buffer © 2006 National Semiconductor Corporation DS200247 www.national.com

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V CC) −0.3V to +4V LVCMOS/LVTTL Input Voltage (EN) −0.3V to (V CC + 0.3V) LVCMOS/LVTTL Output Voltage (LOS) −0.3V to (V CC + 0.3V) B/LVDS Receiver Input Voltage (IN+, IN−) −0.3V to +4V BLVDS Driver Output Voltage (OUT+, OUT−) −0.3V to +4V BLVDS Output Short Circuit Current Continuous Junction Temperature +150˚C Storage Temperature Range −65˚C to +150˚C Lead Temperature Range Soldering (4 sec.) +260˚C Maximum Package Power Dissipation at 25˚C M Package 726 mW Derate M Package 5.8 mW/˚C above +25˚C Derate LDA Package 19.49 mW/˚C above +25˚C ESD Ratings (HBM, 1.5kΩ, 100pF) ≥2.5kV (EIAJ, 0Ω, 200pF) ≥250V Recommended Operating Conditions Min Typ Max Units Supply Voltage (VCC) 3.0 3.3 3.6 V Receiver Differential Input Voltage (VID) with VCM=1.2V 0.1 2.4 |V| Operating Free Air Temperature −40 +25 +85 ˚C B/LVDS Input Rise/Fall 20% to 80% 22 0n s

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3) Symbol Parameter Conditions Min Typ Max Units LVCMOS/LVTTL DC SPECIFICATIONS (EN) V IH High Level Input Voltage 2.0 V CC V VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current V IN =V CC or 2.0V +7 +20 µA IIL Low Level Input Current V IN = GND or 0.8V −10 ±1 +10 µA VCL Input Clamp Voltage I CL = −18 mA −0.6 −1.5 V LVCMOS/LVTTL DC SPECIFICATIONS (LOS) VOH Output High Voltage I OH = −4mA, V ID ≥ |200mV|, VCM = 1.2V V CC −0.4V

3.1 V CC V

(Note 5) IOL = 4mA, VID = 0V, VCM = 1.2V 0.15 0.4 V IOSHLOS Output Short Circuit Current (output high)(Note 4) VOUT = 0V, 200mV ≤ VID ≤ 2V, VCM = 1.5V −35 −60 mA BLVDS OUTPUT DC SPECIFICATIONS (OUT) |VOD| Differential Output Voltage (Note 2) RL =2 7Ω 250 350 500 mV RL =5 0Ω 350 450 600 mV ∆VOD Change in Magnitude of V OD for Complimentary Output States R L=2 7Ω or 50Ω Figure 1, Figure 2 20 mV VOS Offset Voltage R L =2 7Ω or RL =5 0Ω 1.1 1.25 1.375 V ∆VOS Change in Magnitude of V OS for Complimentary Output States Figure 1 22 0 m V IOZ Output TRI-STATE Current EN = 0V, V OUT =V CC or GND −20 ±5 +20 µA IOFF Power-Off Leakage Current V CC = 0V or Open Circuit, V OUT = 3.6V −20 ±5 +20 µA DS92001 www.national.com 2

Over recommended operating supply and temperature ranges unless otherwise specified. (Note 3) Symbol Parameter Conditions Min Typ Max Units LVDS OUTPUT AC SPECIFICATIONS (OUT) t HLT Fall Time (Notes 5, 10) 80% to 20% points 0.350 0.6 1.0 ns tPHZ Disable Time (Active High to Z) R L =5 0Ω,C L = 15pF 3 25 ns tPLZ Disable Time (Active Low to Z) Figure 6and Figure 7 32 5 n s tPZH Enable Time (Z to Active High) 100 120 ns tPZL Enable Time (Z to Active Low) 100 120 ns tDJ LVDS Data Jitter, Deterministic (Peak-to-Peak) (Note 9) VID = 300mV; PRBS = 2 23 − 1 data; V CM = 1.2V at 400Mbps (NRZ) 78 ps tRJ LVDS Clock Jitter, Random (Note 9) VID = 300mV; VCM = 1.2V at 200MHz clock 36 ps fMAX Maximum guaranteed frequency (Note 11) V ID = 200mV, VCM = 1.2V 200 300 MHz LVCMOS/LVTTL AC SPECIFICATIONS (LOS) tPHLLOS LVTTL Propagation Delay High to Low (Note 5) CL = 10pF, IN− = 1V, 1V ≤ IN+ ≤ 1.3V, Freq. = 10MHz, 50% Duty Cycle Figures 8, 9 10 15 20 ns t PLHLOS LVTTL Propagation Delay Low to High (Note 5) 2 5 10 ns tLHLOS Rise Time 20% to 80% (Note 5) 123 n s tHLLOS Fall Time 80% to 20% (Note 5) 1 1.3 3 ns Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VID,V OD,V TH, VTL, and ∆VOD.V OD has a value and direction. Positive direction means OUT+ is a more positive voltage than OUT−. Note 3: All typical are given for V CC = +3.3V and T A = +25˚C, unless otherwise stated. Note 4: Output short circuit current (I OS) is specified as magnitude only, minus sign indicates direction only. Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT (process, voltage and temperature) range. Note 6: tSKD1,| tPLHD −t PHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel (a measure of duty cycle). Note 7: tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5˚C of each other within the operating temperature range. This parameter guaranteed by design and characterization. Note 8: tSKD4, Part to Part Skew, is the differential channel-to- channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. t SKD4 is defined as |Max − Min| differential propagation delay. Note 9: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over the PVT range with the following test equipment setup: Agilent 86130A used as stimulus, 5 feet of RG142B cable with DUT test board and Agilent 86100A (digital scope mainframe) with Agilent 86122A (20GHz scope module). Data input jitter pk to pk = 22 picoseconds; Clock input jitter = 24 picoseconds; t DJ measured 100 picoseconds, t RJ measured 60 picoseconds. Note 10: Propagation delay, rise and fall times are guaranteed by design and characterization to 200MHz. Generator for these tests: 50MHz ≤ f ≤ 200MHz, Zo = 50Ω,t r ,t f≤ 0.5ns. Generator used was HP8130A (300MHz capability). Note 11: fMAX test: Generator (HP8133A or equivalent), Input duty cycle = 50%. Output criteria: VOD ≥ 200mV, Duty Cycle better than 45/55%. This specification is guaranteed by design and characterization. A minimum is specified, which means that the device will operate to specified conditions from DC to the m inimum guaranteed AC frequency. The typical value is always greater than the minimum guarantee. DS92001 www.national.com 4

LOS 4 O Loss of Signal output pin. LOS is asserted low while signal is invalid. See Applications Information section. VCC 5 P Power Supply, 3.3V ± 0.3V. outputs are in TRI-STATE. When EN is HIGH, the driver is enabled. FIGURE 9. LOS Output Waveforms for Propagation Delay, and Rise/Fall Times

Application Information (Continued) Avoid 90˚ turns (these cause impedance discontinuities). Use arcs or 45˚ bevels. Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allow- able. TERMINATION Use a termination resistor which best matches the differen- tial impedance or your transmission line. The resistor should be between 90Ω and 130Ω for point-to-point links. Multidrop (driver in the middle) or multipoint configurations are typically terminated at both ends. The termination value may be lower than 100Ω due to loading effects and in the 50 Ω to 100Ω range. Remember that the current mode outputs need the termination resistor to generate the differential voltage. Surface mount 1% - 2% resistors are the best. PCB stubs, component lead, and the distance from the termination to the receiver inputs should be minimized. The distance between the termination resistor and the receiver should be < 10mm (12mm MAX). PROBING LVDS TRANSMISSION LINES Always use high impedance ( > 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz) scope. Improper probing will give deceiving results. FAILSAFE FEATURE The BLVDS receiver is a high gain, high speed device that amplifies a small differential signal (30mV) to BLVDS ouput drive levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appear- ing as a valid signal. The receiver’s internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a high level output voltage ) for floating, termi- nated or shorted receiver inputs. 1. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a power-off condition, the BLVDS outputs will again be in a HIGH state, even with the end of cable 100 Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the re- ceiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable. 2. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differ- ential input voltage, the BLVDS outputs will remain in a HIGH state. Shorted input fail-safe voltage range is 0V to 2.4V. 3. External Biasing. External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the presence of higher noise levels. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distor- tion to the driver. The common-mode bias point should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. Please refer to application note AN-1194 “Failsafe Biasing of LVDS In- terfaces” for more information. DS92001 www.national.com 10

Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS92001TMA See NS Package Number M08A Order Number DS92001TLD See NS Package Number LDA08A DS92001 www.national.com11

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/quality/green. Lead free products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com DS92001 3.3V B/LVDS-BLVDS Buffer