DS91D180 TI | Alldatasheet

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CLK1A (8 KHz) CLK1B (8 KHz) CLK2A (19.44 MHz) CLK2B (19.44 MHz) CLK3A (User Defined up to 100 MHz) CLK3B (User Defined up to 100 MHz) 80W RT 80W RT 80W RT 80W RT 80W RT 80W RT 80W RT 80W RT 80W RT 80W RT 80W RT 80W RT ATCA Backplane Slot Card N Slot Card N+1 MLVDS Drivers/ReceiversMLVDS Drivers/Receivers DS91C180,DS91D180 www.ti.com SNLS158M –MARCH 2006–REVISED APRIL 2013 DS91D180/DS91C180100MHzM-LVDSLineDriver/ReceiverPair Check forSamples: DS91C180 ,DS91D180 1FEATURES DESCRIPTION The DS91D180 and DS91C180 are 100 MHz M- 2• DC to100+ MHz /200+ Mbps Low Power, Low LVDS (MultipointLow VoltageDifferentialSignaling)EMI Operation linedriver/receiverpairsdesigned for applications• OptimalforATCA, uTCA Clock Distribution thatutilizemultipointnetworks(e.g.clockdistribution Networks in ATCA and uTCA based systems).M-LVDS is a bus interfacestandard(TIA/EIA-899)optimizedfor• Meets or Exceeds TIA/EIA-899M-LVDS multidropnetworks.Controllededge rates,tightinputStandard receiverthresholdsand increaseddrivestrengthare• Wide InputCommon Mode Voltagefor sone of the key enhancments thatmake M-LVDSIncreasedNoise Immunity devicesan idealchoicefordistributingsignalsvia

  • DS91D180 has Type 1 ReceiverInput multipointnetworks.
  • DS91C180 has Type 2 ReceiverInputforFail- The DS91D180/DS91C180 driver input acceptsSafe Functionality LVTTL/LVCMOS signals and converts them to differentialM-LVDS signal levels. The• IndustrialTemperature Range DS91D180/DS91C180 receiveracceptslow voltage• Space Saving SOIC-14 Package (JEDEC MS- differentialsignals(LVDS, B-LVDS, M-LVDS, LV-012) PECL and CML) and convertsthem to3V LVCMOS signals.The DS91D180 devicehas a M-LVDS type1 receiverinputwithno offset.TheDS91C180 device has a type 2 receiverinputwhich enable failsafe functionality. TypicalApplicationinan ATCA Clock DistributionNetwork Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2006–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

2.4 V -2.4 V 50 mV -50 mV 150 mV Transition Region Type 1 Type 2 VID DS91C180,DS91D180 SNLS158M –MARCH 2006–REVISED APRIL 2013 www.ti.com Figure1. Connection Diagram Top View See Package Number D0014A Logic Diagram M-LVDS ReceiverTypes The EIA/TIA-899M-LVDS standardspecifiestwo differenttypesofreceiverinputstages.A type1 receiverhas a conventionalthresholdthatiscenteredatthemidpointoftheinputamplitude,VID/2.A type2 receiverhas a built inoffsetthatis100mV greaterthanVID/2.The type2 receiveroffsetactsas a failsafecircuitwhere open orshort circuitsattheinputwillalwaysresultintheoutputstagebeingdriventoa lowlogicstate. Figure2. M-LVDS ReceiverInputThresholds These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

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DS91C180,DS91D180 www.ti.com SNLS158M –MARCH 2006–REVISED APRIL 2013 AbsoluteMaximum Ratings (1)(2) SupplyVoltage,VCC −0.3Vto+4V ControlInputVoltages −0.3Vto(VCC + 0.3V) DriverInputVoltage −0.3Vto(VCC + 0.3V) DriverOutputVoltages −1.8Vto+4.1V ReceiverInputVoltages −1.8Vto+4.1V ReceiverOutputVoltage −0.3Vto(VCC + 0.3V) Maximum Package Power Dissipationat+25°C SOIC Package 1.1W DerateSOIC Package 8.8mW/ °C above +25°C ThermalResistance(4-Layer,2 oz.Cu, JEDEC) θJA 113.7°C/W θJC 36.9°C/W Maximum JunctionTemperature 150°C StorageTemperatureRange −65°C to+150°C Lead Temperature(Soldering,4 seconds) 260°C ESD Ratings: (HBM 1.5kΩ,100pF) ≥ 5 kV (EIAJ0Ω,200pF) ≥ 250 V (CDM 0Ω,0pF) ≥ 1000 V (1) “AbsoluteMaximum Ratings”arethosebeyond whichthesafetyofthedevicecannotbe ensured.They arenotmeant toimplythatthe deviceshouldbe operatedattheselimits.The tablesof“ElectricalCharacteristics”provideconditionsforactualdeviceoperation. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. Recommended OperatingConditions Min Typ Max Units SupplyVoltage,VCC 3.0 3.3 3.6 V VoltageatAny Bus Terminal(SeparateorCommon-Mode) −1.4 +3.8 V DifferentialInputVoltageVID 2.4 V HighLevelInputVoltageVIH 2.0 VCC V Low LevelInputVoltageVIL 0 0.8 V OperatingFreeAirTemperatureTA −40 +25 +85 °C ElectricalCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2)(3)(4) Symbol Parameter Conditions Min Typ Max Units M-LVDS Driver |VYZ | Differentialoutputvoltagemagnitude R L = 50Ω,C L = 5pF 480 650 mV Figure3 and Figure5ΔVYZ Change indifferentialoutputvoltagemagnitude −50 0 +50 mVbetween logicstates VOS(SS) Steady-statecommon-mode outputvoltage R L = 50Ω,C L = 5pF 0.3 1.8 2.1 V Figure3 and Figure4|ΔVOS(SS)| Change insteady-statecommon-mode outputvoltage 0 +50 mVbetween logicstates VOS(PP) Peak-to-peakcommon-mode outputvoltage (VOS(pp) @ 500KHz clock) 143 mV VY(OC) Maximum steady-stateopen-circuitoutputvoltage Figure6 0 2.4 V VZ(OC) Maximum steady-stateopen-circuitoutputvoltage 0 2.4 V VP(H) Voltageovershoot,low-to-highleveloutput R L = 50Ω,C L = 5pF, 1.2VSS V C D = 0.5pFVP(L) Voltageovershoot,high-to-lowleveloutput −0.2VSS VFigure8 and Figure9(5) IIH High-levelinputcurrent(LVTTL inputs) VIH = 2.0V -15 15 μA (1) Allcurrentsintodevicepinsarepositive;allcurrentsoutofdevicepinsarenegative.Allvoltagesarereferencedtodevicegroundunless otherwisespecified. (2) AlltypicalsaregivenforVCC = 3.3Vand TA = 25°C. (3) The algebraicconvention,inwhichtheleastpositive(mostnegative)limitisdesignatedas minimum, isused inthisdatasheet. (4) C L includesfixturecapacitanceand C D includesprobecapacitance. (5) Not productiontested.Ensuredby a statisticalanalysison a sample basisatthetimeofcharacterization. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS91C180 DS91D180

DS91C180,DS91D180 SNLS158M –MARCH 2006–REVISED APRIL 2013 www.ti.com ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2)(3)(4) Symbol Parameter Conditions Min Typ Max Units IIL Low-levelinputcurrent(LVTTL inputs) VIL= 0.8V -15 15 μA VIKL InputClamp Voltage(LVTTL inputs) IIN = -18mA -1.5 V IOS Differentialshort-circuitoutputcurrent Figure7 -43 43 mA M-LVDS Receiver VIT+ Positive-goingdifferentialinputvoltagethreshold See FunctionTables Type 1 20 50 mV Type 2 94 150 mV VIT− Negative-goingdifferentialinputvoltagethreshold See FunctionTables Type 1 −50 20 mV Type 2 50 94 mV VOH High-leveloutputvoltage IOH = −8mA 2.4 2.7 V VOL Low-leveloutputvoltage IOL = 8mA 0.28 0.4 V IOZ TRI-STATE outputcurrent VO = 0V or3.6V −10 10 μA IOSR ShortcircuitRrceiveroutputcurrent(LVTTL Output) VO = 0V -90 -48 mA M-LVDS Bus (Inputand Output)Pins IA,IY Receiverinputordriverhigh-impedanceoutput VA,Y = 3.8V,VB,Z = 1.2V, 32 µAcurrent DE = GND VA,Y = 0V or2.4V,VB,Z = 1.2V,DE −20 +20 µA= GND VA,Y = −1.4V,VB,Z = 1.2V, −32 µADE = GND IB,IZ Receiverinputordriverhigh-impedanceoutput VB,Z = 3.8V,VA,Y = 1.2V, 32 µAcurrent DE = GND VB,Z = 0V or2.4V,VA,Y = 1.2V,DE −20 +20 µA= GND VB,Z = −1.4V,VA,Y = 1.2V, −32 µADE = GND IAB ,IYZ Receiverinputordriverhigh-impedanceoutput VA,Y = VB,Z,−1.4V≤ V ≤ 3.8V,DE −4 +4 µAdifferentialcurrent(IA − IB orIY − IZ) = GND IA(OFF), Receiverinputordriverhigh-impedanceoutput VA,Y = 3.8V,VB,Z = 1.2V, IY(OFF) power-offcurrent DE = 0V 32 µA 0V ≤ VCC ≤ 1.5V VA,Y = 0V or2.4V,VB,Z = 1.2V, DE = 0V −20 +20 µA 0V ≤ VCC ≤ 1.5V VA,Y = −1.4V,VB,Z = 1.2V, DE = 0V −32 µA 0V ≤ VCC ≤ 1.5V IB(OFF), Receiverinputordriverhigh-impedanceoutput VB,Z = 3.8V,VA,Y = 1.2V, IZ(OFF) power-offcurrent DE = 0V 32 µA 0V ≤ VCC ≤ 1.5V VB,Z = 0V or2.4V,VA,Y = 1.2V, DE = 0V −20 +20 µA 0V ≤ VCC ≤ 1.5V VB,Z = −1.4V,VA,Y = 1.2V, DE = 0V −32 µA 0V ≤ VCC ≤ 1.5V IAB(OFF), Receiverinputordriverhigh-impedanceoutput VA,Y = VB,Z,−1.4V≤ V ≤ 3.8V, IYZ(OFF) power-offdifferentialcurrent DE = 0V −4 +4 µA (IA(OFF) − IB(OFF) orIY(OFF) − IZ(OFF)) 0V ≤ VCC ≤ 1.5V C A,C B Receiverinputcapacitance VCC = OPEN 5.1 pF C Y,C Z Driveroutputcapacitance 8.5 pF C AB Receiverinputdifferentialcapacitance 2.5 pF C YZ Driveroutputdifferentialcapacitance 5.5 pF

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DS91C180,DS91D180 www.ti.com SNLS158M –MARCH 2006–REVISED APRIL 2013 ElectricalCharacteristics(continued) Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2)(3)(4) Symbol Parameter Conditions Min Typ Max Units C A/B, Receiverinputordriveroutputcapacitancebalance 1.0C Y/Z (CA/CB orC Y/CZ) SUPPLY CURRENT (VCC ) ICCD DriverSupplyCurrent R L = 50Ω,DE = VCC ,RE = VCC 17 29.5 mA ICCZ TRI-STATE SupplyCurrent DE = GND, RE = VCC 7 9.0 mA ICCR ReceiverSupplyCurrent DE = GND, RE = GND 14 18.5 mA ICCB SupplyCurrent,Driverand ReceiverEnabled DE = VCC ,RE = GND 20 29.5 mA SwitchingCharacteristics Over recommended operatingsupplyand temperaturerangesunlessotherwisespecified.(1)(2) Symbol Parameter Conditions Min Typ Max Units DRIVER AC SPECIFICATION tPLH DifferentialPropagationDelayLow toHigh R L = 50Ω,C L = 5 pF, 1.0 3.4 5.5 ns tPHL DifferentialPropagationDelayHightoLow C D = 0.5pF 1.0 3.1 5.5 ns tSKD1 (tsk(p)) PulseSkew |tPLHD − tPHLD |(3)(4) Figure8 and Figure9 300 420 ps tSKD3 Part-to-PartSkew (5)(4) 1.9 ns tTLH (tr) RiseTime (4) 1.0 1.8 3.0 ns tTHL (tf) FallTime (4) 1.0 1.8 3.0 ns tPZH EnableTime (ZtoActiveHigh) R L = 50Ω,C L = 5 pF, 8 ns tPZL EnableTime (ZtoActiveLow ) C D = 0.5pF 8 ns tPLZ DisableTime (ActiveLow toZ) Figure10 and Figure11 8 ns tPHZ DisableTime (ActiveHightoZ) 8 ns tJIT Random Jitter,RJ (4) 100MHz clockpattern(6) 2.5 5.5 psrms fMAX Maximum Data Rate 200 Mbps RECEIVER AC SPECIFICATION tPLH PropagationDelayLow toHigh C L = 15 pF 2.0 4.7 7.5 ns tPHL PropagationDelayHightoLow Figure12 Figure13 and Figure14 2.0 5.3 7.5 ns tSKD1 (tsk(p)) PulseSkew |tPLHD − tPHLD |(3)(4) 0.6 1.9 ns tSKD3 Part-to-PartSkew (5)(4) 1.5 ns tTLH (tr) RiseTime(4) 0.5 1.2 3.0 ns tTHL (tf) FallTime(4) 0.5 1.2 3.0 ns tPZH EnableTime (ZtoActiveHigh) R L = 500Ω,C L = 15 pF 10 ns tPZL EnableTime (ZtoActiveLow) Figure15 and Figure16 10 ns tPLZ DisableTime (ActiveLow toZ) 10 ns tPHZ DisableTime (ActiveHightoZ) 10 ns fMAX Maximum Data Rate 200 Mbps (1) AlltypicalsaregivenforV = 3.3Vand TA = 25°C. (2) C L includesfixturecapacitanceand C D includesprobecapacitance. (3) tSKD1 ,|tPLHD − tPHLD |,isthemagnitudedifferenceindifferentialpropagationdelaytimebetween thepositivegoingedge and thenegative goingedge ofthesame channel. (4) Not productiontested.Ensuredby a statisticalanalysison a sample basisatthetimeofcharacterization. (5) tSKD3 ,Part-to-PartSkew, isdefinedas thedifferencebetween theminimum and maximum specifieddifferentialpropagationdelays.This specificationappliestodevicesatthesame VCC and within5°C ofeach otherwithintheoperatingtemperaturerange. (6) Stimulusand fixturejitterhas been subtracted. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS91C180 DS91D180

A B ~ 2.1V ~ 1.5V 'VOS(SS) VOS(PP)VOS DS91C180,DS91D180 SNLS158M –MARCH 2006–REVISED APRIL 2013 www.ti.com TestCircuitsand Waveforms Figure3. DifferentialDriverTestCircuit Figure4. DifferentialDriverWaveforms Figure5. DifferentialDriverFullLoad TestCircuit Figure6. DifferentialDriverDC Open TestCircuit

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DS91C180,DS91D180 www.ti.com SNLS158M –MARCH 2006–REVISED APRIL 2013 Figure7. DifferentialDriverShort-CircuitTestCircuit Figure8. DriverPropagationDelay and TransitionTime TestCircuit Figure9. DriverPropagationDelays and TransitionTime Waveforms Figure10. DriverTRI-STATE Delay TestCircuit Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS91C180 DS91D180

DS91C180,DS91D180 SNLS158M –MARCH 2006–REVISED APRIL 2013 www.ti.com Figure11. DriverTRI-STATE Delay Waveforms Figure12. ReceiverPropagationDelay and TransitionTime TestCircuit Figure13. Type 1 ReceiverPropagationDelay and TransitionTime Waveforms

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DS91C180,DS91D180 www.ti.com SNLS158M –MARCH 2006–REVISED APRIL 2013 Figure14. Type 2 ReceiverPropagationDelay and TransitionTime Waveforms Figure15. ReceiverTRI-STATE Delay TestCircuit Figure16. ReceiverTRI-STATE Delay Waveforms Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS91C180 DS91D180

DS91C180,DS91D180 SNLS158M –MARCH 2006–REVISED APRIL 2013 www.ti.com FUNCTION TABLES Table1.DS91D180/DS91C180 Transmitting(1) Inputs Outputs DE D Z Y 2.0V 2.0V L H 2.0V 0.8V H L 0.8V X Z Z (1) X — Don 'tcarecondition Z — Highimpedance state Table2.DS91D180 Receiving(1) Inputs Output RE A − B R 0.8V ≥ +0.05V H 0.8V ≤ −0.05V L 0.8V 0V X 2.0V X Z (1) X — Don 'tcarecondition Z — Highimpedance state Table3.DS91C180 Receiving(1) Inputs Output RE A − B R 0.8V ≥ +0.15V H 0.8V ≤ +0.05V L 0.8V 0V L 2.0V X Z (1) X — Don 'tcarecondition Z — Highimpedance state Table4.DS91D180 ReceiverInputThresholdTestVoltages(1) AppliedVoltages ResultingDifferentialInputVoltage ResultingCommon-Mode Input ReceiverOutput Voltage VIA VIB VID VIC R 2.400V 0.000V 2.400V 1.200V H 0.000V 2.400V −2.400V 1.200V L 3.800V 3.750V 0.050V 3.775V H 3.750V 3.800V −0.050V 3.775V L −1.400V −1.350V −0.050V −1.375V H −1.350V −1.400V 0.050V −1.375V L (1) H — HighLevel L — Low Level Outputstateassumes thatthereceiverisenabled(RE = L)

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DS91C180,DS91D180 www.ti.com SNLS158M –MARCH 2006–REVISED APRIL 2013 Table5.DS91C180 ReceiverInputThresholdTestVoltages(1) AppliedVoltages ResultingDifferentialInputVoltage ResultingCommon-Mode Input ReceiverOutput Voltage VIA VIB VID VIC R 2.400V 0.000V 2.400V 1.200V H 0.000V 2.400V −2.400V 1.200V L 3.800V 3.650V 0.150V 3.725V H 3.800V 3.750V 0.050V 3.775V L −1.250V −1.400V 0.150V −1.325V H −1.350V −1.400V 0.050V −1.375V L (1) H — HighLevel L — Low Level Outputstateassumes thatthereceiverisenabled(RE = L) PIN DESCRIPTIONS Pin No. Name Description 1,8 NC No connect.

2 R Receiveroutputpin

3 RE Receiverenablepin:When RE ishigh,thereceiverisdisabled.When RE isloworopen,the receiverisenabled. 4 DE Driverenablepin:When DE islow,thedriverisdisabled.When DE ishigh,thedriverisenabled.

5 D Driverinputpin

6,7 GND Ground pin

9 Y Non-invertingdriveroutputpin

10 Z Invertingdriveroutputpin

11 B Invertingreceiverinputpin

12 A Non-invertingreceiverinputpin

13,14 VCC Power supplypin,+3.3V ± 0.3V Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS91C180 DS91D180

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REVISION HISTORY

Changes from RevisionL (April2013)toRevisionM Page

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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS91C180TMA/NOPB Active Production SOIC (D) | 14 55 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 DS91C180 TMA DS91C180TMA/NOPB.A Active Production SOIC (D) | 14 55 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 DS91C180 TMA DS91C180TMAX/NOPB Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 DS91C180 TMA DS91C180TMAX/NOPB.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 DS91C180 TMA DS91D180TMA/NOPB Active Production SOIC (D) | 14 55 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 DS91D180 TMA DS91D180TMA/NOPB.A Active Production SOIC (D) | 14 55 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 DS91D180 TMA DS91D180TMAX/NOPB Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 DS91D180 TMA DS91D180TMAX/NOPB.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 DS91D180 TMA (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Addendum-Page 1

www.ti.com 23-May-2025 Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS91C180TMAX/NOPB SOIC D 14 2500 367.0 367.0 35.0 DS91D180TMAX/NOPB SOIC D 14 2500 356.0 356.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DS91C180TMA/NOPB D SOIC 14 55 495 8 4064 3.05 DS91C180TMA/NOPB.A D SOIC 14 55 495 8 4064 3.05 DS91D180TMA/NOPB D SOIC 14 55 495 8 4064 3.05 DS91D180TMA/NOPB.A D SOIC 14 55 495 8 4064 3.05 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

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