DS91C180

DS91D180 NSC | Alldatasheet

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Technical content

Features

n Meets TIA/EIA-899 M-LVDS Standard n Capable of driving 32 M-LVDS loads n Controlled edge rates tolerant to stubs n Wide Common Mode for Increased Noise Immunity n DS91D180 has type 1 receiver input n DS91C180 has type 2 Fail-safe support n Up to 200 Mbps operation n Industrial temperature range n Single 3.3 V Supply n 14L SOIC Package (JEDEC MS-012) Typical Application in AdvancedTCA Clock Distribution 20041930 June 2006 DS91D180/DS91C180 Multipoint LVDS (M-LVDS) Line Driver/Receiver © 2006 National Semiconductor Corporation DS200419 www.national.com

Order Number DS91D180TMA, DS91C180TMA See NS Package Number M14A Logic Diagram 20041925

Ordering Information

Order Number Receiver Input Function Package Type DS91D180TMA type 1 Data (0V threshold receiver) SOIC/M14A DS91C180TMA type 2 Control (offset fail-safe receiver) SOIC/M14A M-LVDS Receiver Types The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a conventional threshold that is centered at the midpoint of the input amplitude, V ID/2. A type 2 receiver has a built in offset that is 100mV greater then V ID/2. The type 2 receiver offset acts as a failsafe circuit where open or short circuits at the input will always result in the output stage being driven to a low logic state. 20041940 FIGURE 1. M-LVDS Receiver Input Thresholds

Electrical Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 2, 3, 4, 8) Symbol Parameter Conditions Min Typ Max Units M-LVDS Bus (Input and Output) Pins I A,I Y Receiver input or driver high-impedance output current VA,Y = 3.8V, VB,Z = 1.2V, DE = GND 32 µA VA,Y = 0V or 2.4V, V B,Z = 1.2V, DE = GND −20 +20 µA VA,Y = −1.4V, V B,Z = 1.2V, DE = GND −32 µA IB,I Z Receiver input or driver high-impedance output current VB,Z = 3.8V, VA,Y = 1.2V, DE = GND 32 µA VB,Z = 0V or 2.4V, V A,Y = 1.2V, DE = GND −20 +20 µA VB,Z = −1.4V, V A,Y = 1.2V, DE = GND −32 µA IAB,I YZ Receiver input or driver high-impedance output differential current (IA −I B or IY −I Z) VA,Y =V B,Z, −1.4V ≤ V ≤ 3.8V, DE = GND −4 +4 µA IA(OFF), IY(OFF) Receiver input or driver high-impedance output power-off current V A,Y = 3.8V, VB,Z = 1.2V, D E=V CC = 1.5V 32 µA VA,Y = 0V or 2.4V, V B,Z = 1.2V, D E=V CC = 1.5V −20 +20 µA VA,Y = −1.4V, V B,Z = 1.2V, D E=V CC = 1.5V −32 µA IB(OFF), IZ(OFF) Receiver input or driver high-impedance output power-off current V B,Z = 3.8V, VA,Y = 1.2V, D E=V CC = 1.5V 32 µA VB,Z = 0V or 2.4V, V A,Y = 1.2V, D E=V CC = 1.5V −20 +20 µA VB,Z = −1.4V, V A,Y = 1.2V, D E=V CC = 1.5V −32 µA IAB(OFF), IYZ(OFF) Receiver input or driver high-impedance output power-off differential current A(OFF) −I B(OFF) or IY(OFF) −I Z(OFF)) VA,Y =V B,Z, −1.4V ≤ V ≤ 3.8V, VCC = 1.5V, DE = 1.5V −4 +4 µA CA,C B Receiver input capacitance V CC = OPEN 5.1 pF CY,C Z Driver output capacitance 8.5 pF CAB Receiver input differential capacitance 2.5 pF CYZ Driver output differential capacitance 5.5 pF CA/B, CY/Z Receiver input or driver output capacitance balance (C A/CB or CY/CZ) 1.0 SUPPLY CURRENT (VCC) ICCD Driver Supply Current R L =5 0Ω,D E=V CC,R E=V CC 17 29.5 mA ICCZ TRI-STATE Supply Current DE = GND, RE = V CC 7 9.0 mA ICCR Receiver Supply Current DE = GND, RE = GND 14 18.5 mA ICCB Supply Current, Driver and Receiver Enabled DE = V CC,R E=G N D 20 29.5 mA DS91D180/DS91C180 www.national.com 4

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 3, 8) Symbol Parameter Conditions Min Typ Max Units DRIVER AC SPECIFICATION t PLH Differential Propagation Delay Low to High R L =5 0Ω,C L = 5 pF, 1.0 3.4 5.5 ns tPHL Differential Propagation Delay High to Low C D = 0.5 pF 1.0 3.1 5.5 ns tSKD1 (tsk(p)) Pulse Skew |t PLHD −t PHLD| (Notes 5, 9) Figure 7and Figure 8 300 420 ps tSKD3 Part-to-Part Skew (Notes 6, 9) 1.9 ns tTLH (tr) Rise Time (Note 9) 1.0 1.8 3.0 ns tTHL (tf) Fall Time (Note 9) 1.0 1.8 3.0 ns tPZH Enable Time (Z to Active High) R L =5 0Ω,C L = 5 pF, 8 ns tPZL Enable Time (Z to Active Low ) C D = 0.5 pF 8 ns tPLZ Disable Time (Active Low to Z) Figure 9and Figure 10 8n s tPHZ Disable Time (Active High to Z) 8 ns tJIT Random Jitter, RJ (Note 9) 100MHz clock pattern (Note 7) 2.5 5.5 psrms fMAX Maximum Data Rate 200 Mbps RECEIVER AC SPECIFICATION t PLH Propagation Delay Low to High C L = 15 pF 2.0 4.7 7.5 ns tPHL Propagation Delay High to Low Figures 11, 12and Figure 13 2.0 5.3 7.5 ns tSKD1 (tsk(p)) Pulse Skew |t PLHD −t PHLD| (Notes 5, 9) 0.6 1.9 ns tSKD3 Part-to-Part Skew (Notes 6, 9) 1.5 ns tTLH (tr) Rise Time (Note 9) 0.5 1.2 3.0 ns tTHL (tf) Fall Time (Note 9) 0.5 1.2 3.0 ns tPZH Enable Time (Z to Active High) R L = 500Ω,C L =1 5p F 1 0 n s tPZL Enable Time (Z to Active Low) Figure 14and Figure 15 10 ns tPLZ Disable Time (Active Low to Z) 10 ns tPHZ Disable Time (Active High to Z) 10 ns fMAX Maximum Data Rate 200 Mbps Note 1: “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. Note 3: All typicals are given for V CC = 3.3V and T A = 25˚C. Note 4: The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet. Note 5: tSKD1,| tPLHD −t PHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. Note 6: tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same V CC and within 5˚C of each other within the operating temperature range. Note 7: Stimulus and fixture jitter has been subtracted. Note 8: CL includes fixture capacitance and C D includes probe capacitance. Note 9: Not production tested. Guaranteed by a statistical analysis on a sample basis at the time of characterization. DS91D180/DS91C180 www.national.com5

FIGURE 15. Receiver TRI-STATE Delay Waveforms

DS91D180/DS91C180 Transmitting Inputs Outputs DE D Z Y 2.0V 2.0V L H 2.0V 0.8V H L 0.8V X Z Z X — Don’t care condition Z — High impedance state DS91D180 Receiving Inputs Output RE A−B R 0.8V ≥ +0.05V H 0.8V ≤ −0.05V L 0.8V 0V X 2.0V X Z X — Don’t care condition Z — High impedance state DS91C180 Receiving Inputs Output RE A−B R 0.8V ≥ +0.15V H 0.8V ≤ +0.05V L 0.8V 0V L 2.0V X Z X — Don’t care condition Z — High impedance state DS91D180 Receiver Input Threshold Test Voltages Applied Voltages Resulting Differential Input Voltage Resulting Common-Mode Input Voltage Receiver Output VIA VIB VID VIC R 2.400V 0.000V 2.400V 1.200V H 0.000V 2.400V −2.400V 1.200V L 3.800V 3.750V 0.050V 3.775V H 3.750V 3.800V −0.050V 3.775V L −1.400V −1.350V −0.050V −1.375V H −1.350V −1.400V 0.050V −1.375V L H — High Level L — Low Level Output state assumes that the receiver is enabled (RE = L) DS91C180 Receiver Input Threshold Test Voltages Applied Voltages Resulting Differential Input Voltage Resulting Common-Mode Input Voltage Receiver Output VIA VIB VID VIC R 2.400V 0.000V 2.400V 1.200V H 0.000V 2.400V −2.400V 1.200V L 3.800V 3.650V 0.150V 3.725V H 3.800V 3.750V 0.050V 3.775V L −1.250V −1.400V 0.150V −1.325V H −1.350V −1.400V 0.050V −1.375V L H — High Level L — Low Level Output state assumes that the receiver is enabled (RE = L) DS91D180/DS91C180 www.national.com11

Pin No. Name Description 1, 8 NC No connect.

2 R Receiver output pin

Receiver enable pin: When RE is high, the receiver is disabled. When RE is low or open, the receiver is enabled. 4 DE Driver enable pin: When DE is low, the driver is disabled. When DE is high, the driver is enabled.

5 D Driver input pin

6, 7 GND Ground pin

9 Y Non-inverting driver output pin

10 Z Inverting driver output pin

11 B Inverting receiver input pin

12 A Non-inverting receiver input pin

13, 14 V CC Power supply pin, +3.3V ± 0.3V

Application Information

Stub lengths should be kept to a minimum. The typical transition time of the DS91D180/DS91C180 driver output is For a general approximation, if the electrical length of a trace is greater than 1/5 of the transition edge, then the trace is considered a transmission line. For example, 2.25 ns/5 is 450ps. If the velocity equals 160 ps per inch for a typical loaded backplane, then the maximum stub length is 450 ps/160 ps/inch or 2.8 inches (approximately 3 inches). To determine the maximum stub for your backplane, the propa- gation velocity for the backplane is required (refer to appli- cation notes AN-905 and AN-808). DS91D180/DS91C180 www.national.com 12

Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS91D180TMA, DS91C180TMA See NS package Number M14A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at: www.national.com/quality/green. Lead free products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com DS91D180/DS91C180 Multipoint LVDS (M-LVDS) Line Driver/Receiver