DS90C031E-QML

DS90C031QML TI | Alldatasheet

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www.ti.com SNLS202B –MARCH 2006–REVISED MARCH 2013 DS90C031QMLLVDSQuadCMOS DifferentialLineDriver Check forSamples: DS90C031QML 1FEATURES DESCRIPTION The DS90C031 is a quad CMOS differentialline 2• Radiationguaranteed100 krad(Si) driverdesigned forapplicationsrequiringultralow• High impedance LVDS outputswithpower-off power dissipationand highdatarates.

• ±350 mV differentialsignaling The DS90C031 acceptsTTL/CMOS inputlevelsand• Low power dissipation translatesthem to low voltage(350 mV) differential
• Low differentialskew outputsignals.Inadditionthedriversupportsa TRI- STATE functionthatmay be used to disablethe• Low propagationdelay outputstage,thusdroppingthe deviceto a low idle• Pin compatiblewithDS26C31 power stateof11 mW typical.
• Compatible withIEEE 1596.3SCI LVDS In addition,the DS90C031 providespower-offhighstandard impedance LVDS outputs.This featureassures• Compatible withproposed TIA LVDS standard minimalloadingeffecton the LVDS bus lineswhen VCC isnot present.The DS90C031 and companion• Failsafelogicforfloatinginputs linereceiver(DS90C032) providea new alternativeto highpower psuedo-ECL devicesforhighspeed point- to-pointinterfaceapplications. Connection Diagram Figure1. Dual-In-Line See Package Number NAD0016A & NAC0016A Figure2. LCCC Package See Pacakage Number NAJ0020A Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2006–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS202B –MARCH 2006–REVISED MARCH 2013 www.ti.com FunctionalBlock Diagram TruthTable Enables Input Outputs EN EN* D I D O+ D O − L H X Z Z L L HAllothercombinationsof ENABLE inputs H H L

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www.ti.com SNLS202B –MARCH 2006–REVISED MARCH 2013 These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1) SupplyVoltage(VCC ) −0.3Vto+6V InputVoltage(DI) −0.3Vto(VCC + 0.3V) EnableInputVoltage(EN,EN*) −0.3Vto(VCC + 0.3V) OutputVoltage(DO+ ,D O −) −0.3Vto+ 5.8V StorageTemperatureRange −65°C ≤ TA ≤ +150°C Lead TemperatureRange, Soldering(4seconds) +260°C Maximum Package Power Dissipationat+25°C (2)

20 PinLCCC Package 1900 mW

16 PinCLGA (NAD) 1450 mW

16 PinCLGA (NAC) 1450 mW

θJA

20 PinLCCC Package 78°C/W

16 PinCLGA (NAD) 145°C/W

16 PinCLGA (NAC) 145°C/W

θJC

20 PinLCCC Package 18°C/W

16 PinCLGA (NAD) 14°C/W

16 PinCLGA (NAC) 14°C/W

ESD Rating(3) 3.5KV (1) AbsoluteMaximum Ratingsindicatelimitsbeyond whichdamage tothedevicemay occur.OperatingRatingsindicateconditionsfor whichthedeviceisfunctional,butdo notguaranteespecificperformancelimits.Forguaranteedspecificationsand testconditions,see theElectricalCharacteristics.The guaranteedspecificationsapplyonlyforthetestconditionslisted.Some performancecharacteristics may degradewhen thedeviceisnotoperatedunderthelistedtestconditions. (2) DerateLCCC at12.8mW/°C above +25°C. DerateCLGA at6.9mW/°C above +25°C. (3) Human body model,1.5kΩ inserieswith100 pF. Recommended OperatingConditions Min Typ Max Unit SupplyVoltage(VCC ) +4.5 +5.0 +5.5 V OperatingFreeAirTemperature(TA) −55 +25 +125 °C Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS90C031QML

SNLS202B –MARCH 2006–REVISED MARCH 2013 www.ti.com QualityConformance Inspection Table1.Mil-Std-883,Method 5005 -Group A Subgroup Description Temp (°C)

1 Statictestsat +25

2 Statictestsat +125

3 Statictestsat -55

4 Dynamic testsat +25

5 Dynamic testsat +125

6 Dynamic testsat -55

7 Functionaltestsat +25

9 Switchingtestsat +25

10 Switchingtestsat +125

11 Switchingtestsat -55

12 Settlingtimeat +25

13 Settlingtimeat +125

14 Settlingtimeat -55

DC Parameters (1) Sub-Symbol Parameter Conditions Notes Min Max Units groups VOD1 DifferentialOuput Voltage R L = 100Ω 250 450 mV 1,2,3 DV OD1 Change inMagnitudeofVod1 for R L = 100Ω 35 mV 1,2,3 complementaryoutputStates VOS OffsetVoltage R L = 100Ω 1.12 1.37 V 1,2,3 5 5 DV OS Change inMagnitudeofVos for R L = 100Ω 25 mV 1,2,3 ComplementaryOutputStates VOH OutputVoltageHigh R L = 100Ω 1.6 V 1,2,3 VOL OutputVoltageLow R L = 100Ω 0.9 V 1,2,3 VIH InputVoltageHigh (2) 2.0 VCC V 1,2,3 VIL InputVoltageLow (2) Gnd 0.8 V 1,2,3 II InputCurrent VI= VCC ,Gnd, 2.5,or0.4V ±10 µA 1,2,3 VCl InputClamp Voltage ICl = -18mA -1.5 V 1,2,3 IOS OutputShortCircuitCurrent VO = 0V -5.0 mA 1,2,3 IOff Power-offLeakage VO = 0V or2.4V, ±10 µA 1,2,3 VCC -=0V orOpen IOZ OutputTRI-STATE Current EN = 0.8Vand EN* = 2.0V ±10 µA 1,2,3 VO = 0V orVCC ICC DriversEnabledSupplyCurrent D I= HiorLow 25 mA 1,2,3 ICCZ DriversDisabledSupplyCurrent D I= HiorLow, En = Gnd, 10 mA 1,2,3 En* = VCC (1) Pre and PostirradiationlimitsareidenticaltothoselistedunderAC and DC electricalcharacteristicsexceptas listedinthe“Post RadiationLimits”table.Radiationend pointlimitsforthenotedparametersareguaranteedonlyfortheconditions,as specified. (2) TestedduringVOH /VOL tests.

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www.ti.com SNLS202B –MARCH 2006–REVISED MARCH 2013 AC Parameters The followingconditionsapply,unlessotherwisespecified. AC: VCC = 4.5V/5.0V/5.5V,R L = 100Ω (betweenoutputs),C L = 20pF (eachoutputtoGnd) Sub-Symbol Parameter Conditions Notes Min Max Units groups tPHLD DifferentialPropagationDelay 0.5 5.0 ns 9,10,11 HightoLow tPLHD DifferentialPropagationDelay 0.5 5.0 ns 9,10,11 Low toHigh tSkD DifferentialSkew |tPHLD-tPLHD| 3.0 ns 9,10,11 tSk1 ChanneltoChannelSkew (1) 3.0 ns 9,10,11 tSk2 ChiptoChipSkew (2) 4.5 ns 9,10,11 tPHZ DisableTime HightoZ (3) 20 ns 9,10,11 tPLZ DisableTime Low To Z (3) 20 ns 9,10,11 tPZH EnableTime Z toHigh (3) 20 ns 9,10,11 tPZL EnableTime Z toLow (3) 20 ns 9,10,11 (1) Channel-to-ChannelSkew isdefinedas thedifferencebetween thepropagationdelayofthechanneland theotherchannelsinthe same chipwithan eventon theinputs. (2) ChiptoChipSkew isdefinedas thedifferencebetween theminimum and maximum specifieddifferentialpropagationdelays. (3) Parameterguaranteed,nottested100% AC/DC Parameters -Post RadiationLimits(1) Sub-Symbol Parameter Conditions Notes Min Max Units groups ICC DriversEnabledSupplyCurrent D I-HiorLow, En = Gnd, 30 mA 1 En* = VCC ICCZ DriversDisabledSupplyCurrent D I-HiorLow, En = Gnd, 30 mA 1 En* = VCC (1) Pre and PostirradiationlimitsareidenticaltothoselistedunderAC and DC electricalcharacteristicsexceptas listedinthe“Post RadiationLimits”table.Radiationend pointlimitsforthenotedparametersareguaranteedonlyfortheconditions,as specified. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS90C031QML

SNLS202B –MARCH 2006–REVISED MARCH 2013 www.ti.com Parameter Measurement Information Figure3. DriverVOD and VOS TestCircuit Figure4. DriverPropagationDelay and TransitionTime TestCircuit Figure5. DriverPropagationDelay and TransitionTime Waveforms Figure6. DriverTRI-STATE Delay TestCircuit

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www.ti.com SNLS202B –MARCH 2006–REVISED MARCH 2013 Parameter Measurement Information(continued) Figure7. DriverTRI-STATE Delay Waveform Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS90C031QML

SNLS202B –MARCH 2006–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics Power Supply Currentvs Power Supply Voltage Power Supply Currentvs Temperature Figure8. Figure9. Power Supply Currentvs Power Supply Voltage Power Supply Currentvs Temperature Figure10. Figure11. Output TRI-STATE Currentvs Power Supply Voltage Output ShortCircuitCurrentvs Power Supply Voltage Figure12. Figure13.

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www.ti.com SNLS202B –MARCH 2006–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) DifferentialOutput Voltagevs Power Supply Voltage DifferentialOutput Voltagevs Ambient Temperature Figure14. Figure15. Output VoltageHigh vs Power Supply Voltage Output VoltageHigh vs Ambient Temperature Figure16. Figure17. Output VoltageLow vs Power Supply Voltage Output VoltageLow vs Ambient Temperature Figure18. Figure19. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS90C031QML

SNLS202B –MARCH 2006–REVISED MARCH 2013 www.ti.com TypicalPerformance Characteristics(continued) OffsetVoltagevs Power Supply Voltage OffsetVoltagevs Ambient Temperature Figure20. Figure21. Power Supply Currentvs Frequency Power Supply Currentvs Frequency Figure22. Figure23. DifferentialOutput Voltagevs Load Resistor DifferentialPropagationDelay vs Power Supply Voltage Figure24. Figure25.

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www.ti.com SNLS202B –MARCH 2006–REVISED MARCH 2013 TypicalPerformance Characteristics(continued) DifferentialPropagationDelay vs Ambient Temperature DifferentialSkew vs Power Supply Voltage Figure26. Figure27. DifferentialSkew vs Ambient Temperature DifferentialTransitionTime vs Power Supply Voltage Figure28. Figure29. DifferentialTransitionTime vs Ambient Temperature Figure30. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS90C031QML

SNLS202B –MARCH 2006–REVISED MARCH 2013 www.ti.com TYPICAL APPLICATION Figure31. Point-to-PointApplication APPLICATIONS INFORMATION LVDS driversand receiversareintendedtobe primarilyused inan uncomplicatedpoint-to-pointconfigurationas isshown inFigure31.Thisconfigurationprovidesa cleansignalingenvironmentforthequickedge ratesofthe drivers.The receiverisconnectedtothedriverthrougha balancedmedia whichmay be a standardtwistedpair cable,a parallelpaircable,or simplyPCB traces.Typically,thecharacteristicimpedance ofthemedia isinthe rangeof100Ω.A terminationresistorof100Ω shouldbe selectedtomatch themedia,and islocatedas closeto the receiverinputpinsas possible.The terminationresistorconvertsthe currentsourcedby the driverintoa voltagethatisdetectedby thereceiver.Otherconfigurationsarepossiblesuch as a multi-receiverconfiguration, but the effectsof a mid-streamconnector(s),cablestub(s),and otherimpedance discontinuitiesas wellas groundshifting,noisemarginlimits,and totalterminationloadingmust be takenintoaccount. The DS90C031differentiallinedriverisa balancedcurrentsource design.A currentmode driver,generally speakinghas a highoutputimpedance and suppliesa constantcurrentfora range of loads(a voltagemode driveron theotherhand suppliesa constantvoltagefora rangeofloads).Currentisswitchedthroughtheloadin one directionto produce a logicstateand inthe otherdirectionto produce the otherlogicstate.The typical outputcurrentismere 3.4mA, a minimum of2.5mA, and a maximum of4.5mA. The currentmode requires(as discussedabove)thata resistiveterminationbe employed toterminatethesignaland tocompletetheloopas shown inFigure31.AC orunterminatedconfigurationsarenotallowed.The 3.4mA loopcurrentwilldevelopa differentialvoltageof 340 mV acrossthe 100Ω terminationresistorwhich the receiverdetectswitha 240 mV minimum differentialnoisemargin neglectingresistivelinelosses(drivensignalminus receiverthreshold(340 mV – 100 mV = 240 mV)).The signaliscenteredaround +1.2V (DriverOffset,VOS ) withrespecttoground as shown inFigure32.Note thatthesteady-statevoltage(VSS )peak-to-peakswingistwicethedifferentialvoltage (VOD )and istypically680 mV. The currentmode driverprovidessubstantialbenefitsovervoltagemode drivers,such as an RS-422 driver.Its quiescentcurrentremainsrelativelyflatversusswitchingfrequency.Whereas theRS-422 voltagemode driver increasesexponentiallyinmost case between 20 MHz –50 MHz. Thisisdue to the overlapcurrentthatflows between therailsofthedevicewhen theinternalgatesswitch.Whereas thecurrentmode driverswitchesa fixed currentbetween itsoutputwithoutany substantialoverlapcurrent.This is similarto some ECL and PECL devices,but withoutthe heavy staticICC requirementsof the ECL/PECL designs.LVDS requires> 80% less currentthansimilarPECL devices.AC specificationsforthedriverarea tenfoldimprovementoverotherexisting RS-422 drivers. The TRI-STATE functionallowsthedriveroutputstobe disabled,thusobtainingan even lowerpower statewhen thetransmissionofdataisnotrequired.The LVDS outputsarehighimpedance underpower-offcondition.This allowsformultipleorredundantdriverstobe used incertainapplications. The footprintoftheDS90C031 isthesame as theindustrystandard26LS31 Quad Differential(RS-422)Driver.

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www.ti.com SNLS202B –MARCH 2006–REVISED MARCH 2013 Figure32. DriverOutput Levels Pin Descriptions Pin No. (SOIC) Name Description 1,7,9,15 D I Driverinputpin,TTL/CMOS compatible 2,6,10,14 D O+ Non-invertingdriveroutputpin,LVDS levels 3,5,11,13 D O − Invertingdriveroutputpin,LVDS levels

4 EN Activehighenablepin,OR-ed withEN*

12 EN* Activelowenablepin,OR-ed withEN

16 VCC Power supplypin,+5V ± 10%

8 Gnd Ground pin

Carefulconsiderationshould be given to environmentalconditionswhen using a productin a radiation environment. TotalIonizingDose Radiationhardness assured (RHA) productsare those partnumbers witha totalionizingdose (TID)level specifiedintheOrderingInformationtableon thefrontpage.Testingand qualificationoftheseproductsisdone on a wafer levelaccordingto MIL-STD-883G, Test Method 1019.7,ConditionA and the “Extended room temperatureanneal test” describedin section3.11 forapplicationenvironmentdose ratesless than 0.16 rad(Si)/s.Wafer levelTID dataisavailablewithlotshipments. SingleEvent Latch-Up One timesingleeventlatch-up(SEL)testingwas preformedshowingSEL immunityto103 MeV-cm 2/mg.A test reportisavailableupon request. SingleEvent Upset Singleeventupset(SEU) dataareavailableupon request. Copyright© 2006–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:DS90C031QML

SNLS202B –MARCH 2006–REVISED MARCH 2013 www.ti.com

REVISION HISTORY

Released Revision Section Changes 03/01/06 New New Release,Corporateformat 1 MDS datasheetconvertedintoCorp.datasheet format.MNDS90C031-X-RH Rev 2A1 willbe archived. 10/12/2010 A Features,OrderingTable,AbsoluteMaximum Added referencetoRadiationand Failsafe.Removed Ratings,ApplicationsInformation referencetoEOL NSID, OutputVoltagechanged limit from−0.3Vto(VCC + 0.3V)to−0.3Vto+5.8V,Added paragraphtoApplicationsInformationsectionand New RadiationEnvironmentsection.RevisionA will be Archived. 03/04/2013 B All Changed layoutofNationalData SheettoTIformat.

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www.ti.com 29-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) 5962-9583301Q2A Active Production LCCC (NAJ) | 20 50 | TUBE Yes Call TI Level-1-NA-UNLIM -55 to 125 DS90C031E -QML Q 5962-95833 01Q2A ACO 01Q2A >T 5962-9583301VFA Active Production CFP (NAD) | 16 19 | TUBE No Call TI Level-1-NA-UNLIM -55 to 125 DS90C031W- QMLV Q 5962-95833 01VFA ACO 01VFA >T 5962R9583301VFA Active Production CFP (NAD) | 16 19 | TUBE No Call TI Level-1-NA-UNLIM -55 to 125 DS90C031WR QMLV Q 5962R95833 01VFA ACO 01VFA >T 5962R9583301VZA Active Production CFP (NAC) | 16 88 | JEDEC TRAY (5+1) No Call TI Level-1-NA-UNLIM -55 to 125 DS90C031WGR QMLV Q 5962R95833 01VZA ACO 01VZA >T DS90C031 MDR Active Production DIESALE (Y) | 0 28 | OTHER Yes Call TI Level-1-NA-UNLIM -55 to 125 DS90C031-MDR.A Active Production DIESALE (Y) | 0 28 | OTHER Yes Call TI Level-1-NA-UNLIM -55 to 125 DS90C031E-QML Active Production LCCC (NAJ) | 20 50 | TUBE Yes Call TI Level-1-NA-UNLIM -55 to 125 DS90C031E -QML Q 5962-95833 01Q2A ACO 01Q2A >T DS90C031E-QML.A Active Production LCCC (NAJ) | 20 50 | TUBE Yes Call TI Level-1-NA-UNLIM -55 to 125 DS90C031E -QML Q 5962-95833 01Q2A ACO 01Q2A >T Addendum-Page 1

www.ti.com 29-May-2025 Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS90C031W-QMLV Active Production CFP (NAD) | 16 19 | TUBE No Call TI Level-1-NA-UNLIM -55 to 125 DS90C031W- QMLV Q 5962-95833 01VFA ACO 01VFA >T DS90C031W-QMLV.A Active Production CFP (NAD) | 16 19 | TUBE No Call TI Level-1-NA-UNLIM -55 to 125 DS90C031W- QMLV Q 5962-95833 01VFA ACO 01VFA >T DS90C031WGRQMLV Active Production CFP (NAC) | 16 88 | JEDEC TRAY (5+1) No Call TI Level-1-NA-UNLIM -55 to 125 DS90C031WGR QMLV Q 5962R95833 01VZA ACO 01VZA >T DS90C031WGRQMLV.A Active Production CFP (NAC) | 16 88 | JEDEC TRAY (5+1) No Call TI Level-1-NA-UNLIM -55 to 125 DS90C031WGR QMLV Q 5962R95833 01VZA ACO 01VZA >T DS90C031WRQMLV Active Production CFP (NAD) | 16 19 | TUBE No Call TI Level-1-NA-UNLIM -55 to 125 DS90C031WR QMLV Q 5962R95833 01VFA ACO 01VFA >T DS90C031WRQMLV.A Active Production CFP (NAD) | 16 19 | TUBE No Call TI Level-1-NA-UNLIM -55 to 125 DS90C031WR QMLV Q 5962R95833 01VFA ACO 01VFA >T (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. Addendum-Page 2

www.ti.com 29-May-2025 (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DS90C031QML, DS90C031QML-SP :

• Military : DS90C031QML
• Space : DS90C031QML-SP NOTE: Qualified Version Definitions:
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) 5962-9583301Q2A NAJ LCCC 20 50 470 11 3810 0 5962-9583301VFA NAD CFP 16 19 502 23 9398 9.78 5962R9583301VFA NAD CFP 16 19 502 23 9398 9.78 DS90C031E-QML NAJ LCCC 20 50 470 11 3810 0 DS90C031E-QML.A NAJ LCCC 20 50 470 11 3810 0 DS90C031W-QMLV NAD CFP 16 19 502 23 9398 9.78 DS90C031W-QMLV.A NAD CFP 16 19 502 23 9398 9.78 DS90C031WRQMLV NAD CFP 16 19 502 23 9398 9.78 DS90C031WRQMLV.A NAD CFP 16 19 502 23 9398 9.78 Pack Materials-Page 1

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www.ti.com PACKAGE OUTLINE 14X .050 .002 [1.27 0.0508] .250+.020 -.005 [6.35+0.508 -0.127 .410 .010 [10.414 0.254] .010 .002 [0.254 0.0508] .00 MIN TYP [0.0] 16X .017 .002 [0.4318 0.0508] R.015 .002 [0.381 0.0508] .040 .003 [1.016 0.0762]0 -4 .070+.010 -.020 [1.778+0.254 -0.508 .008 .004 TYP [0.2032 0.1016] .018 MAX TYP [0.46] .006 .002 TYP [0.1524 0.0508] .3870 .0030 [9.83 0.076] CFP - 2.33mm max height NAC0016A CERAMIC FLATPACK NOTES: 1. Controlling dimension is Inch. Values in [ ] are milimeters. Dimensions in ( ) for reference only. 2. For solder thickness and composition, see the "Lead Finish Composition/Thickness" link in the packaging section of the Texas Instruments website 3. Lead 1 identification shall be: a) A notch or other mark within this area b) A tab on lead 1, either side 4. No JEDEC registration as of December 2021 4215198/C 08/2022 8 9 NOTE 3 LEAD 1 ID SUPPLIER OPTION NOTE 3 .004 [0.1] SEE DETAIL A SEATING PLANE SCALE:12.000[ DETAIL A DETAIL A TYPICAL SCALE 1.500

www.ti.com EXAMPLE BOARD LAYOUT (14X .050 ) [1.27] R.002 TYP [0.05] .003 MIN [0.07] ALL AROUND .003 MAX [0.07] ALL AROUND (16X .090 ) [2.29] (16X .027 ) [0.69] (.37 ) [9.4] CFP - 2.33mm max height NAC0016A CERAMIC FLATPACK RECOMMENDED LAND PATTERN SYMM SYMM 4215198/C 08/2022 NON SOLDERMASK DEFINED METAL OPENING SOLDERMASK SOLDERMASK DEFINED SOLDERMASK OPENING SOLDER MASK METAL UNDER

A SIZESCALE PAGE 4 OF REVISIONS BY/APP'DDATEE.C.N.DESCRIPTIONREV TINA TRAN / ANIS FAUZI12/30/20212197879RELEASE TO DOCUMENT CONTROLA K. SINCERBOX02/15/20222198832NO CHANGE TO DRAWING; REVISION FOR YODA RELEASE;B 4215198 REV C

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