DS9096P

DS1972_V01 MAXIM | Alldatasheet

Document overview

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Technical content

Features

♦ 1024 Bits of EEPROM Memory Partitioned Into Four Pages of 256 Bits ♦ Individual Memory Pages Can Be Permanently Write Protected or Put in EPROM-Emulation Mode (“Write to 0”) ♦ Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise ♦ IEC 1000-4-2 Level 4 ESD Protection (±8kV Contact, ±15kV Air, Typical) ♦ Reads and Writes Over a Wide Voltage Range from 2.8V to 5.25V from -40°C to +85°C ♦ Communicates to Host with a Single Digital Signal at 15.4kbps or 125kbps Using 1-Wire Protocol Common iButton Features ♦ Unique Factory-Lasered 64-Bit Registration Number Ensures Error-Free Device Selection and Absolute Traceability Because No Two Parts are Alike ♦ Built-In Multidrop Controller for 1-Wire Net ♦ Chip-Based Data Carrier Stores Digital Identification and Information, Armored in a Durable Stainless-Steel Case ♦ Data Can Be Accessed While Affixed to Object ♦ Button Shape is Self-Aligning with Cup-Shaped Probes ♦ Easily Affixed with Self-Stick Adhesive Backing, Latched by its Flange, or Locked with a Ring Pressed Onto its Rim ♦ Presence Detector Acknowledges When Reader First Applies Voltage

Ordering Information

16.25mm 5.89mm 0.51mm 3.10mm 0.51mm 17.35mm BRANDING F5 SIZE GNDGND IOIO F3 SIZE 52 2D 0000006234FB 1-Wire® iBut t o n® . com YYWW ZZZ DS1972-F5 Pin Configurations +Denotes a lead(Pb)-free/RoHS-compliant package. PART TEMP RANGE PIN-PACKAGE DS1972-F5+ -40°C to +85°C F5 i Button DS1972-F3+ -40°C to +85°C F3 i Button Examples of Accessories PART ACCESSORY DS9096P Self-Stick Adhesive Pad DS9101 Multipurpose Clip DS9093RA Mounting Lock Ring DS9093A Snap-In Fob DS9092 i Button Probe 1-Wire and iButton are registered trademarks of Maxim Integrated Products, Inc.

ELECTRICAL CHARACTERISTICS

(TA = -40°C to +85°C, unless otherwise noted.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: GENERAL DATA 1-Wire Pullup Voltage V PUP (Note 2) 2.8 5.25 V 1-Wire Pullup Resistance R PUP (Notes 2, 3) 0.3 2.2 k Input Capacitance C IO (Notes 4, 5) 1000 pF Input Load Current I L IO pin at VPUP 0.05 6.7 μA High-to-Low Switching Threshold V TL (Notes 5, 6, 7) 0.5 VPUP - 1.8 V Input Low Voltage V IL (Notes 2, 8) 0.5 V Low-to-High Switching Threshold V TH (Notes 5, 6, 9) 1.0 VPUP - 1.0 V Switching Hysteresis V HY (Notes 5, 6, 10) 0.21 1.70 V Output Low Voltage V OL At 4mA (Note 11) 0.4 V Standard speed, RPUP = 2.2k 5 Overdrive speed, R PUP = 2.2k 2 Recovery Time (Notes 2, 12) tREC Overdrive speed, directly prior to reset pulse; R PUP = 2.2k 5 μs Standard speed 0.5 5.0 Rising-Edge Hold-Off Time (Notes 5, 13) tREH Overdrive speed Not applicable (0) μs Standard speed 65 Time Slot Duration (Notes 2, 14) tSLOT Overdrive speed 8 μs IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE Standard speed 480 640 Reset Low Time (Note 2) t RSTL Overdrive speed 48 80 μs Standard speed 15 60 Presence-Detect High Time t PDH Overdrive speed 2 6 μs Standard speed 60 240 Presence-Detect Low Time t PDL Overdrive speed 8 24 μs Standard speed 60 75 Presence-Detect Sample Time (Notes 2, 15) tMSP Overdrive speed 6 10 μs

ELECTRICAL CHARACTERISTICS (continued) (TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: 1-Wire WRITE Standard speed 60 120 Overdrive speed, VPUP > 4.5V 5 15.5 Write-Zero Low Time (Notes 2, 16, 17) tW0L Overdrive speed 6 15.5 μs Standard speed 1 15 Write-One Low Time (Notes 2, 17) tW1L Overdrive speed 1 2 μs IO PIN: 1-Wire READ Standard speed 5 15 - Read Low Time (Notes 2, 18) tRL Overdrive speed 1 2 - μs Standard speed t RL + 15 Read Sample Time (Notes 2, 18) tMSR Overdrive speed t RL + 2 μs EEPROM Programming Current I PROG (Notes 5, 19) 0.8 mA Programming Time t PROG (Note 20) 10 ms At +25°C 200k Write/Erase Cycles (Endurance) (Notes 21, 22) NCY At +85°C (worst case) 50k Data Retention (Notes 23, 24, 25) tDR At +85°C (worst case) 40 Years Note 1: Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and rel- evant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed. Note 2: System requirement. Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required. Note 4: Maximum value represents the internal parasite capacitance when VPUP is first applied. If a 2.2kΩ resistor is used to pull up the data line, 2.5µs after VPUP has been applied, the parasite capacitance does not affect normal communications. Note 5: Guaranteed by design, characterization, and/or simulation only. Not production tested. Note 6: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected. Note 8: The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic 0 level. Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected. Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0. Note 11: The I-V characteristic is linear for voltages less than 1V. Note 12: Applies to a single device attached to a 1-Wire line. Note 13: The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge. Note 14: Defines maximum possible bit rate. Equal to tW0LMIN + tRECMIN. Note 15: Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS1972 present. Minimum limit is tPDHMAX; maximum limit is tPDHMIN + tPDLMIN. Note 16: Numbers in bold are not in compliance with legacy 1-Wire product standards. See the Comparison Table. Note 17: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively. Note 18: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.

Note 19: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval should be such that the voltage at IO is greater than or equal to VPUPMIN. If VPUP in the system is close to VPUPMIN, a low- impedance bypass of RPUP, which can be activated during programming, may need to be added. Note 20: Interval begins tREHMAX after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by the device has returned from IPROG to IL. Note 21: Write-cycle endurance is degraded as TA increases. Note 22: Not 100% production tested; guaranteed by reliability monitor sampling. Note 23: Data retention is degraded as TA increases. Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the data sheet limit at operating temperature range is established by reliability testing. Note 25: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem- peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C. COMPARISON TABLE LEGACY VALUES DS1972 VALUES STANDARD SPEED (μs) OVERDRIVE SPEED (μs) STANDARD SPEED (μs) OVERDRIVE SPEED (μs) PARAMETER MIN MAX MIN MAX MIN MAX MIN MAX tSLOT (including tREC) 61 (undefined) 7 (undefined) 65* (undefined) 8* (undefined) tRSTL 480 (undefined) 48 80 480 640 48 80 tPDH 15 60 2 6 15 60 2 6 tPDL 60 240 8 24 60 240 8 24 tW0L 60 120 6 16 60 120 6 15.5 *Intentional change; longer recovery time requirement due to modified 1-Wire front-end. Note: Numbers in bold are not in compliance with legacy 1-Wire product standards.

pages of EEPROM, and a 64-bit register page.

4 PAGES OF

256 BITS EACH

64 BITS

Figure 1. Block Diagram Figure 2. Hierarchical Structure for 1-Wire Protocol

memory is unprotected and its contents are undefined. the product with which the DS1972 is associated. manufacturer ID. The last row is reserved for future use. device only supports full row (8-byte) copy operations. bytes must be written into the scratchpad. Figure 5. Memory Map address nor activate any function.

(i.e., refresh) are blocked.

1. The highest valued bit of the E/S register, called

scratchpad clears this flag. Figure 6. Address Registers

inverted CRC-16 of the command, address (actual address sent), and data at the end of the Write Scratchpad command sequence. Knowing this CRC value, the master can compare it to the value it has cal- culated to decide if the communication was successful and proceed to the Copy Scratchpad command. If the master could not receive the CRC-16, it should send the Read Scratchpad command to verify data integrity. As a preamble to the scratchpad data, the DS1972 repeats the target address TA1 and TA2 and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the scratchpad, or there was a loss of power since data was last written to the scratchpad. The master does not need to continue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag together with a cleared PF flag indicate that the device did not recog- nize the Write Scratchpad command. If everything went correctly, both flags are cleared. Now the master can continue reading and verifying every data byte. After the master has verified the data, it can send the Copy Scratchpad command, for exam- ple. This command must be followed exactly by the data of the three address registers: TA1, TA2, and E/S. The master should obtain the contents of these regis- ters by reading the scratchpad. Memory Function Commands The Memory Function Flowchart (Figure 7) describes the protocols necessary for accessing the memory of the DS1972. An example on how to use these functions to write to and read from the device is in the Memory Function Example section. The communication between the master and the DS1972 takes place either at standard speed (default, OD = 0) or at overdrive speed (OD = 1). If not explicitly set into overdrive mode, the DS1972 assumes standard speed. Write Scratchpad [0Fh] The Write Scratchpad command applies to the data memory and the writable addresses in the register page. For the scratchpad data to be valid for copying to the array, the user must perform a Write Scratchpad command of 8 bytes starting at a valid row boundary. The Write Scratchpad command accepts invalid addresses and partial rows, but subsequent Copy Scratchpad commands are blocked. After issuing the Write Scratchpad command, the mas- ter must first provide the 2-byte target address, fol- lowed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the byte off- set of T[2:0]. The E/S bits E[2:0] are loaded with the starting byte offset and increment with each subse- quent byte. Effectively, E[2:0] is the byte offset of the last full byte written to the scratchpad. Only full data bytes are accepted. When executing the Write Scratchpad command, the CRC generator inside the DS1972 (Figure 13) calcu- lates a CRC of the entire data stream, starting at the command code and ending at the last data byte as sent by the master. This CRC is generated using the CRC-16 polynomial by first clearing the CRC generator and then shifting in the command code (0Fh) of the Write Scratchpad command, the target addresses (TA1 and TA2), and all the data bytes. Note that the CRC-16 calculation is performed with the actual TA1 and TA2 and data sent by the master. The master can end the Write Scratchpad command at any time. However, if the end of the scratchpad is reached (E[2:0] = 111b), the master can send 16 read time slots and receive the CRC generated by the DS1972. If a Write Scratchpad command is attempted to a write- protected location, the scratchpad is loaded with the data already existing in memory rather than the data transmitted. Similarly, if the target address page is in EPROM mode, the scratchpad is loaded with the bit- wise logical AND of the transmitted data and data already existing in memory. Read Scratchpad [AAh] The Read Scratchpad command allows verifying the target address and the integrity of the scratchpad data. After issuing the command code, the master begins reading. The first 2 bytes are the target address. The next byte is the ending offset/data status byte (E/S) fol- lowed by the scratchpad data, which may be different from what the master originally sent. This is of particular importance if the target address is within the register page or a page in either write-protection mode or EPROM mode. See the Write Scratchpad [0Fh] section for details. The master should read through the scratch- pad (E[2:0] - T[2:0] + 1 bytes), after which it receives the inverted CRC based on data as it was sent by the DS1972. If the master continues reading after the CRC, all data is logic 1.

TO SCRATCHPAD APPLIES ONLY IF THE MEMORY AREA IS NOT PROTECTED. IF WRITE PROTECTED, THE DS1972 COPIES THE DATE BYTE FROM THE TARGET ADDRESS INTO THE SCRATCHPAD. IF IN EPROM MODE, THE DS1972 LOADS THE BITWISE LOGICAL AND OF THE TRANSMITTED BYTE AND THE DATA BYTE FROM THE TARGETED ADDRESS INTO THE SCRATCHPAD. BUS MASTER Rx "1"s DS1972 INCREMENTS E[2:0] PF = 0 DS1972 SETS PF = 1 CLEARS AA = 0 SETS E[2:0] = T[2:0] 0Fh WRITE SCRATCHPAD? N Y N Y N Y Y Y N N MASTER Tx RESET? E[2:0] = 7? T[2:0] = 0? MASTER Tx RESET? DS1972 SETS SCRATCHPAD BYTE COUNTER = T[2:0] AAh READ SCRATCHPAD? N Y DS1972 Tx CRC-16 OF COMMAND, ADDRESS, AND DATA BYTES AS THEY WERE SENT BY THE BUS MASTER BUS MASTER Rx "1"s Y N MASTER Tx RESET? BUS MASTER Rx CRC-16 OF COMMAND, ADDRESS, E/S BYTE, AND DATA BYTES AS SENT BY THE DS1972 Y N MASTER Tx RESET? Y BYTE COUNTER = E[2:0]? FROM ROM FUNCTIONS FLOWCHART (FIGURE 9) TO ROM FUNCTIONS FLOWCHART (FIGURE 9) DS1972 INCREMENTS BYTE COUNTER N TO FIGURE 7b FROM FIGURE 7b Figure 7a. Memory Function Flowchart

MEMORY LOCATIONS. DURATION: t PROG * * 1-Wire IDLE HIGH FOR POWER. DS1972 COPIES SCRATCHPAD DATA TO ADDRESS BUS MASTER Rx "1"s AA = 1 BUS MASTER Rx "1"s MASTER Tx RESET? N Y N N MASTER Tx RESET? Y MASTER Tx RESET? BUS MASTER Tx AND E/S BYTE 55h COPY SCRATCHPAD? N Y Y Y N DS1972 Tx "0" DS1972 Tx "1" F0h READ MEMORY? N Y Y N AUTH. CODE MATCH? Y N Y N N T[15:0] < 0090h? PF = 0? ADDRESS < 90h? Y COPY PROTECTED? BUS MASTER Rx "1"s MASTER Tx RESET?N Y DS1972 SETS MEMORY ADDRESS = (T[15:0]) BUS MASTER Rx DATA BYTE FROM MEMORY ADDRESS Y N N MASTER Tx RESET? ADDRESS < 8Fh? N Y MASTER Tx RESET? DS1972 INCREMENTS ADDRESS COUNTER Y TO FIGURE 7a FROM FIGURE 7a Figure 7b. Memory Function Flowchart (continued)

Copy Scratchpad [55h] The Copy Scratchpad command is used to copy data from the scratchpad to writable memory sections. After issuing the Copy Scratchpad command, the master must provide a 3-byte authorization pattern, which should have been obtained by an immediately preced- ing Read Scratchpad command. This 3-byte pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the target address is valid, the PF flag is not set, and the target memory is not copy protected, then the AA flag is set and the copy begins. All 8 bytes of scratchpad contents are copied to the target memo- ry location. The duration of the device’s internal data transfer is t PROG during which the voltage on the 1-Wire bus must not fall below 2.8V. A pattern of alternating 0s and 1s are transmitted after the data has been copied until the master issues a reset pulse. If the PF flag is set or the target memory is copy protected, the copy does not begin and the AA flag is not set. If the copy command was disturbed due to lack of power or for other reasons, the master will read a con- stant stream of FFh bytes until it sends a 1-Wire Reset Pulse. In this case, the destination memory may be incompletely programmed requiring a Write Scratchpad command and Copy Scratchpad command be repeat- ed to ensure proper programming of the EEPROM. This requires careful consideration when designing applica- tion software that writes to the DS1972 in an intermittent contact environment. Read Memory [F0h] The Read Memory command is the general function to read data from the DS1972. After issuing the com- mand, the master must provide the 2-byte target address. After these 2 bytes, the master reads data beginning from the target address and can continue until address 008Fh. If the master continues reading, the result is logic 1s. The device’s internal TA1, TA2, E/S, and scratchpad contents are not affected by a Read Memory command. 1-Wire Bus System The 1-Wire bus is a system that has a single bus mas- ter and one or more slaves. In all instances the DS1972 is a slave device. The bus master is typically a micro- controller. The discussion of this bus system is broken down into three topics: hardware configuration, trans- action sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transac- tions in terms of the bus state during specific time slots, which are initiated on the falling edge of sync pulses from the bus master. Hardware Configuration The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-drain or three-state outputs. The 1-Wire port of the DS1972 is open drain with an internal circuit equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The DS1972 supports both a standard and overdrive communication speed of 15.4kbps (max) and 125kbps (max), respectively. Note that legacy 1-Wire products support a standard communication speed of 16.3kbps and overdrive of 142kbps. The slightly reduced rates for the DS1972 are a result of additional recovery times, which in turn were driven by a 1-Wire physical interface enhancement to improve noise immunity. The value of the pullup resistor primari- ly depends on the network size and load conditions. The DS1972 requires a pullup resistor of 2.2kΩ (max) at any speed. The idle state for the 1-Wire bus is high. If for any rea- son a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16µs (overdrive speed) or more than 120µs (standard speed), one or more devices on the bus could be reset. Transaction Sequence The protocol for accessing the DS1972 through the 1-Wire port is as follows:

• Initialization
• ROM Function Command
• Memory Function Command
• Transaction/Data

48-bit serial number result in a mismatch of the CRC. single device or multiple devices on the bus. detailed discussion, including an example. pulldowns produce a wired-AND result). Figure 8. Hardware Configuration

(1 BYTE) DS1972 Tx SERIAL NUMBER (6 BYTES) RC = 0 MASTER Tx BIT 0 RC = 0 RC = 0 RC = 0 OD = 0 YY Y Y Y Y Y Y 33h READ ROM COMMAND? N 55h MATCH ROM COMMAND? BIT 0 MATCH? BIT 0 MATCH? N N N N N N N F0h SEARCH ROM COMMAND? OD RESET PULSE? N N CCh SKIP ROM COMMAND? N RC = 1 MASTER Tx BIT 1 MASTER Tx BIT 63 BIT 1 MATCH? BIT 63 MATCH? Y Y RC = 1 FROM MEMORY FUNCTIONS FLOWCHART (FIGURE 7) TO MEMORY FUNCTIONS FLOWCHART (FIGURE 7) DS1972 Tx BIT 0 DS1972 Tx BIT 0 MASTER Tx BIT 0 BIT 1 MATCH? BIT 63 MATCH? DS1972 Tx BIT 1 DS1972 Tx BIT 1 MASTER Tx BIT 1 DS1972 Tx BIT 63 DS1972 Tx BIT 63 MASTER Tx BIT 63 Y TO FIGURE 9b TO FIGURE 9b FROM FIGURE 9b FROM FIGURE 9b Figure 9a. ROM Functions Flowchart

RC = 0; OD = 1 RC = 0; OD = 1 N BIT 0 MATCH? YN RC = 1? Y A5h RESUME COMMAND? N Y 3Ch OVERDRIVE- SKIP ROM? N Y 69h OVERDRIVE- MATCH ROM? FROM FIGURE 9a FROM FIGURE 9a TO FIGURE 9a NOTE: THE OD FLAG REMAINS AT 1 IF THE DEVICE WAS ALREADY AT OVERDRIVE SPEED BEFORE THE OVERDRIVE-MATCH ROM COMMAND WAS ISSUED. TO FIGURE 9a N Y Y N MASTER Tx RESET? YMASTER Tx RESET? N BIT 1 MATCH? MASTER Tx BIT 0 MASTER Tx BIT 1 OD = 0 (SEE NOTE) (SEE NOTE) (SEE NOTE) N OD = 0 N OD = 0 Y RC = 1 BIT 63 MATCH? MASTER Tx BIT 63 Y Figure 9b. ROM Functions Flowchart (continued)

Resume [A5h] To maximize the data throughput in a multidrop envi- ronment, the Resume command is available. This com- mand checks the status of the RC bit and, if it is set, directly transfers control to the memory function com- mands, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive-Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume com- mand. Accessing another device on the bus clears the RC bit, preventing two or more devices from simultane- ously responding to the Resume command. Overdrive-Skip ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the memory func- tions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive-Skip ROM command sets the DS1972 into the overdrive mode (OD = 1). All communication following this command must occur at overdrive speed until a reset pulse of minimum 480µs duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus, this command sets all overdrive-supporting devices into overdrive mode. To subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed must be issued followed by a Match ROM or Search ROM com- mand sequence. This speeds up the time for the search process. If more than one slave supporting overdrive is present on the bus and the Overdrive-Skip ROM command is followed by a read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired- AND result). Overdrive-Match ROM [69h] The Overdrive-Match ROM command followed by a 64- bit ROM sequence transmitted at overdrive speed allows the bus master to address a specific DS1972 on a multidrop bus and to simultaneously set it in overdrive mode. Only the DS1972 that exactly matches the 64-bit ROM sequence responds to the subsequent memory function command. Slaves already in overdrive mode from a previous Overdrive-Skip ROM or successful Overdrive-Match ROM command remain in overdrive mode. All overdrive-capable slaves return to standard speed at the next reset pulse of minimum 480µs dura- tion. The Overdrive-Match ROM command can be used with a single device or multiple devices on the bus. 1-Wire Signaling The DS1972 requires strict protocols to ensure data integrity. The protocol consists of four types of signal- ing on one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. Except for the presence pulse, the bus master initiates all falling edges. The DS1972 can communicate at two different speeds: standard speed and overdrive speed. If not explicitly set into the overdrive mode, the DS1972 communicates at standard speed. While in overdrive mode, the fast timing applies to all waveforms. To get from idle to active, the voltage on the 1-Wire line needs to fall from V PUP below the threshold VTL. To get from active to idle, the voltage needs to rise from V ILMAX past the threshold VTH. The time it takes for the voltage to make this rise is seen in Figure 10 as ε, and its duration depends on the pullup resistor (R PUP) used and the capacitance of the 1-Wire network attached. The voltage V ILMAX is relevant for the DS1972 when determining a logical level, not triggering any events. Figure 10 shows the initialization sequence required to begin any communication with the DS1972. A reset pulse followed by a presence pulse indicates that the DS1972 is ready to receive data, given the correct ROM and memory function command. If the bus master uses slew-rate control on the falling edge, it must pull down the line for t RSTL + t F to compensate for the edge. A t RSTL duration of 480µs or longer exits the overdrive mode, returning the device to standard speed. If the DS1972 is in overdrive mode and t RSTL is no longer than 80µs, the device remains in overdrive mode. If the device is in overdrive mode and t RSTL is between 80µs and 480µs, the device resets, but the communication speed is undetermined. After the bus master has released the line it goes into receive mode. Now the 1-Wire bus is pulled to V PUP through the pullup resistor or, in the case of a DS2482- x00 or DS2480B driver, through the active circuitry. When the threshold V TH is crossed, the DS1972 waits for tPDH and then transmits a presence pulse by pulling the line low for t PDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at t MSP. The t RSTH window must be at least the sum of tPDHMAX , t PDLMAX , and t RECMIN . Immediately after tRSTH is expired, the DS1972 is ready for data commu- nication. In a mixed population network, t RSTH should be extended to minimum 480µs at standard speed and 48µs at overdrive speed to accommodate other 1-Wire devices.

trates the definitions of the write and read time slots. valid during a read time slot. REC before it is ready for the next time slot. A read-data time slot begins like a write-one time slot. modate the additional 1-Wire device input capacitance. x00 or DS2480B 1-Wire line drivers can be used. Figure 10. Initialization Procedure: Reset and Presence Pulse

Figure 11. Read/Write Timing Diagrams

which makes it less sensitive to noise. slave devices in three characteristics. at the factory and lasered into the ROM. transfer when writing to or reading from the scratchpad. or to reread the portion of the data with the CRC error. Figure 12. Noise Suppression Scheme

CRC values, refer to Application Note 27. Figure 13. CRC-16 Hardware Description and Polynomial RST 1-Wire reset pulse generated by master. PD 1-Wire presence pulse generated by slave. Select Command and data to satisfy the ROM function protocol. TA-E/S Target address TA1, TA2 with E/S byte. <8–T[2:0] bytes> Transfer of as many bytes as needed to reach the end of the scratchpad for a given target address. <Data to EOM> Transfer of as many data bytes as are needed to reach the end of the memory. CRC-16 Transfer of an inverted CRC-16. FF Loop Indefinite loop where the master reads FF bytes. AA Loop Indefinite loop where the master reads AA bytes. Programming Data transfer to EEPROM; no activity on the 1-Wire bus permitted during this time.

Command-Specific 1-Wire Communication Protocol—Color Codes 1-Wire Communication Examples Master to Slave Slave to Master Programming Write Scratchpad (Cannot Fail) RST PD Select WS TA <8–T[2:0] bytes> CRC-16 FF Loop Read Scratchpad (Cannot Fail) RST PD Select RS TA-E/S <8–T[2:0] bytes> CRC-16 FF Loop Copy Scratchpad (Success) RST PD Select CPS TA-E/S Programming AA Loop Copy Scratchpad (Invalid Address or PF = 1 or Copy Protected) RST PD Select CPS TA-E/S FF Loop Read Memory (Success) RST PD Select RM TA <Data to EOM> FF Loop Read Memory (Invalid Address) RST PD Select RM TA FF Loop

Write to the first 8 bytes of memory page 1. Read the entire memory. With only a single DS1972 connected to the bus mas- ter, the communication looks like this: MASTER MODE DATA (LSB FIRST) COMMENTS Tx (Reset) Reset pulse Rx (Presence) Presence pulse Tx CCh Issue “Skip ROM” command Tx 0Fh Issue “Write Scratchpad” command Tx 20h TA1, beginning offset = 20h Tx 00h TA2, address = 00 20h Tx <8 Data Bytes> Write 8 bytes of data to scratchpad Rx <2 Bytes CRC-16> Read CRC to check for data integrity Tx (Reset) Reset pulse Rx (Presence) Presence pulse Tx CCh Issue “Skip ROM” command Tx AAh Issue “Read Scratchpad” command Rx 20h Read TA1, beginning offset = 20h Rx 00h Read TA2, address = 00 20h Rx 07h Read E/S, ending offset = 111b, AA, PF = 0 Rx <8 Data Bytes> Read scratchpad data and verify Rx <2 Bytes CRC-16> Read CRC to check for data integrity Tx (Reset) Reset pulse Rx (Presence) Presence pulse Tx CCh Issue “Skip ROM” command Tx 55h Issue “Copy Scratchpad” command Tx 20h TA1 Tx 00h TA2 Tx 07h E/S (AUTHORIZATION CODE) — <1-Wire Idle High> Wait t PROGMAX for the copy function to complete Rx AAh Read copy status, AAh = success Tx (Reset) Reset pulse Rx (Presence) Presence pulse Tx CCh Issue “Skip ROM” command Tx F0h Issue “Read Memory” command Tx 00h TA1, beginning offset = 00h Tx 00h TA2, address = 00 00h Rx <144 Data Bytes> Read the entire memory Tx (Reset) Reset pulse Rx (Presence) Presence pulse PACKAGE TYPE PACKAGE CODE DOCUMENT NO. F3 iButton IB+3NT 21-0252 F5 iButton IB+5NT 21-0266

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to th e package regardless of RoHS status.

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 © 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

0 4/06 Initial release — 1 8/06 UL#913 bullet changed from “Meets UL#93 (4 th Edit.). . .(Application Pending)” to “Designed to meet UL#93 (4 th Edit.). . .” 1, 2 Deleted UL#913 bullet from the Common i Button Features section. 1 2 8/09 Changed the RoHS packages to lead(Pb)-free packages in the Ordering Information table. 1 Changed VTLMIN from 0.46V to 0.5V in the Electrical Characteristics table. 2 In the Absolute Maximum Ratings , changed storage temp to -55°C to +125°C; in the Electrical Characteristics table, changed V TH, VTL based on VPUP and data retention to 40 years min at 85°C; added note to retention spec: “EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.” 2, 3 In the Electrical Characteristics table, changed the V ILMAX spec from 0.3V to 0.5V; removed from the tW1LMAX spec; added Note 17 to t W0L spec; updated EC table Notes 17 and 18; corrected Note 20. 2, 3 Added to Figure 11 Write-Zero Time Slot. 18 Added Package Information table. 22 3 4/10 Created newer template-style data s heet. All 4 1/12 Updated Note 1 in the Electrical Characteristics section; specified the data memory default status and added a note that the memory must be programmed to FFh for the EPROM mode to function to the Memory Access section. 3, 7, 8