DS89C420_05 MAXIM | Alldatasheet
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Technical content
1 of 47 REV: 081805 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS89C420 offers the highest performance available in 8051-compatible microcontrollers. It features a redesigned processor core that executes every 8051 instruction (depending on the instruction type) up to 12 times faster than the original for the same crystal speed. Typical applications see a speed improvement of 10 times using the same code and crystal. The DS89C420 offers a maximum crystal speed of 33MHz, achieving execution rates up to 33 million instructions per second (MIPS). The DS89C430 ultra-high-speed flash microcontroller is an improved version of the DS89C420. The device offers more features, such as in-application programming, for approximately the same price. Engineers interested in the DS89C420 are encouraged to compare both devices when selecting an ultra-high-speed flash microcontroller.
APPLICATIONS
ORDERING INFORMATION
(MHz) PIN- PACKAGE DS89C420-MNG -40°C to +85°C 25 40 PDIP DS89C420-QNG -40°C to +85°C 25 44 PLCC DS89C420-ENG -40°C to +85°C 25 44 TQFP DS89C420-MCL 0°C to +70°C 33 40 PDIP DS89C420-QCL 0°C to +70°C 33 44 PLCC DS89C420-ECL 0°C to +70°C 33 44 TQFP DS89C420-MNL -40°C to +85°C 33 40 PDIP DS89C420-QNL -40°C to +85°C 33 44 PLCC DS89C420-ENL -40°C to +85°C 33 44 TQFP
FEATURES
/g167/g3280C52 Compatible
8051 Pin- and Instruction-Set Compatible
Four Bidirectional I/O Ports Three 16-Bit Timer Counters
256 Bytes Scratchpad RAM
/g167/g32On-Chip Memory 16kB Flash Memory In-System Programmable through Serial Port 1kB SRAM for MOVX /g167/g32ROMSIZE Feature Selects Internal Program Memory Size from 0 to 16k Allows Access to Entire External Memory Map Dynamically Adjustable by Software /g167/g32High-Speed Architecture
1 Clock-Per-Machine Cycle
Single-Cycle Instruction in 30ns Optional Variable Length MOVX to Access Fast/Slow Peripherals Dual Data Pointers with Auto Increment/Decrement and Toggle Select Supports Four Paged Modes /g167/g32Power Management Mode Programmable Clock Divider Automatic Hardware and Software Exit /g167/g32Two Full-Duplex Serial Ports /g167/g32Programmable Watchdog Timer /g167/g3213 Interrupt Sources (Six External) /g167/g32Five Levels of Interrupt Priority /g167/g32Power-Fail Reset /g167/g32Early Warning Power-Fail Interrupt The Ultra-High-Speed Flash Microcontroller Users Guide should be used in conjunction with this data sheet. Download it at www.maxim-ic.com/microcontrollers. Pin Configurations appear at end of data sheet. Data Logging Vending Security and Door Access Control Automotive Test Equipment Building Energy Control and Management Motor Control Gaming Equipment Uninterruptible Power Supplies Magstripe Reader/Scanner Programmable Logic Controllers Consumer Electronics Telephones Industrial Control and Automation Appliances (Washers, Microwaves, etc.) www.maxim-ic.com DS89C420 Ultra-High-Speed Microcontroller
DS89C420 Ultra-High-Speed Microcontroller 2 of 47 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground -0.3V to (V CC + 0.5V) Voltage Range on VCC Relative to Ground -0.3V to +6.0V Operating Temperature Range -40°C to +85°C Storage Temperature Range -55°C to +125°C Soldering Temperature See IPC/ JEDEC J-STD-020 Specification Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 4.5V to 5.5V; TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC (Notes 2, 13) 4.5 5.0 5.5 V Power-Fail Warning VPFW (Notes 2, 12) 4.2 4.375 4.6 V Reset Trip Point VRST (Notes 2, 12, 13) 3.95 4.125 4.35 V 33MHz 100 150 Supply Current Active Mode (Note 3) I CC 25MHz 75 125 mA 33MHz 40 50 Supply Current Idle Mode (Note 4) I IDLE 25MHz 40 50 mA Supply Current Stop Mode, Bandgap Disabled ISTOP (Note 5) 40 mA Supply Current Stop Mode, Bandgap Enabled ISPBG (Note 5) 40 mA Input Low Level V IL (Note 2) -0.3 +0.8 V Input High Level V IH (Note 2) 2.0 VCC + 0.3 V Input High Level XTAL and RST VIH2 (Note 2) 3.5 VCC + 0.3 V Output Low Voltage; Port 1 and 3 at IOL = 1.6mA VOL1 (Note 2) 0.15 0.45 V Output Low Voltage; Port 0 and 2, ALE, PSEN at IOL = 3.2mA VOL2 (Note 2) 0.15 0.45 V Output High Voltage; Port 1, 2, and 3, ALE, PSEN at IOH = -50/g109A VOH1 (Notes 2, 7) 2.4 V Output High Voltage; Port 1, 2, and 3 at IOH = -1.5mA VOH2 (Notes 2, 8) 2.4 V Output High Voltage; Port 0 and 2 in Bus Mode at IOH = -8mA VOH3 (Notes 2, 6) 2.4 V Output High Voltage, RST at IOL = - 0.4mA VOH4 (Notes 2, 14) 2.4 V Input Low Current; Port 1, 2, and 3 at 0.4V IIL -55 µA Transition Current from 1 to 0; Port 1, 2, and 3 at 2V ITL (Note 9) -650 µA Input Leakage Current, Port 0 in I/O Mode and EA IL (Note 11) -10 +10 µA Input Leakage Current, Port 0 in Bus Mode IL (Note 10) -300 +300 µA RST Pulldown Resistance R RST (Note 11) 50 170 k/g87
DS89C420 Ultra-High-Speed Microcontroller 3 of 47 Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: All voltages are referenced to ground. Note 3: Active current is measured with a 25MHz/33MHz clock source driving XTAL1, VCC = RST = 5.5V. All other pins disconnected. Note 4: Idle mode current measured with a 25MHz/33MHz clock source driving XTAL1, VCC = 5.5V, RST at ground. All other pins disconnected. Note 5: Stop mode measured with XTAL and RST grounded, VCC = 5.5V. All other pins disconnected. Note 6: When addressing external memory. Note 7: RST = 5.5V. This condition mimics the operation of pins in I/O mode. Note 8: During a 0-to-1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects a port pin in transition mode. Note 9: Ports 1, 2, and 3 source transition current when being pulled down externally. The current reaches its maximum at approximately 2V. Note 10: This port is a weak address holding latch in bus mode. Peak current occurs near the input transition point of the holding latc h at approximately 2V. Note 11: RST = 5.5V. Port 0 floating during reset and when in the logic-high state during I/O mode. Note 12: While the specifications for VPFW and VRST overlap, the design of the hardware makes it such that this is not possible. Within the ranges given, there is a guaranteed separation between these two voltages. Note 13: The user should note that this part is tested and guaranteed to operate down to 4.5V (10%) and that V RST (min) is specified below that point. This indicates that there is a range of voltages [V MIN to V RST (min)] where the processors operation is not guaranteed, but the reset trip point has not been reached. This should not be an issue in most applications, but should be considered when proper operation must be maintained at all times. For these applications, it may be desirable to use a more accurate external reset. Note 14: Guaranteed by design.
DS89C420 Ultra-High-Speed Microcontroller 4 of 47 AC CHARACTERISTICS (VCC = 4.5V to 5.5V; TA = -40°C to +85°C)* (Figure 1, Figure 2, and Figure 3)
1 CYCLE
2 CYCLE
4 CYCLE
PAGE MODE 1 PAGE MODE 2 NON-PAGE MODE PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS 0 25 0 25 0 25 0 25 0 25 External Oscillator (25MHz, 33MHz) 0 33 0 33 0 33 0 33 0 33 1 25 1 25 1 25 1 25 1 25 System Clock (Note 1) External Crystal (25MHz, 33MHz) 1 / tCLCL 1 33 1 33 1 33 1 33 1 33 MHz ALE Pulse Width (Note 2) t LHLL 0.5tCLCL - 2 + tSTC3 tCLCL - 2 + tSTC3 2tCLCL - 4 + tSTC3 1.5tCLCL - 5 + tSTC3 1.5tCLCL - 5 + tSTC3 ns Port 0 Instruction Address Valid to ALE Low tAVLL t CLCL - 2 0.5t CLCL - 2 ns Port 2 Instruction Address Valid to ALE Low tAVLL2 0.5t CLCL - 4 0.5t CLCL - 4 1.5t CLCL - 5 0.5t CLCL - 2 t CLCL - 2 ns Port 0 Data AddressValid to ALE Low tAVLL3 tCLCL - 2 + tSTC3 0.5tCLCL - 2 + tSTC3 ns Program Address Hold Address Hold After ALE Low MOVX Write tLLAX2 0.5tCLCL - 8 + tSTC4 1.5tCLCL - 8 + tSTC4 2.5tCLCL - 8 + tSTC4 0.5tCLCL - 8 + tSTC4 0.5tCLCL - 8 + tSTC4 ns Address Hold After ALE Low MOVX Read tLLAX3 0.5tCLCL - 8 + tSTC4 1.5tCLCL - 8 + tSTC4 2.5tCLCL - 8 + tSTC4 0.5tCLCL - 8 + tSTC4 0.5tCLCL - 8 + tSTC4 ns ALE Low to Valid Instruction In tLLIV 2.5tCLCL - 20 2.5tCLCL - 20 ns ALE Low to PSEN Low tLLPL 1.5t CLCL - 6 0.5t CLCL - 6 ns PSEN Pulse Width for Program Fetch tPLPH t CLCL - 5 t CLCL - 5 2t CLCL - 5 t CLCL - 5 2t CLCL - 5 ns
DS89C420 Ultra-High-Speed Microcontroller 5 of 47 PAGE MODE 1 PAGE MODE 2 NON-PAGE MODE PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS PSEN Low to Valid Instruction In tPLIV t CLCL - 18 t CLCL - 18 2t CLCL - 18 t CLCL - 18 2t CLCL - 18 ns Input Instruction Hold After PSEN tPXIX 0 0 0 0 0 ns Input Instruction Float After PSEN tPXIZ t CLCL - 5 t CLCL - 5 ns Port 0 Address to Valid Instruction In tAVIV0 1.5tCLCL - 20 3t CLCL - 20 ns Port 2 Address to Valid Instruction In tAVIV2 t CLCL - 18 1.5tCLCL - 18 2.5tCLCL - 18 3t CLCL - 20 3.5tCLCL - 20 ns PSEN Low to Port 0 Address Float tPLAZ 0 0 ns RD Pulse Width (P3.7) (Note 2) tRLRH tCLCL - 5 + tSTC1 tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 ns WR Pulse Width (P3.6) (Note 2) tWLWH tCLCL - 5 + tSTC1 tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 ns RD (P3.7) Low to Valid Data In (Note 2) tRLDV tCLCL - 15 + tSTC1 tCLCL - 15 + tSTC1 2tCLCL - 15 + tSTC1 2tCLCL - 15 + tSTC1 2tCLCL - 15 + tSTC1 ns Data Hold After RD (P3.7) tRHDX 0 0 0 0 0 ns Data Float After RD (P3.7) tRHDZ t CLCL - 5 t CLCL - 5 ns MOVX ALE Low to Input Data Valid (Note 2) tLLDV 2.5tCLCL - 20 + tSTC1 2.5tCLCL - 20 + tSTC1 ns Port 0 Address to Valid Data In (Note 2) tAVDV0 3tCLCL - 20 + tSTC1 3tCLCL - 20 + tSTC1 ns
DS89C420 Ultra-High-Speed Microcontroller 6 of 47 PAGE MODE 1 PAGE MODE 2 NON-PAGE MODE PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS Port 2 Address to Valid Data In (Note 2) tAVDV2 tCLCL - 16 + tSTC1 1.5tCLCL - 16 + tSTC1 3.5tCLCL - 16 + tSTC1 3.0tCLCL - 16 + tSTC1 3.5tCLCL - 20 + tSTC1 ns ALE Low to RD or WR Low (Note 2) tLLRL (tLLWL) 0.5tCLCL - 8 + tSTC2 0.5tCLCL + 1 + tSTC2 2tCLCL - 8 + tSTC2 2tCLCL + 8 + tSTC2 4tCLCL - 8 + tSTC2 4tCLCL + 8 + tSTC2 0.5tCLCL - 8 + tSTC2 0.5tCLCL + 4 + tSTC2 0.5tCLCL - 8 + tSTC2 0.5tCLCL + 4 + tSTC2 ns Port 0 Address Valid to RD or WR Low (Note 2) tAVRL0 (tAVWL0) 1.5tCLCL - 5 + tSTC2 tCLCL - 5 + tSTC2 ns Port 2 Address Valid to RD or WR Low (Note 2) tAVRL2 (tAVWL2) 0 + tSTC5 - 5 0.5tCLCL - 5 + tSTC5 1.5tCLCL - 5 + tSTC5 tCLCL - 5 + tSTC5 1.5tCLCL - 5 + tSTC5 ns Data Out Valid to WR Transition (Note 1) tQVWX -5 -5 -5 -5 -5 ns Data Hold After WR (Note 1) tWHQX 20 20 20 20 20 ns RD or WR High to ALE High (Note 1) tRHLH (tWHLH) tSTC2 - 2 tSTC2 + 6 tSTC2 - 2 tSTC2 + 6 tSTC2 - 2 tSTC2 + 6 tSTC2 - 2 tSTC2 + 6 tSTC2 - 2 tSTC2 + 6 ns *Specifications to -40°C are guaranteed by design and not production tested.
exceed the rated speed of the device. In addition, the use of the crystal multiplier feature establishes a minimum external speed. tSTC1, tSTC2, tSTC3 used in the variable timing table are calculated through the use of the table given below. capacitance is dependent on the frequency of the selected crystal. Figure 1. Non-Page Mode Timing
DS89C420 Ultra-High-Speed Microcontroller 9 of 47 EXTERNAL CLOCK CHARACTERISTICS (VCC = 4.5V to 5.5V; TA = -40°C to +85°C.)* PARAMETER SYMBOL MIN MAX UNITS Clock High Time t CHCX 10 ns Clock Low Time t CLCX 10 ns Clock Rise Time t CLCH 5 ns Clock Fall Time t CHCL 5 ns SERIAL PORT MODE 0 TIMING CHARACTERISTICS (VCC = 4.5V to 5.5V; TA = -40°C to +85°C.)* (Figure 4) 33MHz VARIABLE PARAMETER SYMBOL CONDITIONS MIN MAX MIN MAX UNITS SM2 = 0 360 12t CLCL Clock Cycle Time t XLXL SM2 = 1 120 4t CLCL ns SM2 = 0 200 10tCLCL -
100 Output Data Setup to
SM2 = 1 40 3tCLCL - ns SM2 = 0 50 2tCLCL -
10 Output Data Hold to Clock
SM2 = 1 20 tCLCL - 100 ns SM2 = 0 0 0 Input Data Hold after Clock Rising tXHDX SM2 = 1 0 0 ns SM2 = 0 200 10tCLCL -
100 Clock Rising Edge to Input
SM2 = 1 40 3tCLCL - ns Note: SM2 is the serial port 0, mode bit 2. When serial port 0 is operating in mode 0 (SM0 = SM1 = 0), SM2 determines the number of crystal clocks in a serial-port clock cycle. *Specifications to -40°C are guaranteed by design and not production tested.
Figure 4. Serial Port Timing
DS89C420 Ultra-High-Speed Microcontroller 11 of 47 POWER CYCLE TIMING CHARACTERISTICS (VCC = 4.5V to 5.5V; TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Crystal Startup Time t CSU (Note 2) 8 ms Power-On Reset Delay t POR (Note 3) 65,536 t CLCL Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: Startup time for a crystal varies with load capacitance and manufacturer. Time shown is for a 11.0592MHz crystal manufactured by Fox Electronics. Note 3: Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins when the level on the XTAL1 pin meets the VIH2 criteria. At 33MHz, this time is 1.99ms. FLASH MEMORY PROGRAMMING CHARACTERISTICS (VCC = 4.5V to 5.5V; TA = +21°C to +27°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Oscillator Frequency 1 / t CLCL 4 6 MHz Address Setup to PROG Low tAVGL 48tCLCL Address Hold After PROG tGHAX 48tCLCL Data Setup to PROG Low tDVGL 48tCLCL Data Hold After PROG tGHDX 48tCLCL PROG Pulse Width tGLGH 85 100 /g109s Address to Data Valid t AVQV 48t CLCL Enable Low to Data Valid t ELQV 48t CLCL Data Float After Enable t EHQZ 0 48t CLCL PROG High to PROG Low tGHGL 10 /g109s
DS89C420 Ultra-High-Speed Microcontroller 12 of 47 PIN DESCRIPTION PIN DIP PLCC TQFP NAME FUNCTION 40 12, 44 6, 38 V CC V CC - +5V 20 1, 22, 23, 34 16, 17, 28,
39 GND Logic Ground
External Reset. The RST input pin is bidirectional and contains a Schmitt trigger to recognize external active-high reset inputs. The pin also employs an internal pulldown resistor to allow for a combination of wire-ORed external reset sources. An RC is not required for power-up, since the device provides this function internally. 19 21 15 XTAL1 18 20 14 XTAL2 XTAL1, XTAL2. The crystal oscillator pins XTAL1 and XTAL2 provide support for fundamental mode parallel resonant, AT cut crystals. XTAL1 also acts as an input if there is an external clock source in place of a crystal. XTAL2 serves as the output of the crystal amplifier. 29 32 26 PSEN Program Store Enable. This signal is commonly connected to optional external program memory as a chip enable. PSEN provides an active-low pulse and is driven high when external program memory is not being accessed. In 1-cycle page mode 1, PSEN remains low for consecutive page hits. 30 33 27 ALE/PROG Address Latch Enable. Functions as a clock to latch the external address LSB from the multiplexed address/data bus on Port 0. This signal is commonly connected to the latch enable of an external 373 family transparent latch. In default mode, ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. In page mode, the ALE pulse width is altered according to the page mode selection. In traditional 8051 mode, ALE is high when using the EMI reduction mode and during a reset condition. ALE can be enabled by writing ALEON = 1 (PMR.2). Note that ALE operates independently of ALEON during external memory accesses. As an alternate mode, this pin (PROG) is used to execute the parallel program function. 39 43 37 P0.0 (AD0) 38 42 36 P0.1 (AD1) 37 41 35 P0.2 (AD2) 36 40 34 P0.3 (AD3) 35 39 33 P0.4 (AD4) 34 38 32 P0.5 (AD5) 33 37 31 P0.6 (AD6) 32 36 30 P0.7 (AD7) Port 0 (AD07), I/O. Port 0 is an open-drain 8-bit, bidirectional I/O port. As an alternate function, Port 0 can function as the multiplexed address/data bus to access off-chip memory. During the time when ALE is high, the LSB of a memory address is presented. When ALE falls to a logic 0, the port transitions to a bidirectional data bus. This bus is used to read external program memory and read/write external RAM or peripherals. When used as a memory bus, the port provides weak pullups for logic 1 outputs. The reset condition of Port 0 is three-state. Pullup resistors are required when using Port 0 as an I/O port. 18 29 4044, 1 Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port and an alternate functional interface for timer 2 I/O, new external interrupts, and new serial port 1. The reset condition of port 1 is with all bits at logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input state, since any external circuit that writes to the port overcomes the weak pullup. When software writes a 0 to any port pin, the DS89C420 activates a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes the output high (and input) state. The alternate functions of Port 1 are outlined below. PORT ALTERNATE FUNCTION 1 2 40 P1.0 T2 External I/O for Timer/Counter 2 2 3 41 P1.1 T2EX Timer 2 Capture/Reload Trigger 3 4 42 P1.2 RXD1 Serial Port 1 Receive 4 5 43 P1.3 TXD1 Serial Port 1 Transmit 5 6 44 P1.4 INT2 External Interrupt 2 (Positive Edge Detect) 6 7 1 P1.5 INT3 External Interrupt 3 (Negative Edge Detect) 7 8 2 P1.6 INT4 External Interrupt 4 (Positive Edge Detect) 8 9 3 P1.0P1.7 P1.7 INT5 External Interrupt 5 (Negative Edge Detect)
DS89C420 Ultra-High-Speed Microcontroller 13 of 47 PIN DESCRIPTION (continued) PIN DIP PLCC TQFP NAME FUNCTION 21 24 18 P2.0 (A8) 22 25 19 P2.1 (A9) 23 26 20 P2.2 (A10) 24 27 21 P2.3 (A11) 25 28 22 P2.4 (A12) 26 29 23 P2.5 (A13) 27 30 24 P2.6 (A14) 28 31 25 P2.7 (A15) Port 2 (A815), I/O. Port 2 is an 8-bit, bidirectional I/O port. The reset condition of port 2 is logic high. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port overcomes the weak pullup. When software writes a 0 to any port pin, the DS89C420 activates a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes both the output high and input state. As an alternate function, port 2 can function as the MSB of the external address bus when reading external program memory and read/write external RAM or peripherals. In page mode 1, port 2 provides both the MSB and LSB of the external address bus; in page mode 2, it provides the MSB and data. 1017 11, 1319 5, 713 P3.0P3.7 Port 3, I/O. Port 3 functions as both an 8-bit, bidirectional I/O port and an alternate functional interface for external interrupts, serial port 0, timer 0 and 1 inputs, and RD and WR strobes. The reset condition of port 3 is with all bits at logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port overcomes the weak pullup. When software writes a 0 to any port pin, the DS89C420 activates a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes both the output high and input state. The alternate modes of Port 3 are outlined below. PORT ALTERNATE FUNCTION 10 11 5 P3.0 P3.0 RXD0 Serial Port 0 Receive 11 13 7 P3.1 P3.1 TXD0 Serial Port 0 Transmit 12 14 8 P3.2 P3.2 INT0 External Interrupt 0 13 15 9 P3.3 P3.3 INT1 External Interrupt 1 14 16 10 P3.4 P3.4 T0 Timer 0 External Input 15 17 11 P3.5 P3.5 T1 Timer 1 External Input 16 18 12 P3.6 P3.6 WR External Data Memory Write Strobe 17 19 13 P3.7 P3.7 RD External Data Memory Read Strobe 31 35 29 EA External Access. Allows selection of internal or external program memory. Connect to ground to force the DS89C420 to use an external memory- program memory. The internal RAM is still accessible as determined by register settings. Connect to V CC to use internal flash memory.
Figure 5. Block Diagram also be loaded externally using standard commercially available programmers. flexibility in selecting external memory and peripherals. this mode to enable a normal speed response to interrupts. The EMI reduction feature disables the ALE signal when the processor is not accessing external memory.
DS89C420 Ultra-High-Speed Microcontroller 15 of 47 COMPATIBILITY The DS89C420 is a fully static CMOS 8051-compatible microcontroller similar to the DS87C520 in functional features, but with much higher performance. In most cases the DS89C420 can drop into an existing socket for the 8xC51 family to improve the operation significantly. While remaining familiar to 8051 family users, it has many new features. The DS89C420 runs the standard 8051 family instruction set and is pin compatible with DIP, PLCC, and TQFP packages. In general, software written for existing 8051-based systems works without DS89C420 modification, with the exception of critical timing routines, since the DS89C420 performs its instructions much faster than the original for any given crystal selection. The DS89C420 provides three 16-bit timer/counters, two full-duplex serial ports, and 256 bytes of direct RAM plus 1kB of extra MOVX RAM. I/O ports can operate as in standard 8051 products. Timers default to a 12 clock-per- cycle operation to keep their timing compatible with original 8051 family systems. However, timers are individually programmable to run at the new 1 clock-per-cycle if desired. The DS89C420 provides several new hardware features implemented by new SFRs. PERFORMANCE OVERVIEW The DS89C420 features a completely redesigned high-speed 8051-compatible core and allows operation at a higher clock frequency, but the updated core does not have the dummy memory cycles that are present in a standard 8051. A conventional 8051 generates machine cycles using the clock frequency divided by 12. In the DS89C420, the same machine cycle takes 1 clock. Thus, the fastest instructions execute 12 times faster for the same crystal frequency (and actually 24 times faster for the INC data pointer instruction). It should be noted that this speed improvement reduces when using external memory access modes that require more than 1 clock per cycle. Improvement of individual programs depends on the actual instructions used. Speed-sensitive applications make the most use of instructions that are 12 times faster. However, the sheer number of 12-to-1 improved op codes makes dramatic speed improvements likely for any code. These architecture improvements produce instruction cycle times as low as 30ns (33MIPs). The dual data pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory. The new page modes allow for increased efficiency in external memory accesses. INSTRUCTION SET SUMMARY All instructions perform the same functions as their 8051 counterparts. Their effect on bits, flags, and other status functions is also identical. However, the timing of each instruction is different in both absolute and relative number of clocks. For absolute timing of real-time events, the timing of software loops can be calculated using information in the Instruction Set table of the Ultra-High-Speed Flash Microcontroller Users Guide. However, counter/timers default to run at the older 12 clocks per increment. In this way, timer-based events occur at the standard intervals with software executing at higher speed. Timers optionally can run at lower numbers of clocks per increment to take advantage of faster processor operation. The relative time of some instructions might be different in the new architecture than it was previously. For example, in the original architecture, the MOVX A, @DPTR instruction and the MOV direct, direct instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of time. In the DS89C420, the MOVX instruction takes as little as two machine cycles or two oscillator cycles but the MOV direct, direct uses three machine cycles or three oscillator cycles. While both are faster than their original counterparts, they now have different execution times. This is because the DS89C420 usually uses one machine cycle for each instruction byte and requires one cycle for execution. The user concerned with precise program timing should examine the timing of each instruction to become familiar with the changes. SPECIAL FUNCTION REGISTERS (SFRS) All peripherals and operations that are not explicit instructions in the DS89C420 are controlled through SFRs. The most common features basic to the architecture are mapped to the SFRs. These include the CPU registers (ACC, B, and PSW), data pointers (DPTRs), stack pointer, I/O ports, timer/counters, and serial ports. In many cases, an SFR controls an individual function or reports the functions status. The SFRs reside in register locations 80hFFh and are only accessible by direct addressing. SFRs whose addresses end in 0h or 8h are bit-addressable.
DS89C420 Ultra-High-Speed Microcontroller 16 of 47 All standard SFR locations from the 8051 are duplicated in the DS89C420 and several SFRs have been added for the unique features of the DS89C420. Most of these features are controlled by bits in SFRs located in unused locations in the 8051 SFR map. This allows for increased functionality while maintaining complete instruction set compatibility. Table 1 summarizes the SFRs and their locations. Table 2 specifies the default reset condition for all SFR bits. DATA POINTERS The data pointers (DPTR and DPTR1) are used to assign a memory address for the MOVX instructions. This address can point to a MOVX RAM location (on-chip or off-chip), or a memory-mapped peripheral. Two pointers are useful when moving data from one memory area to another, or when using a memory-mapped peripheral for both source and destination addresses. The user selects the active pointer through a dedicated SFR bit (Sel = DPS.0), or activates an automatic toggling feature for altering the pointer selection (TSL = DPS.5). An additional feature, if selected, provides automatic incrementing or decrementing of the current DPTR. STACK POINTER The stack pointer denotes the register location at the top of the stack, which is the last used value. The user can place the stack anywhere in the scratchpad RAM by setting the stack pointer to the desired location, although the lower bytes are normally used for working registers. I/O PORTS The DS89C420 offers four 8-bit I/O ports. Each I/O port is represented by an SFR location, and can be written or read. The I/O port has a latch that contains the value written by software. COUNTER/TIMERS Three 16-bit timer/counters are available in the DS89C420. Each timer is contained in two SFR locations that can be read or written by software. The timers are controlled by other SFRs described in the SFR Bit Description section of the Ultra-High-Speed Flash Microcontroller Users Guide. SERIAL PORTS The DS89C420 provides two UARTs that are controlled and accessed by SFRs. Each UART has an address that is used to read and write the UART. The same address is used for read and write operations, which are distinguished by the instruction. Its own SFR control register controls each UART.
Table 1. Special Function Registers
Table 2. SFR Reset Value
DS89C420 Ultra-High-Speed Microcontroller 19 of 47 external MOVX data memory access. The lower 128 bytes of on-chip flash memory store reset and interrupt vectors. The program memory ROMSIZE feature allows software to dynamically configure the maximum address of on-chip program memory. This allows the DS89C420 to act as a bootloader for an external flash or NV SRAM. It also enables the use of the overlapping external program spaces. 256 bytes of on-chip RAM serve as a register area and program stack, which are separated from the data memory. REGISTER SPACE Registers are located in the 256 bytes of on-chip RAM, which can be divided into two subareas of 128 bytes each as illustrated in Figure 6. Separate classes of instructions are used to access the registers and the program/data memory. The upper 128 bytes are overlapped with the 128 bytes of SFRs in the memory map. Indirect addressing accesses the upper 128 bytes of scratchpad RAM, and direct addressing accesses the SFR area. Direct or indirect addressing can access the lower 128 bytes. There are four banks of eight individual working registers in the lower 128 bytes of scratchpad RAM. The working registers are general-purpose RAM locations that can be addressed within the selected bank by any instructions that use R0R7. The register bank selection is controlled through the program status register in the SFR area. The contents of the working registers can be used for indirectly addressing the upper 128 bytes of scratchpad RAM. To support the Boolean operations, there are individually addressable bits in both the RAM and SFR areas. In the scratchpad RAM area, registers 20h2Fh are bit-addressable by software using Boolean operation instructions. Another use of the scratchpad RAM area is for the stack. The stack pointer in the SFRs is used to select storage locations for program variables and for return addresses of control operations. MEMORY CONFIGURATION As illustrated in Figure 6, the DS89C420 incorporates two 8kB flash memories for on-chip program memory and 1kB of SRAM for on-chip data memory or a particular range (4007FF) of alternate program memory space. The DS89C420 uses an address scheme that separates program memory from data memory, such that the 16-bit address bus can address each memory area up to 64kB. PROGRAM MEMORY ACCESS On-chip program memory begins at address 0000h and is contiguous through 3FFFh (16kB). Exceeding the maximum address of on-chip program memory causes the device to access off-chip memory. However, the maximum on-chip decoded address is selectable by software using the ROMSIZE feature. Software can cause the DS89C420 to behave like a device with less on-chip memory. This is beneficial when overlapping external memory is used. The maximum memory size is dynamically variable. Thus, a portion of memory can be removed from the memory map to access off-chip memory, then be restored to access on-chip memory. In fact, all of the on-chip memory can be removed from the memory map allowing the full 64kB memory space to be addressed from off-chip memory. Program memory addresses that are larger than the selected maximum are automatically fetched from outside the part through ports 0 and 2 (Figure 6 The ROMSIZE register is used to select the maximum on-chip decoded address for program memory. Bits RMS2, RMS1, RMS0 have the following effect: RMS2 RMS1 RMS0 ADDRESS MAXIMUM ON-CHIP PROGRAM MEMORY 0 0 0 0k 0 0 1 1k/03FFh 0 1 0 2k/07FFh 0 1 1 4k/0FFFh 1 0 0 8k/1FFFh 1 0 1 16k (default)/3FFFh 1 1 0 InvalidReserved 1 1 1 InvalidReserved
Figure 6. Memory Map
128 Bytes
128 Bytes SFR
software must alter bits RMS2RMS0. Altering these bits requires a timed access procedure as explained later. external program execution because program code from 4kB to 16kB (1000h3FFFh) is no longer located on-chip.
DS89C420 Ultra-High-Speed Microcontroller 21 of 47 4kB (1000h) boundary or above the 16kB (3FFFh) boundary so that it is unaffected by the memory modification. The same precaution should be applied if the internal program memory size is modified while executing from external program memory. For non-page mode operations, off-chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2. While serving as a memory bus, these pins are not I/O ports. This convention follows the standard 8051 method of expanding on-chip memory. Off-chip program memory access also occurs if the EA pin is logic 0. EA overrides all bit settings. The PSEN signal goes active (low) to serve as a chip enable or output enable when port 0 and port 2 fetch from external program memory. The RD and WR signals are used to control the external data memory device. Data memory is accessed by MOVX instructions. The MOVX@Ri instruction uses the value in the designated working register to provide the LSB of the address, while port 2 supplies the address MSB. The MOVX@DPTR instruction uses one of the two data pointers to move data over the entire 64kB external data memory space. Software selects the data pointer to be used by writing to the SEL bit (DPS.0). The DS89C420 also provides a user option for high-speed external memory access by reconfiguring the external memory interface into page mode operation. Note: When using the original 8051 expanded bus structure, the throughput is reduced by 75% compared with that of internal operations. This is due to the CPU being stalled for three out of four clocks waiting for the data fetch, which takes four clocks. Page Mode 1 is the only external addressing mode where the CPU does not require stalls for external memory access, but page misses result in reduced external access performance. ON-CHIP PROGRAM MEMORY The processor can fetch the full on-chip program memory range automatically. The reset routines and all interrupt vectors are located in the lower 128 bytes of the on-chip program memory area. On-chip program memory is logically divided into two 8kB flash memory banks and is designed to be programmed with the standard 5V V CC supply by using a built-in program memory loader. It can also be programmed in standard flash or EPROM programmers. The DS89C420 incorporates a memory management unit (MMU) and other hardware to support any of the two programming methods. The MMU controls program and data memory access, and provides sequencing and timing controls for programming the on-chip program memory. There is also a separate security flash block that is used to support a standard three-level lock, a 64-byte encryption array, and other flash options. SECURITY FEATURES The DS89C420 incorporates a 64-byte encryption array, allowing the user to verify program codes while viewing the data in encrypted form. The encryption array is implemented in a security flash memory block that has the same electrical and timing characteristics as the on-chip program memory. Once the encryption array is programmed to non-FFh, the data presented in the verify mode is encrypted. Each byte of data is XNORed with a byte in the encryption array during verification. A three-level lock restricts viewing of the internal program and data memory contents. By programming the three lock bits, the user can select a level of security as specified in Table 3 . Once a security level is selected and programmed, the setting of the lock bits remains. Only a mass erase can erase these bits to allow reprogramming the security level to a less restricted protection.
Table 3. Flash Memory Lock Bits 1 1 1 1 No program lock. Encrypted verify if encryption array is programmed. program memory loader programming. 4 X X 0 Level 3 plus no external execution. parallel programming mode or when executing a verify-option control-register instruction in ROM loader mode. programmed in-system from an external source through serial port 0 under the control of a built-in ROM loader. communication and sets up the baud rate generator for communication at that frequency. fetching from the 2kB internal ROM for program memory initialization and other loader functions. default state. Otherwise, the memory bank select cannot be altered in the ROM loader mode.
Figure 7. Interfacing the Bootloader to a PC The microcontroller also supports a programming mode such as that used by commercial device programmers. An internal data memory cycle spans only one system clock period to support fast internal execution.
Table 4. Parallel Programming Instruction Set location is returned to FFh. Memory ADDR DIN PL (3) L H H H Program the 16k program memory. Memory ADDR DOUT H (4) L L H H Verify the 16k program memory. Array ADDR DIN PL (3) L H L H Program the 64 byte encryption array. Write LB1 Dont care Dont care PL (3) H H H H Program LB1 to logic 0. Write LB2 Dont care Dont care PL (3) H H L L Program LB2 and LB1 to 00b. Write LB3 Dont care Dont care PL (3) H L H L Program LB3, LB2, and LB1 to 000b. LB3, LB2, and LB1, respectively. FCh = Verify the option control register. 1) Mass erase requires an active-low PROG pulse width of 828ms. 2) Erase option control register requires an active-low PROG pulse width of 828ms. 3) Byte program requires an active-low PROG pulse width of 100/g109s max. 4) PROG is weakly pulled to a high internally. Note 1: P3.2 is pulled low during programming to indicate Busy. P3.2 is pulled high again when programming is completed to indicate Ready. Note 2: P3.0 is pulled high during programming to indicate an error.
DS89C420 Ultra-High-Speed Microcontroller 25 of 47 The SEL (DPS.0) bit always selects the active data pointer. The DS89C420 offers a programmable option that allows any instructions related to data pointer to toggle the SEL bit automatically. This option is enabled by setting the toggle-select-enable bit (TSL-DPS.5) to logic 1. Once enabled, the SEL bit is automatically toggled after the execution of one of the following five DPTR-related instructions: INC DPTR MOV DPTR #data16 MOVC A, @A+DPTR MOVX A, @DPTR MOVX @DPTR, A The DS89C420 also offers a programmable option that automatically increases (or decreases) the contents of the selected data pointer by 1 after the execution of a DPTR-related instruction. The actual function (increment or decrement) is dependent upon the setting of the ID1 and ID0 bits. This option is enabled by setting the automatic increment/decrement enable (AID-DPS.4) to a logic 1 and is affected by one of the following three instructions: MOVC A, @A+DPTR MOVX A, @DPTR MOVX @DPTR, A EXTERNAL MEMORY The DS89C420 executes external memory cycles for code fetches and read/writes of external program and data memory. A non-page external memory cycle is four times slower than the internal memory cycles (i.e., an external memory cycle contains four system clocks). For this reason, although a DS89C420 can be substituted for a ROM- less 8051 device (DS80C310, C320, etc.), there is no increase in execution speed. However, a page mode external memory cycle can be completed in 1, 2, or 4 system clocks for a page hit and 2, 4, or 8 system clocks for a page miss, depending on user selection. The DS89C420 also supports a second page mode operation with a different external bus structure that provides for fast external code fetches but uses 4 system clock cycles for data memory access. EXTERNAL PROGRAM MEMORY INTERFACE (NON-PAGE MODE) Figure 8 shows the timing relationship for internal and external code fetches when CD1 and CD0 are set to 10b, assuming the microcontroller is in non-page mode for external fetches. Note that an external program fetch takes 4 system clocks, and an internal program fetch requires only 1 system clock. As illustrated in Figure 8, ALE is deasserted when executing an internal memory fetch. The DS89C420 provides a programmable user option to turn on ALE during internal program memory operation. ALE is automatically enabled for code fetch externally, independent of the setting of this option. PSEN is only asserted for external code fetches, and is inactive during internal execution. EXTERNAL DATA MEMORY INTERFACE IN NON-PAGE MODE OPERATION Just like the program memory cycle, the external data memory cycle is four times slower than the internal data memory cycle in non-page mode. A basic internal memory cycle contains one system clock and a basic external memory cycle contains four system clocks for non-page mode operation. The DS89C420 allows software to adjust the speed of external data memory access by stretching the memory bus cycle. CKCON (8Eh) provides an application-selectable stretch value for this purpose. Software can change the stretch value dynamically by changing the setting of CKCON.2CKCON.0. Table 5 shows the data memory cycle stretch values and their effects on the external MOVX-memory bus cycle and the control signal pulse width in terms of the number of oscillator clocks. A stretch machine cycle always contains four system clocks.
configuration of P0 and P2 for the purposes of address output and data I/O during external memory cycles. PSEN are altered to support this mode of operation. register requires a timed access. Table 6. Page Mode Select P2: The upper address byte is multiplexed with the data byte. memory machine cycle can be 2, 4, or 8 system clocks in length for a page miss. external memory machine cycle can be 1, 2, or 4 system clocks in length for a page hit. PSEN, RD, and WR strobe accordingly for the appropriate operation on the P0 data bus. There is no ALE assertion for page hits. and the appropriate operation takes place.
DS89C420 Ultra-High-Speed Microcontroller 29 of 47 Note that there are a few exceptions for this mode of operation when PAGES1 and PAGES2 are set to 00b: /g167/g32 PSEN is asserted for both page hit and page miss for a full clock cycle. /g167/g32The execution of external MOVX instruction causes a page miss. /g167/g32A page miss occurs when fetching the next external instruction following the execution of an external MOVX instruction. Figure 11 shows the external memory cycle for this bus structure. The first case illustrates a back-to-back execution sequence for 1-cycle page mode (PAGES1 = PAGES0 = 0b). PSEN remains active during page-hit cycles, and page misses are forced during and after MOVX executions, independent of the most significant byte of the subsequent addresses. The second case illustrates a MOVX execution sequence for 2-cycle page mode (PAGES1 = 0 and PAGES0 = 1). PSEN is active for a full clock cycle in code fetches. Note that changing the MSB of the data address causes the page misses in this sequence. The third case illustrates a MOVX execution sequence for 4-cycle page mode (PAGES1 = 1 and PAGES0 = 0). There is no page miss in this execution cycle because the most significant byte of the data address is assumed to match the last program address. The second page mode (page mode 2) external bus structure multiplexes the most significant address byte with data on P2, and uses P0 for the least significant address byte. This bus structure is used to speed up external code fetches only. External data-memory access cycles are identical to the non-page mode except for the different signals on P0 and P2. Figure 12 illustrates the memory cycle for external code fetches.
Figure 11. Page Mode 1, External Memory Cycle (CD1:CD0 = 10)
Figure 12. Page Mode 2, External Code Fetch Cycle (CD1:CD0 = 10) logic value of the page mode select bits. Table 7. Page Mode 1, Data Memory Cycle Stretch Values (Pages1:Pages0 = 00) Table 8. Page Mode 1, Data Memory Cycle Stretch Values (Pages1:Pages0 = 01)
Table 9. Page Mode 1, Data Memory Cycle Stretch Values (Pages1:Pages0 = 10) Table 10. Page Mode 2, Data Memory Cycle Stretch Values (Pages1:Pages0 = 11) system clock mode (CD1:CD0 = 10b).
supports five levels of interrupt priorities instead of the original two. Table 11. Interrupt Summary *Cleared automatically by hardware when the service routine is vectored to. the flag follows the state of the pin. events, where 1-to-0 transitions on a port pin are monitored and counted, or timers that count oscillator cycles. Table 12 summarizes the timer functions.
timer control (TCON) register enables Timers 0 and 1. Table 12. Timer Functions *8-bit timer/counter includes auto-reload feature; 2- x 8-bit mode does not. TL2 and TH2) is enabled by the T2CON register, and its mode of operation is selected by the T2MOD register. at divide by 2, regardless of the setting of its timer mode bits.
DS89C420 Ultra-High-Speed Microcontroller 37 of 47 Before these bits can be altered, the processor must execute the timed access sequence. This sequence consists of writing an AAh to the timed access (TA, C7h) register, followed by writing a 55h to the same register within three machine cycles. This timed sequence of steps then allows any of the timed-access-protected SFR bits to be altered during the three machine cycles, following the writing of the 55h. Writing to a timed access-protected bit outside of these three machine cycles has no effect on the bit. The timed-access process is address-, data-, and time-dependent. A processor running out of control and not executing system software cannot statistically perform this timed sequence of steps, and as such, will not accidentally alter the protected bits. It should be noted that this method should be used in the main body of the system software and never used in an interrupt routine in conjunction with the watchdog reset. Interrupt routines using the timed-access watchdog-reset bit (RWT) can recover a lost system and allow the resetting of the watchdog, but the system returns to a lost condition once the RETI is executed, unless the stack is modified. It is advisable that interrupts be disabled (EA = 0) when executing the timed-access sequence, since an interrupt during the sequence adds time, making the timed-access attempt fail. POWER MANAGEMENT AND CLOCK-DIVIDE CONTROL The DS89C420 incorporates power management features that monitor the power-supply voltage levels and support low-power operation with three power-saving modes. Such features include a bandgap voltage monitor, watchdog timer, selectable internal ring oscillator, and programmable system clock speed. The SFRs that provide control and application software access are the watchdog control (WDCON, D8h), extended interrupt enable (EIE, E8h), extended interrupt flag (EXIF, 91h), and power control (PCON, 87h) registers. SYSTEM CLOCK-DIVIDE CONTROL The programmable clock-divide control bits (CD1 and CD0) provide the processor with the ability to adapt to different crystals and also to slow the system clocks providing lower power operation when required. An on-chip crystal multiplier allows the DS89C420 to operate at two or four times the crystal frequency by setting the 4X/ 2X bit and is enabled by setting the CTM bit to a logic 1. An additional circuit provides a clock source at divide-by-1024. When used with a 7.372MHz crystal, for example, the processor executes machine cycle in times ranging from 33.9ns (divide-by-0.25) to 138.9 /g109s (multiply-by-1024), and maintains a highly accurate serial port baud rate while allowing the use of more cost-effective, lower-frequency crystals. Although the clock-divide control bits can be written at any time, certain hardware features have been provided to enhance the use of these clock controls to guarantee proper serial port operation, and also to allow for a high-speed response to an external interrupt. The 01b setting of CD1 and CD0 is reserved, and has the same effect as the 10b setting, which forces the system clock into a divide by 1 mode. The DS89C420 defaults to divide-by-1 clock mode on all forms of reset. When programmed to the divide-by-1024 mode, and the switchback bit (PMR.5:SWB) is also set, the system forces the clock-divide control bits to reset automatically to the divide-by-1 mode whenever the system has detected externally enabled interrupts. The oscillator divide ratios of 0.25, 0.5, and 1 are also used to provide standard baud-rate generation for the serial ports through a forced divide-by-12 input clock (TxMH, TxM = 00b, x = 1, 2, or 3) to the timers. When in divide-by-1024 mode, in order to allow a quick response to incoming data on a serial port, the system uses the switchback mode to automatically revert to divide-by-1 mode whenever a start bit is detected. This automatic switchback is only enabled during divide-by-1024 mode, and all other clock modes are unaffected by interrupts and serial port activity. See Power Management Mode for more details. Use of the divide-by-0.25 or 0.5 options through the clock-divide control bits requires that the crystal multiplier be enabled and the specific system-clock-multiply value be established by the 4X/ 2X bit in the PMR register. The multiplier is enabled through the CTM (PMR.4) bit but cannot be automatically selected until a startup delay has been established through the CKRY bit in the status register. The 4X/2X bit can only be altered when the CTM bit is cleared to logic 0. This prevents the system from changing the multiplier until the system has moved back to the divide-by-1 mode and the multiplier has been disabled through the CTM bit. The CTM bit can only be altered when the CD1 and CD0 bits are set to divide-by-1 mode and the RGMD bit is cleared to 0. Setting the CTM to logic 1 from a previous logic 0 automatically clears the CKRY bit in the status register and starts the multiplier startup timeout in the multiplier startup counter. During the multiplier startup period the CKRY bit remains cleared and the CD1 and CD0 clock controls cannot be set to 00b. The CTM bit is cleared to logic 0 on all resets. Figure 15 gives a
use of the 4X/2X CTM, CKRY, CD1, and CD0 bits are outlined in the SFR description. Figure 15. System Clock Sources The power monitor in the DS89C420 monitors the V CC pin in relation to the on-chip bandgap voltage reference. automatically disabled to conserve power, if the BGS (EXIF.0) bit is set to a logic 0. This is the lowest power mode. although in a reduced fashion, while in stop mode.
settings and the timeout values. Table 13. Watchdog Timeout Value (in Number of Oscillator Clocks) watchdog interrupt can be programmed to allow a system to wake up periodically to sample the external world. delay of 65,536 clock cycles to allow the oscillator to stabilize. circuit. Connecting the RST pin to a capacitor does not affect the internal reset condition.
DS89C420 Ultra-High-Speed Microcontroller 40 of 47 OSCILLATOR-FAIL DETECT The DS89C420 incorporates an oscillator fail-detect circuit that, when enabled, causes a reset if the crystal oscillator frequency falls below 20kHz and holds the chip in reset with the ring oscillator operating. Setting the OFDE (PCON.4) bit to logic 1 enables the circuit. The OFDE bit is only cleared from logic 1 to logic 0 by a power- fail reset or by software. A reset caused by an oscillator failure also sets the OFDF (PCON.5) to logic 1. This flag is cleared by software or power-on reset. Note that this circuit does not force a reset when the oscillator is stopped by the software-enabled stop mode. POWER MANAGEMENT MODE Power management mode offers a software-controllable power-saving scheme by providing a reduced instruction cycle speed, which allows the DS89C420 to continue to operate while using an internally divided version of the clock source to save power. Power management mode is invoked by software setting the clock-divide control bits CD1 and CD0 (PMR.7-6) bits to 11b, which sets an operating rate of 1024 oscillator cycles for 1 machine cycle. On all forms of reset, the clock-divide control bits default to 10b, which selects 1 oscillator cycle per machine cycle. Since the clock speed choice affects all functional logic including timers, the DS89C420 implements several hardware switchback features that allow the clock speed to automatically return to the divide-by-1 mode from a reduced cycle rate. Setting the SWB (PMR.5) bit to a 1 in software enables this switchback function. When CD1 and CD0 are programmed to the divide-by-1024 mode and the SWB bit is also enabled, the system forces the clock-divide control bits to automatically reset to the divide-by-1 mode whenever the system detects an externally enabled (and allowed through nesting priorities) interrupt. The switchback occurs whenever one of the two conditions occur. The first switchback condition is initiated by the detection of a low on either INT0, INT1, INT3 or INT5, or a high on INT2 or INT4 when the respective pin has been programmed and allowed (through nesting priorities) to issue an interrupt. The second switchback condition occurs when either serial port is enabled to receive data and is found to have an active-low transition on the respective receive input pin. Serial port transmit activity also forces a switchback if the SWB is set. Note that the serial port activity, as related to the switchback, is independent of the serial port interrupt relationship. Any attempt to change the clock divider to the divide-by-1024 mode while the serial port is either transmitting or receiving has no effect, leaving the clock control in the divide-by- 1 mode. Note also that the switchback interrupt relationship requires that the respective external interrupt source is allowed to actually generate an interrupt as defined by the priority of the interrupt and the state of the nested interrupts, before the switchback can actually occur. An interrupt by the serial port is not required, nor is the setting of serial port enable. Disabling external interrupts and serial port receive/transmission mode disable the automatic switchback mode. Clearing the SWB bit also disables the switchback, and all interrupt and serial port controls of the clock divider are disabled. All other clock modes ignore the switchback relationship and are unaffected by interrupts and serial port activity. The basic divide-by-12 mode for the timers (TxMH, TxM = 00b), as well as the divide-by-32 and 64 for mode 2 on the serial ports, are maintained when running the processor with the oscillator divide ratio of 0.25, 0.5, and 1. Serial ports and timers track the oscillator cycles per machine cycle when the higher divide ratio of 1024 is selected, and require the switchback function to automatically return to the divide-by-1 mode for proper operation when a qualified event occurs. Table 14 summarizes the effect of clock mode on timer operation. It is possible to enable a receive function on a serial port when incoming data is not present and then change to the higher divide ratio. An inactive serial port receive/transmit mode requires the receive input pin to remain high and all outgoing transmissions to be completed. During this inactive receive mode it is possible to change the clock- divide control bits from a divide-by-1 to a 1024 divide ratio. In the case when the serial port is being used to receive or transmit data it is very important to validate an attempted change in the clock-divide control bits (read CD1 and CD0 to verify write was allowed) before proceeding with low-power program functions.
Table 14. Effect of Clock Mode on Timer Operation (in Number of Oscillator Clocks) A ring oscillator, which typically runs at 10MHz, allows the processor to recover instantly from the stop mode. rate. The ring oscillator does not drive it. immediately follows the instruction that invoked the idle mode. Any processor resets also remove the idle mode. are stopped, and no processing is possible.
DS89C420 Ultra-High-Speed Microcontroller 42 of 47 An external reset by the RST pin unconditionally exits the processor from stop mode. If the BGS bit is set to logic 1, the bandgap provides a reset while in stop mode if V CC should drop below the V RST level. If BGS is 0, no reset is generated if VCC drops below VRST. When the stop mode is removed, the processor waits for 65,536 clock cycles for the internal flash memory to warm up before starting normal execution. Also, the processor waits for the crystal warmup period if not using the ring oscillator. SERIAL I/O The DS89C420 provides a serial port (UART) that is identical to the 80C52. In addition, it includes a second hardware serial port that is a full duplicate of the standard one. This port optionally uses pins P1.2 (RXD1) and P1.3 (TXD1) and has duplicate control functions included in new SFR locations. Both ports can operate simultaneously but can be at different baud rates or even in different modes. The second serial port has similar control registers (SCON1 at C0h, SBUF1 at C1h) as the original. The new serial port can only use timer 1 for timer-generated baud rates. Control for serial port 0 is provided by the SCON0 register while its I/O buffer is SBUF0. Registers SCON1 and SBUF1 provide the same functions for the second serial port. A full description of the use and operation of both serial ports is in the Ultra-High-Speed Flash Microcontroller Users Guide. INSTRUCTION SET The DS89C420 instructions are 100% binary compatible with the industry standard 8051, and are only different in the number of machine cycles used for the instructions. Some special conditions and features should be considered when analyzing the DS89C420 instruction set. Full details are given in the Ultra-High-Speed Flash Microcontroller Users Guide.
DS89C420 Ultra-High-Speed Microcontroller 43 of 47
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) PKG 40-PIN DIM MIN MAX A 0.200 A1 0.015 A2 0.140 0.160 b 0.014 0.022 c 0.008 0.012 D 1.980 2.085 E 0.600 0.625 E1 0.530 0.555 e 0.090 0.110 L 0.115 0.145 eB 0.600 0.700 56G5000000 Dimensions are in inches (in).
DS89C420 Ultra-High-Speed Microcontroller 44 of 47 Note 1: Pin 1 identifier to be located in zone indicated. Note 2: Controlling dimensions are in inches (in).
DS89C420 Ultra-High-Speed Microcontroller 45 of 47
DS89C420 Ultra-High-Speed Microcontroller 46 of 47 PIN CONFIGURATIONS 6 1 40 18 28 7 39 17 29 Dallas Semiconductor DS89C420 TOP VIEW PLCC 33 23 1 11 34 22 44 12 Dallas Semiconductor DS89C420 TOP VIEW TQFP P1.0/T2 P1.1/T2EX P1.2/RXD1 P1.3/TXD1 P1.4/INT2 P1.5/INT3 P1.6/INT4 P1.7/INT5 RST P3.0/RXD0 P3.1/TXD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS VCC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 DS89C420 DIP TOP VIEW
DS89C420 Ultra-High-Speed Microcontroller 47 of 47 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Ma xim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specification s without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products /g183 Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.
REVISION HISTORY
092200 Initial release
122601 Added errata (See www.maxim-ic.com/errata for details.)
042702 Official product introduction release
051302 Inserted AC Characteristics table
103102 Removed (Min Operating Voltage) from DC Electrical Characteristics;
inserted diagram of ROM loader interface circuit
032003 Added 25MHz variant information
102203 Modified Figure 7 to support programmer-only operation. 081805 Clarified availability of progamming software. Corrected min/max external clock speed table in Note 1. Removed detailed parallel programming instructions and repalced with a note to contact factory for more information.