DS89C387TMEA

DS89C387_16 TI1 | Alldatasheet

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www.ti.com SNLS101E –MAY 1995–REVISED APRIL 2013 DS89C387TwelveChannelCMOS DifferentialLineDriver Check forSamples: DS89C387 1FEATURES DESCRIPTION The DS89C387 is a high speed twelve channel 2• Low Power ICC :1.5mA Maximum CMOS differentialdriverthatmeets therequirements• Meets TIA/EIA-422-B(RS-422) ofTIA/EIA-422-B.The DS89C387 featuresa low ICC

• Ensured AC Parameters: specificationof 1.5 mA maximum, which makes it ideal for batterypowered and power conscious– Maximum DriverSkew −3 ns applications.The devicereplacesthreeDS34C87s– Maximum TransitionTime −10 ns and offersa PC boardspace savingsup to30%. The
• AvailableinSSOP Packaging: twelve channel driveris availablein a SSOP package. The deviceis idealforwide parallelbus– Requires30% Less PCB Space than 3 applications.DS34C87TMs Each TRI-STATE enable (EN) allows the driver outputsto be activeor ina HI-impedanceoffstate. Each enable is common to only two driversfor flexibilityand control.The driversmay be disabledto turnoffloadcurrentand tosave power when datais notbeingtransmitted. The driver'sinput(DI)iscompatiblewithboth TTL and CMOS signallevels. Connection Diagrams 1/6ofpackage Figure2. FunctionalDiagram TruthTable Enable Input Outputs EN DI DO DO* L X Z Z H H H L H L L H Figure1. 48-PinSSOP Package See Package Number DL0048A Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1995–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS101E –MAY 1995–REVISED APRIL 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2)(3) SupplyVoltage(VCC ) −0.5to7.0V DC Voltage(VIN) −1.5toVCC +1.5V DC OutputVoltage(VOUT ) −0.5to7V Clamp DiodeCurrent(IIK,IOK ) ±20 mA DC OutputCurrent,perpin(IOUT ) ±150 mA DC VCC orGND Current(ICC ) ±500 mA StorageTemperatureRange (TSTG ) −65°C to+150°C JunctionTemperature +150°C Maximum Power Dissipation(PD )@ 25°C (4) ThermalResistance θJA 81.7°C/W θJC 31.7°C/W Lead Temperature(TL) (Soldering4 sec.) 260°C Thisdevicedoes notmeet 2000V ESD rating.(5) (1) Unlessotherwisespecified,allvoltagesarereferencedtoground.Allcurrentsintodevicepinsarepositive;allcurrentsoutofdevice pinsarenegative. (2) AbsoluteMaximum Ratingsarethosevaluesbeyond whichthesafetyofthedevicecannotbe specified.They arenotmeant toimply thatthedeviceshouldbe operatedattheselimits.The tableof“ElectricalCharacteristics”provideconditionsforactualdeviceoperation. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. (4) Ratingsapplytoambienttemperatureat25°C. Above thistemperaturederateSSOP (MEA) Package 10.9mW/ °C. (5) ESD Rating:HBM (1.5kΩ,100 pF) Inputs≥ 1500V Outputs≥ 1000V EIAJ (0Ω,200 pF) AllPins≥ 350V OperatingConditions Min Max Units SupplyVoltage(VCC ) 4.50 5.50 V DC InputorOutputVoltage(VIN,VOUT ) 0 VCC V OperatingTemperatureRange (TA) DS89C387T −40 +85 °C InputRiseorFallTimes (tr,tf) 500 ns DC ElectricalCharacteristics(1)(2) VCC = 5V ±10% (unlessotherwisespecified) Parameter TestConditions Min Typ Max Units VIH HighLevelInput 2.0 VCC V Voltage VIL Low LevelInput GND 0.8 V Voltage VOH HighLevelOutput VIN = VIH orVIL, 2.5 3.4 V Voltage IOUT = −20 mA VOL Low LevelOutput VIN = VIH orVIL, 0.3 0.5 V Voltage IOUT = 48 mA (1) Unlessotherwisespecified,allvoltagesarereferencedtoground.Allcurrentsintodevicepinsarepositive;allcurrentsoutofdevice pinsarenegative. (2) Unlessotherwisespecified,min/max limitsapplyacrossthe−40°C to85°C temperaturerange.AlltypicalsaregivenforVCC = 5V and TA = 25°C.

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www.ti.com SNLS101E –MAY 1995–REVISED APRIL 2013 DC ElectricalCharacteristics(1)(2)(continued) VCC = 5V ±10% (unlessotherwisespecified) Parameter TestConditions Min Typ Max Units VT DifferentialOutput R L = 100Ω 2.0 3.1 V Voltage See (3) |VT|–|VT| DifferenceIn R L = 100Ω 0.4 V DifferentialOutput See (3) VOS Common Mode R L = 100Ω 2.0 3.0 V OutputVoltage See (3) |VOS –VOS | DifferenceIn R L = 100Ω 0.4 V Common Mode Output See (3) IIN InputCurrent VIN = VCC ,GND, VIH,orVIL ±1.0 μA ICC QuiescentSupply IOUT = 0 μA, 600 1500 μA Current VIN = VCC orGND VIN = 2.4Vor0.5V(4) 0.8 2.0 mA IOZ TRI-STATE Output VOUT = VCC orGND ±0.5 ±5.0 μA Leakage Current Control= VIL ISC OutputShort VIN = VCC orGND −30 −115 −150 mA CircuitCurrent See (3)and (5) IOFF Power OffOutput VCC = 0V VOUT = 6V 100 μA Leakage Current See (6) VOUT = −0.25V −100 μA (3) See TIA/EIA-422-Bforexacttestconditions. (4) Measured perinput.AllotherinputsatVCC orGND. (5) Thisisthecurrentsourcedwhen a highoutputisshortedtoground.Onlyone outputata timeshouldbe shorted. (6) See TIA/EIA-422-Bforexacttestconditions. SwitchingCharacteristics(1) VCC = 5V ±10%, tr,tf ≤ 6 ns (Figure3,Figure4,Figure5,and Figure6) Parameter TestConditions Min Typ Max Units tPLH ,tPHL PropagationDelay S1 Open 2 6 11 ns InputtoOutput Skew See (2) S1 Open 0 0.5 3 ns tTLH ,tTHL DifferentialOutputRise S1 Open 6 10 ns And FallTimes tPZH OutputEnableTime S1 Closed 12 25 ns tPZL OutputEnableTime S1 Closed 13 26 ns tPHZ OutputDisableTime(3) S1 Closed 4 8 ns tPLZ OutputDisableTime(3) S1 Closed 6 12 ns C PD Power Dissipation 100 pF Capacitance(4) C IN InputCapacitance 6 pF (1) Unlessotherwisespecified,min/max limitsapplyacrossthe−40°C to85°C temperaturerange.AlltypicalsaregivenforVCC = 5V and TA = 25°C. (2) Skew isdefinedas thedifferenceinpropagationdelaysbetween complementaryoutputsatthecrossingpoint. (3) Outputdisabletimeisthedelayfromthecontrolinputbeingswitchedtotheoutputtransistorsturningoff.The actualdisabletimesare lessthanindicateddue tothedelayadded by theRC timeconstantoftheload. (4) C PD determinestheno loaddynamicpower consumption,PD = C PD V2CC f+ ICC VCC ,and theno loaddynamiccurrentconsumption,IS = C PD VCC f+ ICC . Copyright© 1995–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS89C387

SNLS101E –MAY 1995–REVISED APRIL 2013 www.ti.com Logic Diagram Parameter Measurement Information C1 = C2 = C3 = 40 pF (includingProbe and JigCapacitance),R1 = R2 = 50Ω,R3 = 500Ω Figure3. AC TestCircuit

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www.ti.com SNLS101E –MAY 1995–REVISED APRIL 2013 Parameter Measurement Information(continued) Figure4. PropagationDelays Figure5. Enable and DisableTimes Inputpulse;f= 1 MHz, 50%, tr ≤ 6 ns,tf≤ 6 ns Figure6. DifferentialRise and FallTimes TypicalApplication *R T isoptionalalthoughhighlyrecommended toreducereflection. Figure7. Two-Wire Balanced System, RS-422 Copyright© 1995–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS89C387

SNLS101E –MAY 1995–REVISED APRIL 2013 www.ti.com

APPLICATION INFORMATION

Skew may be thoughtofina lotofdifferentways,thenextfew paragraphsshouldclarifywhat isrepresentedby “Skew ” inthedatasheetand how itisdetermined.Skew, as used inthisdatabook,istheabsolutevalueofa mathematicaldifferencebetween two propagationdelays.This is commonly accepted throughoutthe semiconductorindustry.However,thereisno standardizedmethod ofmeasuringpropagationdelay,fromwhich skew iscalculated,of differentiallinedrivers.Elucidating,the voltagelevel,at which propagationdelaysare measured, on both inputand outputwaveforms are not always consistant.Therefore,skew calculatedinthis datasheet,may notbe calculatedthesame as skew definedinanother.Thisisimportanttoremember whenever making a skew comparison. Skew may be calculatedfortheDS89C387, frommany differentpropagationdelaymeasurements.They may be classifiedintothreecategories,single-ended,differential,and complementry.Single-endedskew iscalculated from tPHL and tPLH measurements (see Figure9 and Figure11).Differentialskew iscalculatedfrom tPHLD and tPLHD measurements (see Figure12 and Figure13).Complementry skew is calculatedfrom tPHL and tPLH measurements (seeFigure14 and Figure15). Figure8. (Circuit1)– CircuitsforMeasuring Single-EndedPropagationDelays (See Figure11) Figure9. (Circuit2)– CircuitsforMeasuring Single-EndedPropagationDelays (See Figure11) Figure10. Waveforms forCircuit1 – PropagationDelay Waveforms forCircuit1 and Circuit2 (See Figure9) Figure11. Waveforms forCircuit2 – PropagationDelay Waveforms forCircuit1 and Circuit2 (See Figure9)

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www.ti.com SNLS101E –MAY 1995–REVISED APRIL 2013 In Figure 4, VX, where X is a number, is the waveform voltagelevelat which the propagationdelay measurement eitherstartsorstops.Furthermore,V1 and V2 arenormallyidentical.The same istrueforV3 and V4. However, as mentionedbefore,theselevelsare notstandardizedand may vary,even withsimilardevices fromothercompanies.Alsonote,NC (noconnection)inFigure3 means thepinisnotused inpropagationdelay measurement forthecorrespondingcircuit. The single-endedskew providesinformationaboutthepulsewidthdistortionoftheoutputwaveform.The lower theskew,thelesstheoutputwaveform willbe distorted.For bestcase,skew would be zero,and theoutputduty cyclewouldbe 50%, assumingtheinputhas a 50% dutycycle. Figure12. (Circuit3)– CircuitforMeasuring DifferentialPropagationDelays (See Figure13) Figure13. Waveforms forCircuit3 – PropagationDelay Waveforms forCircuit3 (See Figure12) For differentialpropagationdelays,V1 should equal V2. Furthermore,the crossingpointof DO and DO* correspondstozerovoltson thedifferentialwaveform (seebottomwaveform inFigure13).Thisistruewhether V3 equalsV4 ornot.However,ifV3 and V4 arespecifiedvoltages,thenV3 and V4 arelesslikelytobe equalto the crossingpointvoltage.Thus, the differentialpropagationdelayswillnot be measured to zero voltson the differentialwaveform. The differentialskew alsoprovidesinformationaboutthepulsewidthdistortionofthedifferentialoutputwaveform relativetotheinputwaveform.The highertheskew,thegreaterthedistortionofthedifferentialoutputwaveform. Assuming theinputhas a 50% dutycycle,thedifferentialoutputwillhave a 50% dutycycleifskew equalszero and lessthana 50% dutycycleifskew isgreaterthanzero. Figure14. (Circuit4)– CircuitforMeasuring Complementary Skew (See Figure15) Copyright© 1995–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS89C387

SNLS101E –MAY 1995–REVISED APRIL 2013 www.ti.com Figure15. Waveforms forCircuit4 – Waveforms forCircuit4 (See Figure14) Complementary skew is calculatedfrom single-endedpropagationdelay measurements on complementary outputsignals,DO and DO*. Note,when V3 and V4 areabsolutevalues,theyareidenticalon DO and DO*; but varywhenever theyarerelativevalues. The complementaryskew revealsinformationaboutthecontouroftherisingand fallingedge ofthedifferential outputsignalofthedriver.Thisisimportantinformationbecause thereceiverwillinterpretthedifferentialoutput signal.Ifthedifferentialtransitionsdo notcontinuouslyascend ordecend throughthereceiversthresholdregion, errorsmay occur.Errorsmay alsooccurifthetransitionsaretooslow. In addition,complementaryskew providesinformationabout the common mode modulationof the driver.The common mode voltageisrepresentedby (DO –DO*)/2.Thisinformationmay be used as a means fordetermining EMI affects. Only “Skew ” isspecifiedinthisdatasheetfortheDS89C387. Itreferstothecomplementaryskew ofthedriver. Complementaryskew ismeasured atbothV3 and V4 (seeFigure15). More informationcan be calculatedfrom thepropagationdelays.The channeltochanneland devicetodevice skew may be calculatedinadditiontothetypesofskew mentionedpreviously.These parametersprovidetiming performanceinformationbeneficialwhen designing.The channeltochannelskew iscalculatedfromthevariation inpropagationdelayfromreceivertoreceiverwithinone package.The devicetodeviceskew iscalculatedfrom thevariationinpropagationdelayfromone DS89C387 toanotherDS89C387. For theDS89C387, themaximum channeltochannelskew is9 ns (tp max –tp min)where tp isthelow tohighor hightolowpropagationdelay.The minimum channeltochannelskew is0 ns sinceitispossibleforall12 drivers to have identicalpropagationdelays.Note, thisis best and worst case calculationsused whenever Skew (channel)isnotindependentlycharacterizedand specifiedinthedatasheet.The devicetodeviceskew may be calculatedinthesame way and theresultsarethesame. Therefore,thedevicetodeviceskew is9 ns and 0 ns maximum and minimum respectively. Table1.DS89C387 Skew Table Parameter Min Typ Max Units Skew (comp.) 0 0.5 3 ns Skew (channel) 0 9 ns Skew (device) 0 9 ns Note Skew (comp.)inTable1 isthesame as “Skew ”inthedatasheet.AlsoSkew (channel)and Skew (device) arecalculations,butarespecifiedby thepropagationdelaytests.Both Skew (channel)and Skew (device)would normallybe tighterwhenever specifiedfromcharacterizationdata. The informationinthissectionof the datasheetisto helpclarityhow skew isdefinedinthisdatasheet.This shouldhelpwhen designingtheDS89C387 intomost applications.

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www.ti.com SNLS101E –MAY 1995–REVISED APRIL 2013 DS89C387 EquivalentInput/OutputCircuits Figure16. DriverOutput EquivalentCircuit Figure17. DriverInputor DriverEnable EquivalentCircuit Copyright© 1995–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS89C387

SNLS101E –MAY 1995–REVISED APRIL 2013 www.ti.com Table2.Pin Descriptions Pin No. Pin Name Pin Description 7,8,15,16,22,23, DI TTL/CMOS CompatibleDriverInput 31,32,39,40,46,47 2,6,9,13,17,21, DO Non-InvertingDriverOutputPin 26,30,33,37,41,45 3,5,10,12,18,20, DO* InvertingDriverOutputPin 27,29,34,36,44,44 4,11,19,28,35,43 EN ActiveHighDualDriverEnablingPin

38 VCC PositivePower SupplyPin+5 ±10%

14,24 GND DeviceGround Pin 1,25,48 NC Unused Pin(NOT CONNECTED)

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www.ti.com SNLS101E –MAY 1995–REVISED APRIL 2013

REVISION HISTORY

Changes from RevisionD (April2013)toRevisionE Page Copyright© 1995–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:DS89C387

www.ti.com 15-Jun-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS89C387TMEA NRND SSOP DL 48 29 TBD Call TI Call TI -40 to 85 DS89C387T MEA DS89C387TMEA/NOPB ACTIVE SSOP DL 48 29 Pb-Free (RoHS) CU SN | Call TI Level-2A-260C-4 WEEK -40 to 85 DS89C387T MEA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

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