DS89C386_16 TI1 | Alldatasheet

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www.ti.com SNLS100C –MAY 1995–REVISED APRIL 2013 DS89C386TwelveChannelCMOS DifferentialLineReceiver Check forSamples: DS89C386 1FEATURES DESCRIPTION The DS89C386 is a high speed twelve channel 2• Low Power Design— 240 mW Typical CMOS differentialreceiver that meets the• Meets TIA/EIA-422-B(RS-422) requirements of TIA/EIA-422-B.The DS89C386

  • ReceiverOPEN InputFailsafeFeature featureslowpower dissipationof240 mW typical.
  • Ensured AC Parameters: Each TRI-STATE enable,EN, allowsthe receiver – Maximum ReceiverSkew −4 ns outputto be activeor in a Hi-impedanceoffstate. Each enable is common to only two receiversfor– Maximum TransitionTime −9 ns flexibilityand multiplexingofreceiveroutputs.• High Output DriveCapability:±6 mA The receiveroutput(RO) isensuredtobe High when• AvailableinSSOP Packaging: the inputsare leftopen and unterminated.The– Requires30% lessPCB Space than 3 receivercan detectsignalsas low and including±200DS34C86TMs mV over the common mode range of ±7V. The receiveroutputs(RO) are compatiblewithboth TTL and CMOS levels. Connection Diagrams 1/6ofpackage Figure2. FunctionDiagram TruthTable (1) Enable Inputs Output EN RI–RI* RO L X Z H ≥200 mV orOPEN (1) H H ≤ −200 mV L H +200 mV > and > −200 mV X Figure1. 48-PinSSOP See Package Number DL0048A (1) Not terminated. These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1995–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SNLS100C –MAY 1995–REVISED APRIL 2013 www.ti.com AbsoluteMaximum Ratings(1)(2)(3) SupplyVoltage(VCC ) −0.5to7V InputCommon Mode Range (VCM ) ±14V DifferentialInputVoltage(VDIFF) ±14V EnableInputVoltage(VIN) 7V StorageTemperatureRange (TSTG ) −65°C to+150°C Lead Temperature(Soldering4 sec) 260°C Maximum Power Dissipationat25°C (4) CurrentPer Output ±25 mA Thisdevicedoes not meet 2000V ESD rating.(5) (1) Unlessotherwisespecified,allvoltagesarereferencedtoground. (2) AbsoluteMaximum Ratingsarethosevaluesbeyond whichthesafetyofthedevicecannotbe specified.They arenotmeant toimply thatthedeviceshouldbe operatedattheselimits.The tableof“ElectricalCharacteristics”providesconditionsforactualdevice operation. (3) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTexas InstrumentsSalesOffice/Distributorsforavailabilityand specifications. (4) Ratingsapplytoambienttemperatureat25°C. Above thistemperaturederateSSOP (MEA) Package 10.9mW/ °C. (5) ESD Rating:HEM (1.5kΩ,100 pF) Inputs≥ 2000V Outputs≥ 1000V EIAJ (0Ω,200 pF) AllPins≥ 350V OperatingConditions Min Max Unit SupplyVoltage(VCC ) 4.50 5.50 V OperatingTemperatureRange (TA) DS89C386T −40 +85 °C EnableInputRiseorFallTimes 500 ns DC ElectricalCharacteristics(1) VCC = 5V ±10% (unlessotherwisespecified) Parameter TestConditions Min Typ Max Units VTH DifferentialInputVoltage VOUT = VOH orVOL −200 ±35 +200 mV −7V < VCM < +7V VHYST InputHysteresis VCM = 0V 70 mV R IN InputResistance VIN = −7V,+7V 5.0 6.8 10 kΩ (OtherInput= GND) IIN InputCurrent VIN = +10V, OtherInput= GND +1.1 +1.5 mA (UnderTest) VIN = −10V,OtherInput= GND −2.0 −2.5 mA VOH HighLevelOutputVoltage VCC = Min.,V(DIFF)= +1V 3.8 4.2 V IOUT = −6.0mA VOL Low LevelOutputVoltage VCC = Max.,V(DIFF)= −1V 0.2 0.3 V IOUT = 6.0mA VIH EnableHighInputLevelVoltage 2.0 VCC V VIL EnableLow InputLevelVoltage GND 0.8 V IOZ TRI-STATE OutputLeakage Current VOUT = VCC orGND, EN = VIL ±0.5 ±5.0 μA II EnableInputCurrent VIN = VCC orGND ±1.0 μA ICC QuiescentPower SupplyCurrent VCC = Max.,V(DIFF)= +1V 48 69 mA (1) Unlessotherwisespecified,Min/Max limitsapplyacrosstheoperatingtemperaturerange.AlltypicalsaregivenforVCC = 5V and TA = 25°C.

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www.ti.com SNLS100C –MAY 1995–REVISED APRIL 2013 AC ElectricalCharacteristics(1) VCC = 5V ±10% (Figure3,Figure4,and Figure5) Parameter TestConditions Min Typ Max Units tPLH , PropagationDelay C L = 50 pF tPHL InputtoOutput VDIFF = 2.5V 10 19 30 ns VCM = 0V tSK Skew C L = 50 pF VDIFF = 2.5V 0 2 4 ns VCM = 0V tRISE, OutputRiseand C L = 50 pF tFALL FallTimes VDIFF = 2.5V 4 9 ns VCM = 0V tPLZ , PropagationDelay C L = 50 pF tPHZ ENABLE toOutput R L = 1000Ω 13 18 ns VDIFF = 2.5V tPZL , PropagationDelay C L = 50 pF tPZH ENABLE toOutput R L = 1000Ω 13 21 ns VDIFF = 2.5V (1) Unlessotherwisespecified,Min/Max limitsapplyacrosstheoperatingtemperaturerange.AlltypicalsaregivenforVCC = 5V and TA = 25°C. Logic Diagram Copyright© 1995–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS89C386

SNLS100C –MAY 1995–REVISED APRIL 2013 www.ti.com Parameter Measurement Information Figure3. PropagationDelays C L Includesloadand testjigcapacitance. S1 = VCC fortPZL ,and tPLZ measurements. S1 = GND fortPZH ,and tPHZ measurements. S1 = Open fortPLH ,tPHL ,and tSK . Figure4. TestCircuitforSwitchingCharacteristics Figure5. TRI-STATE Output Enable and DisableWaveforms

APPLICATION INFORMATION

*R T isoptionalalthoughhighlyrecommended toreducereflections. Figure6. Two-Wire Balanced System, RS-422

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www.ti.com SNLS100C –MAY 1995–REVISED APRIL 2013 SKEW Skew may be thoughtofina lotofdifferentways,thenextfew paragraphsshouldclarifywhat isrepresentedby tSK in thisdatasheetand how itisdetermined.Skew, as used in thisdatabook,isthe absolutevalueof a mathematicaldifferencebetween two propagationdelays.This is commonly accepted throughoutthe semiconductorindustry.However,thereisno standardizedmethod ofmeasuringpropagationdelay,fromwhich skew iscalculated,ofdifferentiallinereceivers.Elucidating,thevoltagelevel,atwhich propagationdelaysare measured, on both inputand outputwaveforms are not always consistant.Therefore,skew calculatedinthis datasheet,may notbe calculatedthesame as skew definedinanother.Thisisimportanttoremember whenever making a skew comparison. Skew may be calculatedfortheDS89C386, frommany differentpropagationdelaymeasurements.They may be classifiedintotwo categories,single-endedand differential.Single-endedskew iscalculatedfrom tPHL and tPLH propagationdelaymeasurements (see Figure8 and Figure10).Differentialskew iscalculatedfrom tPHLD and tPLHD differentialpropagationdelaymeasurements (seeFigure11 and Figure12). Figure7. (Circuit1)– CircuitsforMeasuring Single-EndedPropagationDelays (See Figure10) Figure8. (Circuit2)– CircuitsforMeasuring Single-EndedPropagationDelays (See Figure10) Figure9. Waveforms forCircuit1 – PropagationDelay Waveforms forCircuit1 and Circuit2 (See Figure8) Figure10. Waveforms forCircuit2 – PropagationDelay Waveforms forCircuit1 and Circuit2 (See Figure8) Copyright© 1995–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS89C386

SNLS100C –MAY 1995–REVISED APRIL 2013 www.ti.com In Figure10, VX, where X is a number, is the waveform voltagelevelat which the propagationdelay measurement eitherstartsorstops.Furthermore,V1 and V2 arenormallyidentical.The same istrueforV3 and V4. However, as mentionedbefore,theselevelsare notstandardizedand may vary,even withsimilardevices fromothercompanies.Alsonote,VREF inFigure3 shouldequalV1 and V2 inFigure10. The single-endedskew providesinformationaboutthepulsewidthdistortionoftheoutputwaveform.The lower theskew,thelesstheoutputwaveform willbe distorted.For bestcase,skew would be zero,and theoutputduty cyclewouldbe 50%, assumingtheinputhas a 50% dutycycle. Figure11. (Circuit3)– CircuitforMeasuring DifferentialPropagationDelays (See Figure12) Figure12. Waveforms forCircuit3 – PropagationDelay Waveforms forCircuit3 (seeFigure11) For differentialpropagationdelays,V1 may not equal V2. Furthermore,the crossingpointof RI and RI* correspondstozerovoltson thedifferentialwaveform.(See middlewaveform inFigure12.)Thisistruewhether V1 equalsV2 ornot.However,ifV1 and V2 arespecifiedvoltages,thenV1 and V2 arelesslikelytobe equalto thecrossingpointvoltage.Thus,thedifferentialpropagationdelayswillnotbe measured fromzerovoltson the differentialwaveform. The differentialskew alsoprovidesinformationaboutthepulsewidthdistortionoftheoutputwaveform relativeto thedifferentialinputwaveform.The highertheskew,thegreaterthedistortionoftheoutputwaveform.Assuming thedifferentialinputhas a 50% dutycycle,theoutputwillhave a 50% dutycycleifskew equalszeroand less thana 50% dutycycleifskew isgreaterthanzero. Only tSK isspecifiedinthisdatasheetforthe DS89C386. tSK ismeasured singIe-endedlybut correspondsto differentialskew.Because,forsingle-endedskew,when VREF equalsV1 and V2, tPHL equalstPHLD when tPHLD is measured fromthecrossingpoint. More informationcan be calculatedfrom thepropagationdelays.The channeltochanneland devicetodevice skew may be calculatedinadditiontothetypesofskew mentionedpreviously.These parametersprovidetiming performanceinformationbeneficialwhen designing.The channeltochannelskew iscalculatedfromthevariation inpropagationdelayfromreceivertoreceiverwithinone package.The devicetodeviceskew iscalculatedfrom thevariationinpropagationdelayfromone DS89C386 toanotherDS89C386.

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www.ti.com SNLS100C –MAY 1995–REVISED APRIL 2013 For theDS89C386, themaximum channeltochannelskew is20 ns (tp max — tp min)where tp isthelow tohigh or hightolow propagationdelay.The minimum channeltochannelskew is0 ns sinceitispossibleforall12 receiverstohave identicalpropagationdelays.Note,thisisbestand worstcase calculationsused whenever tSK (channel)isnotindependentlycharacterizedand specifiedinthedatasheet.The devicetodeviceskew may be calculatedinthesame way and theresultsareidentical.Therefore,thedevicetodeviceskew is20 ns and 0 ns maximum and minimum respectively. Table1.DS89C386 Skew Table Parameter Min Typ Max Units tSK (diff.) 0 2 4 ns tSK (channel) 0 20 ns tSK (device) 0 20 ns Note tSK (diff.)inTable1 isthesame as tSK inthedatasheet.Also,tSK (channel)and tSK (device)arecalculations, but are ensured by the propagationdelaytests.Both tSK (channel)and tSK (device)would normallybe tighter whenever specifiedfromcharacterizationdata. The informationinthissectionof the datasheetisto helpclarifyhow skew isdefinedinthisdatasheet.This shouldhelpwhen designingtheDS89C386 intomost applications. TypicalPerformance Characteristics ReceiverInputVoltagevs ReceiverInputCurrent The DS89C386 isV.11compatible.IIN (RIinput)isnot ≥ 0 when VIN= 3V due tointernalfailsafebiasresistors(seeFigure10).See ITU V.11forcomplete conditions. Failsafe(open inputs)ismaintainedover entirecommon mode range and operatingrange ±10V. Figure13. DS89C386 EquivalentInput/OutputCircuits Figure14. ReceiverInputEquivalentCircuit Copyright© 1995–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS89C386

SNLS100C –MAY 1995–REVISED APRIL 2013 www.ti.com Figure15. ReceiverOutput EquivalentCircuit Figure16. ReceiverEnable EquivalentCircuit Table2.Pin Descriptions Pin No. Pin Name Pin Description 2,4,9,11,17,19,26, RO TTL/CMOS CompatibleReceiverOutputPin 28,33,35,41,43 5,8,12,16,20,23,29, RI Non-InvertingSignalReceiverInputPin 32,36,40,44,47 6,7,13,15,21,22,30, RI* InvertingSignalReceiverInputPin 31,37,39,45,46 3,10,18,27,34,42 EN ActiveHighDualReceiverEnablingPin

38 VCC PositivePower SupplyPin+5 ±10%

14,24 GND DeviceGround Pin 1,25,48 NC Unused Pin(NOT CONNECTED)

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www.ti.com SNLS100C –MAY 1995–REVISED APRIL 2013

REVISION HISTORY

Changes from RevisionB (April2013)toRevisionC Page Copyright© 1995–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS89C386

www.ti.com 15-Jun-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DS89C386TMEA NRND SSOP DL 48 29 TBD Call TI Call TI -40 to 85 DS89C386T MEA DS89C386TMEA/NOPB ACTIVE SSOP DL 48 29 Pb-Free (RoHS) CU SN | Call TI Level-2A-260C-4 WEEK -40 to 85 DS89C386T MEA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

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