DS8921A

DS8921 TI | Alldatasheet

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0.1 µF 5.0 V RI+ RI- RO DO+ DO- DI Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community DS8921,DS8921A,DS8921AT SNLS374D – MAY 1998–REVISED JANUARY 2015 DS8921xDifferentialLineDriverandReceiverPair

1 Features 3 Description

The DS8921, DS8921A, and DS8921AT devices are 1• 12-ns Typical Propagation Delay differential line driver and receiver pairs designed• Output Skew: 0.5 ns Typical specifically for applications meeting the ST506,

• Meets the Requirements of EIA Standard RS-422 ST412, and ESDI disk drive standards. In addition, these devices meet the requirements of the EIA• Complementary Driver Outputs standard RS-422.• High Differential or Common-Mode Input Voltage Ranges of ±7 V The DS8921x receivers offer an input sensitivity of 200 mV over a ±7 V common mode operating range.• ±0.2 V Receiver Sensitivity Over the Input Voltage Hysteresis is incorporated (typically 70 mV) toRange improve noise margin for slowly changing input• Receiver Input Hysteresis: 70 mV Typical waveforms.
• DS8921AT Industrial Temperature Operation: The DS8921x drivers are designed to provide(−40°C to +85°C) unipolar differential drive to twisted-pair or parallel wire transmission lines. Complementary outputs are2 Applications logically ANDed and provide an output skew of 0.5 ns (typical) with propagation delays of 12 ns.• Differential Line Driver and Receiver for: – ST506 Disk Drive Standard The DS8921x devices are designed to be compatible with TTL and CMOS.– ST412 Disk Drive Standard – ESDI Disk Drive Standard Device Information(1) – RS-422 Interface PART NUMBER PACKAGE BODY SIZE (NOM) DS8921 SOIC (8) 4.90 mm x 3.91 mm DS8921A PDIP (8) 9.81 mm x 6.35 mmDS8921AT (1) For all available packages, see the orderable addendum at the end of the data sheet. SPACE Typical Application Block Diagram Simplified Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS8921,DS8921A,DS8921AT SNLS374D – MAY 1998– REVISED JANUARY 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (April 2013) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision B (November 2004) to Revision C Page

2 Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated

Product Folder Links: DS8921 DS8921A DS8921AT

DS8921,DS8921A,DS8921AT www.ti.com SNLS374D – MAY 1998– REVISED JANUARY 2015

5 Pin Configuration and Functions

8 Pins

NAME NO. DIFFERENTIAL SIGNALING I/O DI 3 I TTL/CMOS Compatible Driver Input DO+, DO– 6, 5 O Inverting and non-inverting differential driver outputs RI+, RI– 8, 7 I Inverting and non-inverting differential receiver inputs RO 2 O Receiver Output Pin POWER GND 4 Power Ground Pin VCC 1 Power Supply pin, provide 5-V supply

6 Specifications

6.1 Absolute Maximum Ratings(1)(2)

Driver Input Voltage −0.5 7 V Output Voltage 5.5 V Receiver Output Sink Current 50 mA Receiver Input Voltage –10 10 V Differential Input Voltage –12 12 V Maximum Package Power Dissipation at 25°C: D Package 730 mW Maximum Package Power Dissipation at 25°C: P Package 1160 mW Derate D Package, above 25°C 9.3 mW/°C Derate P Package, above 25°C 5.8 mW/°C Lead Temperature 260 °C (Soldering, 4 sec.) 260 °C Maximum Junction Temperature 150 °C Storage Temperature, Tstg −65 165 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the Texas Instrument Sales Office/ Distributors for availability and specifications. Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: DS8921 DS8921A DS8921AT

DS8921,DS8921A,DS8921AT SNLS374D – MAY 1998– REVISED JANUARY 2015 www.ti.com

6.2 ESD Ratings

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±1500 C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Supply Voltage 4.5 5.5 V Temperature (TA): DS8921/DS8921A 0 70 °C Temperature (TA): DS8921AT −40 85 °C

6.4 Electrical Characteristics

Over operating free-air temperature range unless otherwise noted.(1)(2)(3) TEST CONDITIONS MIN TYP MAX UNIT RECEIVER VTH −7 V ≤ VCM ≤ +7 V −200 ±35 +200 mV VHYST −7 V ≤ VCM ≤ +7 V 15 70 mV RIN VIN = −7 V, +7 V, (Other Input = GND) 4.0 6.0 kΩ VIN = 10 V 3.25 mA IIN VIN = −10 V −3.25 mA VOH IOH = −400 μA 2.5 V VOL IOL = 8 mA 0.5 V ISC VCC = MAX, VOUT = 0 V −15 −100 mA DRIVER VIH 2.0 V VIL 0.8 V IIL VCC = MAX, VIN = 0.4 V −40 −200 μA IIH VCC = MAX, VIN = 2.7 V 20 μA II VCC = MAX, VIN = 7.0 V 100 μA VCL VCC = MIN, IIN = −18 mA −1.5 V VOH VCC = MIN, IOH = −20 mA 2.5 V VOL VCC = MIN, IOL = +20 mA 0.5 V IOFF VCC = 0V, V OUT = 5.5 V 100 μA VT 2.0 V |VOS – VOS| 0.4 V ISC VCC = MAX, VOUT = 0 V −30 −150 mA DRIVER AND RECEIVER ICC VCC = MAX, VOUT = Logic 0 35 mA (1) All currents into device pins are shown as positive values; all currents out of the device are shown as negative; all voltages are referenced to ground unless otherwise specified. All values shown as max or min are classified on absolute value basis. (2) All typical values are VCC = 5 V, TA = 25°C. (3) Only one output at a time should be shorted.

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Product Folder Links: DS8921 DS8921A DS8921AT

results assume a linear transition between measurement points and are a result of the following equations: Where: DS8921,DS8921A,DS8921AT www.ti.com SNLS374D – MAY 1998– REVISED JANUARY 2015

6.5 Receiver Switching Characteristics

MAX MAX MAXTEST CONDITIONS MIN TYP UNIT8921 8921A 8921AT tpLH CL = 30 pF 14 22.5 20 20 ns (Figure 3 and Figure 4) tpHL CL = 30 pF 14 22.5 20 20 ns (Figure 3 and Figure 4) |tpLH–t pHL| CL = 30 pF 0.5 5 3.5 5 ns (Figure 3 and Figure 4)

6.6 Driver Switching Characteristics: Single-Ended Characteristics

MAX MAX MAXTEST CONDITIONS MIN TYP UNIT8921 8921A 8921AT tpLH CL = 30 pF 10 15 15 15 ns (Figure 5 and Figure 6) tpHL CL = 30 pF 10 15 15 15 ns (Figure 5 and Figure 6) tTLH CL = 30 pF 5 8 8 9.5 ns (Figure 9 and Figure 10) tTHL CL = 30 pF 5 8 8 9.5 ns (Figure 9 and Figure 10) Skew CL = 30 pF(1) 1 5 3.5 3.5 ns (Figure 5 and Figure 6) (1) Difference between complementary outputs at the 50% point.

6.7 Driver Switching Characteristics: Differential Characteristics(1)

MAX MAX MAXTEST CONDITIONS MIN TYP UNIT8921 8921A 8921AT tpLH CL = 30 pF 10 15 15 15 ns (Figure 5, Figure 7, and Figure 8) tpHL CL = 30 pF 10 15 15 15 ns (Figure 5, Figure 7, and Figure 8) |tpLH–t pHL| CL = 30 pF 0.5 6 2.75 2.75 ns (Figure 5, Figure 7, and Figure 8) (1) Differential Delays are defined as calculated results from single ended rise and fall time measurements. This approach in establishing AC performance specifications has been taken due to limitations of available Automatic Test Equipment (ATE). The calculated ATE Tcr = Crossing Point Tra, Trb, Tfa and T fb are time measurements with respect to the input. See Figure 8. Copyright © 1998–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: DS8921 DS8921A DS8921AT

6.8 Typical Characteristics

Figure 1. Typical Driver Output Low to High Transition Time Figure 2. Typical Driver Output High to Low Transition Time

7 Parameter Measurement Information

7.1 AC Test Circuits and Switching Diagrams

Figure 3. Test Circuit for Receiver Output Figure 4. Receiver Propagation Delay Figure 5. Driver Test Circuit

6 Submit Documentation Feedback Copyright © 1998–2015, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

designed specifically for ST506, ST412, and ESDI disk drive standards, as well as RS-422 interface applications. DS8921AT is rated at an extended temperature range of -40°C to +85°C.

8.2 Functional Block Diagram

8.3 Feature Description

The DS8921x devices each contain a differential driver and receiver. output. The receiver offers an input sensitivity of ±200 mV and supports a common-mode input voltage of ±7 V.

8.4 Device Functional Modes

Table 1. Function Table (1) VID is the input differential voltage between RI+ and RI–.

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9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

links where ground reference difference, or noisy environment are common.

9.2 Typical Application

Figure 11 shows a typical implementation of the DS8921x device in a ST506 and ST412 disk drive application. connected across the input pins of the receiver. Figure 11. ST506 and ST412 Application

9.2.1 Design Requirements

• Apply TTL or LVCMOS signal to driver input at DI
• Transmit complementary outputs at DO+ and DO-
• Receive complimentary input signals at RI+ and RI-
• Receive TTL output signal at RO
• Use controlled-impedance transmission lines such as printed circuit board traces, twisted-pair wires or parallel wire cable
• Place terminating resistor at the far end of the differential pair

9.2.2 Detailed Design Procedure

• Connect VCC and GND pins to the power and ground planes of the printed circuit board, with 0.1-uF bypass capacitor
• Use TTL/LVCMOS logic levels at DI and RO
• Use controlled-impedance transmission media for the differential signals DI+- and RO+-
• Place a terminating resistor at the far-end of the differential pair to avoid reflection
• Ensure the received complimentary signals at RO+ and RO- are within the signal threshold of ±200 mV

9.2.3 Application Curves

Figure 12. Driver Single-Ended Input Signal Figure 13. Driver Differential Output Signal

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Figure 14. Receiver Differential Input Signal Figure 15. Receiver Single-Ended Output Signal

10 Power Supply Recommendations

11 Layout

11.1 Layout Guidelines

same as the differential impedance of the transmission line to minimize reflections. It is preferable to connect the VCC and GND pins to the power and ground planes using plated-through-holes. Additionally, a 0.1-µF bypass capacitor should be placed close to the VCC pin across VCC and GND. routed with uniform trace width and spacing to minimize impedance mismatch.

11.2 Layout Example

Figure 16. DS8921 Example Layout

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12 Device and Documentation Support

12.1 Related Links

resources, tools and software, and quick access to sample or buy. Table 2. Related Links

12.2 Trademarks

All trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS8921AM/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM 0 to 70 DS89 21AM DS8921AM/NOPB.B Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 DS89 21AM DS8921AMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM 0 to 70 DS89 21AM DS8921AMX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 DS89 21AM DS8921ATM/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 DS892 1ATM DS8921ATM/NOPB.B Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 DS892 1ATM DS8921ATMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 DS892 1ATM DS8921ATMX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 DS892 1ATM DS8921M/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM 0 to 70 DS892 DS8921M/NOPB.B Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 85 DS892 DS8921MX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM 0 to 70 DS892 DS8921MX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 DS892 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. Addendum-Page 1

www.ti.com 23-May-2025 (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS8921AMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 DS8921ATMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 DS8921MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DS8921AM/NOPB D SOIC 8 95 495 8 4064 3.05 DS8921AM/NOPB.B D SOIC 8 95 495 8 4064 3.05 DS8921ATM/NOPB D SOIC 8 95 495 8 4064 3.05 DS8921ATM/NOPB.B D SOIC 8 95 495 8 4064 3.05 DS8921M/NOPB D SOIC 8 95 495 8 4064 3.05 DS8921M/NOPB.B D SOIC 8 95 495 8 4064 3.05 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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