DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 10

Technical content

Features

Y Uses inexpensive 3.96 MHz reference crystal Y FIN capability greater than 120 MHz allows direct syn- thesis at FM frequencies Y FM resolution of either 10 kHz or 20 kHz allows usage of 10.7 MHz ceramic filter distribution Y Serial data entry for simplified control Y 50 Hz output for time-of-day reference driven from sep- arate low power V CCM Y 2 open collector buffered outputs for controlling various radio functions or loop gain Y Separate AM and FM inputs; AM input has 15 mV (typi- cal) hysteresis Y Programmable charge pump current sources enable ad- justment of system loop gain Y Operational amplifier provides high impedance load to charge pump output and a wide voltage range for the VCO input Connection Diagram Dual-In-Line Package TL/F/5111 1 Top View Order Number DS8908BN See NS Package Number N20A TRI STATE É is a registered trademark of National Semiconductor Corp C1995 National Semiconductor Corporation RRD B30M105/Printed in U S A

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage CC1)( V CCM)7 V (VCC2) 17V Input Voltage 7V Output Voltage 7V Storage Temperature Range b65§Ct o a150§C Lead Temperature (Soldering, 4 seconds) 260 §C Operating Conditions Min Max Units VCC1 4.5 5.5 V VCC2 VCC1 a 1.5 15.0 V VCCM 3.5 5.5 V Temperature, T A b40 a85 §C Symbol Parameter Conditions Min Typ Max Units VIH Logical ‘‘1’’ Input Voltage 2.0 V IIH Logical ‘‘1’’ Input Current V IN 2.7V 0 10 mA VIL Logical ‘‘0’’ Input Voltage 0.8 V IIL Logical ‘‘0’’ Input Current Data, Clock, and ENABLE Inputs, V IN 0V b5 b25 mA IOH Logical ‘‘1’’ Output Current VOH 5.5V 50 mAAll Bit Outputs, 50 Hz Output 1.98 MHz Output VOH 2.4V, V CCM 4.5V b250 mA VOL Logical ‘‘0’’ Output Voltage IOL 5 mA 0.5 VAll Bit Outputs 50 Hz Output, 1.98 MHz Output I OL 250 mA 0.5 V 1.98 MHz Output IOL 20 mA, T A l 70§C 0.3 V IOL 20 mA, T A s 70§C 0.4 V ICC1 Supply Current (V CC1) All Bit Outputs High 160 mA ICCM VCCM Supply Current VCCM 5.5V, All Other Pins Open 2.5 4.0 mA IOUT Charge Pump Ougtput Current 3.33k s RPROG s 33.3k Pump Up b20 I PROG a20 % IOUT Measured between Pump Down b20 I PROG a20 %Pin 17 and Pin 18 TRI-STATEÉ 01 1 n AIPROG VCC1/2 R PROG ICC2 VCC2 Supply Current VCCM 5V, V CC1 5.5V, V CC2 15V 6.7 11 mA All Other Pins Open OPVOH Op Amp Minimum High Level V CC1 4.5V, I OH b750 mAV CC2 b0.4 V OPVOL Op Amp Maximum Low Level V CC1 5.5V, I OL 750 mA 0.6 V CPOBIAS Charge Pump Bias Voltage CPO Shorted to Op Amp Output Delta CPO TRI-STATE 100 mV Op Amp I OL: 750 mAv s b750 mA Symbol Parameter Conditions Min Typ Max Units VIN(MIN)(F) FIN Minimum Signal Input AM and FM Inputs, b40§C s TA s 85§C 20 100 mV(rms) VIN(MAX)(F) FIN Maximum Signal Input AM and FM Inputs, b40§C s TA s 85§C 1000 1500 mV(rms) FOPERATE Operating Frequency Range V IN 100 mV rms AM 0.5 15 MHz (Sine Wave Input) b40§C s TA s 85§C FM 80 120 MHz RIN(FM) AC Input Resistance, FM 120 MHz, V IN 100 mV rms 600 X RIN(AM) AC Input Resistance, AM 15 MHz, V IN 100 mV rms 1000 X CIN Input Capacitance, FM and AM V IN 120 MHz (FM), 15 MHz (AM) 3 6 10 pF tEN1 Minimum ENABLE High 625 1250 nsPulse Width

Symbol Parameter Conditions Min Typ Max Units tEN0 Minimum ENABLE Low 375 750 nsPulse Width tCLKEN0 Minimum Time before ENABLE Goes Low That CLOCK Must b50 0 ns Be Low tEN0CLK Minimum Time after ENABLE Goes Low That CLOCK Must 275 550 ns Remain Low tCLKEN1 Minimum Time before ENABLE Goes High That Last Positive 300 600 ns CLOCK Edge May Occur tEN1CLK Minimum Time after ENABLE Goes High before an Unused 175 350 ns Positive CLOCK Edge May Occur tCLKH Minimum CLOCK High 275 550 nsPulse Width tCLKL Minimum CLOCK Low 400 800 nsPulse Width tDS Minimum DATA Set-Up Time, Minimum Time before CLOCK 150 300 ns That DATA Must Be Valid tDH Minimum DATA Hold Time, Minimum Time after CLOCK 400 800 ns That DATA Must Remain Valid Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Unless otherwise specified min/max limits apply across the 40§Ct o a85§C temperature range for the DS8908B. Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltage referenced to ground unless otherwise noted. All values shown as max or min on absolute value basis. Schematic Diagrams (DS8908B AM/FM PLL Typical Input/Output Schematics) TL/F/5111 4 TL/F/5111 2 TL/F/5111 3

Schematic Diagrams (Continued) TL/F/5111 6 TL/F/5111 7 TL/F/5111 5 TL/F/5111 8

Schematic Diagrams (Continued) TL/F/5111 9 Timing Diagrams* ENABLE vs CLOCK TL/F/5111 10 CLOCK vs DATA TL/F/5111 11

Timing Diagrams* (Continued) AM/FM Frequency Synthesizer (Scan Mode) TL/F/5111 12 *Timing diagrams are not drawn to scale. Scale within any one drawing may not be consistent, and intervals are defined positive as drawn. SERIAL DATA ENTRY INTO THE DS8908B Serial information entry into the DS8908B is enabled by a low level on the ENABLE input. One binary bit is then ac- cepted from the DATA input with each positive transition of the CLOCK input. The CLOCK input must be low for the specified time preceding and following the negative tran- sition of the ENABLE input. The first two bits accepted following the negative transition of the ENABLE input are interpreted as address. If these address bits are not 1,1 no further information will be ac- cepted fromt he DATA inputs, and the internal data latches will not be changed when ENABLE returns high. If these first two bits are 1,1, then all succeeding bits are accepted as data, and are shifted successively into the in- ternal shift register as long as ENABLE remains low. Any data bits preceding the 19th to last bit will be shifted out, and thus are irrelevant. Data bits are counted as any bits following two valid address bits (1,1) with the ENABLE low. When the ENABLE input returns high, any further serial data entry is inhibited. Upon this positive transition, the data in the internal shift register is transferred into the internal data latches. Note that until this time, the states of the inter- nal data latches have remained unchanged. These data bits are interpreted as follows: Data Bit Position Data Interpretation Last Bit 19 Output (Pin 2) 2nd to Last Bit 18 Output (Pin 1) 3rd to Last Ref. Freq. Select Bit (1)17 4th to Last Ref. Freq. Select Bit (1)16 5th to Last AM/FM Select Bit 15 6th to Last (2 13) 7th to Last (2 12) 8th to Last (2 11) 9th to Last (2 10) 10th to Last (2 9) 11th to Last (2 8) 12th to Last (2 7) dN(2) 13th to Last (26) 14th to Last (2 5) 15th to Last (2 4) 16th to Last (2 3) 17th to Last (2 2) 18th to Last (2 1) 19th to Last LSB of dN(20) - Note 1: See Reference Frequency Select Truth Table. Note 2: The actual divide code is N a1, ie., the number loaded plus 1. Truth Table Reference Frequency Selection Truth Table Serial Data Reference Frequency Bit 16 Bit 17 (kHz) 11 2 0 10 1 0 01 9 00 1

Typical Application Additional application notes are located at the back of section 11. Electronically Tuned Radio Controller System; Direct Drive LED TL/F/5111 13

AM/FM PLL/Synthesizer (Serial Data 20-Pin Package) *Sections operating from V CCM supply. **Address (1,1) TL/F/5111–14

DS8908B AM/FM Digital Phase-Locked Loop Frequency Synthesizer Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number DS8908BN LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

1111 West Bardin Road Fax: ( a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309

Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: ( a49) 0-180-530 85 85 Tsimshatsui, Kowloon Fax: 1(800) 737-7018 English Tel: ( a49) 0-180-532 78 32 Hong Kong Fran3ais Tel: ( a49) 0-180-532 93 58 Tel: (852) 2737-1600 Italiano Tel: ( a49) 0-180-534 16 80 Fax: (852) 2736-9960 National does not assume any respons bility for use of any circuitry described, no circuit patent l censes are implied and National reserves the right at any t me without notice to change said circuitry and specificat ons