DS8906

DS8906 NSC | Alldatasheet

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Y Uses inexpensive 4 MHz reference crystal Y FIN capability greater than 120 MHz allows direct syn- thesis at FM frequencies Y FM resolution of 12.5 kHz allows usage of 10.7 MHz ceramic filter distribution Y Serial data entry for simplified control Y 50 Hz output for ‘‘time-of-day’’ reference with separate low power supply (V CCM) Y 6-open collector buffered outputs for band switching and other radio functions Y Separate AM and FM inputs. AM input has 15 mV (typi- cal) hysteresis Connection Diagram Dual-In-Line Package TL/F/5775–1 Top View Order Number DS8906N See NS Package Number N20A TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage CC1)7 V (VCCM)7 V Input Voltage 7V Output Voltage 7V Storage Temperature Range b65§Ct o a150§C Lead Temperature (Soldering, 4 seconds) 260 §C Operating Conditions Min Max Units Supply Voltage, V CC VCC1 4.75 5.25 V VCCM 4.5 6.0 V Temperature, T A 07 0 §C Symbol Parameter Conditions Min Typ Max Units VIH Logical ‘‘1’’ Input Voltage 2.1 V IIH Logical ‘‘1’’ Input Current V INeVCC1 01 0 mA VIL Logical ‘‘0’’ Input Voltage 0.7 V IIL Logical ‘‘0’’ Input Current Data, Clock and ENABLE INPUTS, V INe0V b5 b25 mA IOH Logical ‘‘1’’ Output Current 50 mAAll Bit Outputs, 50 Hz Output V OHe5.25V 500 kHz Output V OHe2.4V, V CCMe4.5V b250 mA VOL Logical ‘‘0’’ Output Voltage 0.5 VAll Bit Outputs I OLe5m A 50 Hz Output, 500 kHz Output I OLe250 mA b0.5 V ICC1 Supply Current (V CC1) All Bit Outputs High 90 160 mA ICCM(STANDBY) VCCM Supply Current V CCMe6.0V, All Other Pins Open 1.5 4.0 mA VCCMs6.0V Pump Down 0.10 0.30 0.6 mA TRI-STATEÉ 0 g100 nA ICCM(OPERATE) VCCM Supply Current V CCMe6.0V, V CC1e5.25V, 2.5 6.0 mAAll Other Pins Open Symbol Parameter Conditions Min Typ Max Units VIN(MIN)(F) FIN Minimum Signal Input AM and FM Inputs, 0 §C s TA s 70§C 20 100 mV (rms) VIN(MAX)(F) FIN Maximum Signal Input AM and FM Inputs, 0 §C s TA s 70§C 1000 1500 mV (rms) FOPERATE Operating Frequency Range V IN e 100 mV rms AM 0.4 8 MHz (Sine Wave Input) 0 §C s TA s 70§C FM 60 120 MHz RIN (FM) AC Input Resistance, FM 120 MHz, V IN e 100 mV rms 300 X RIN (AM) AC Input Resistance, AM 2 MHz, V IN e 100 mV rms 1000 X CIN Input Capacitance, FM and AM V IN e 120 MHz 3 6 10 pF tEN1 Minimum ENABLE High 625 1250 nsPulse Width tEN0 Minimum ENABLE Low 375 750 nsPulse Width tCLKEN0 Minimum Time before ENABLE Goes Low that CLOCK must b50 0 ns be Low tEN0CLK Minimum Time after ENABLE Goes Low that CLOCK must 275 550 ns Remain Low tCLKEN1 Minimum Time before ENABLE Goes High that Last Positive 300 600 ns CLOCK Edge May Occur

Symbol Parameter Conditions Min Typ Max Units tEN1CLK Minimum Time After ENABLE Goes High Before an Unused 175 350 ns Positive CLOCK Edge May Occur tCLKH Minimum CLOCK High 275 550 nsPulse Width tCLKL Minimum CLOCK Low 400 800 nsPulse Width tDS Minimum DATA Setup Time, Minimum Time Before CLOCK 150 300 ns that DATA Must be Valid tDH Minimum DATA Hold Time, Minimum Time After CLOCK 400 800 ns that DATA Must Remain Valid Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Unless otherwise specified min/max limits apply across the 0 §Ct o a70§C temperature range for the DS8906. Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as max or min on absolute value basis. Schematic Diagrams (DS8906 AM/FM PLL Typical Input/Output Schematics) TL/F/5775–2 TL/F/5775–3 TL/F/5775–4 TL/F/5775–5 TL/F/5775–6

Schematic Diagrams (DS8906 AM/FM PLL Typical Input/Output Schematics) (Continued) TL/F/5775–7 TL/F/5775–8 Timing Diagrams * ENABLE vs CLOCK TL/F/5775–9 CLOCK vs DATA TL/F/5775–10 AM/FM Frequency Synthesizer (Scan Mode) *Timing diagrams are not drawn to scale. Scale within any one drawing may not be consistent, and intervals are defined positive as drawn. TL/F/5775–11

SERIAL DATA ENTRY INTO THE DS8906 Serial information entry into the DS8906 is enabled by a low level on the ENABLE input. One binary bit is then accepted from the DATA input with each positive transition of the CLOCK input. The CLOCK input must be low for the speci- fied time preceding and following the negative transition of the ENABLE input. The first 2 bits accepted following the negative transition of the ENABLE input are interpreted as address. If these ad- dress bits are not 1,1, no further information will be accept- ed from the DATA inputs, and the internal data latches will not be changed when ENABLE returns high. If these first 2 bits are 1,1, then all succeeding bits are ac- cepted as data, and are shifted successively into the inter- nal shift register as long as ENABLE remains low. Any data bits preceding the 20th to last bit will be shifted out, and are thus irrelevant. Data bits are counted as any bits following 2 valid (1,1) address bits with the ENABLE low. When the ENABLE input returns high, any further serial data input is inhibited. Upon this positive transition of the ENABLE , the data in the internal shift register is transferred into the internal data latches. Note that until this time, the states of the internal data latch- es have remained unchanged. These data bits are interpreted as follows: DATA BIT POSITION DATA INTERPRETATION Last Bit 20 Output (Pin 2) 2nd to Last Bit 19 Output (Pin 1) 3rd to Last Bit 18 Output (FM/AM ) (Pin 20) 4th to Last Bit 17 Output (Pin 19) 5th to Last Bit 16 Output (Pin 18) 6th to Last Bit 15 Output (Pin 17) 7th to Last MSB of N (2 13) 8th to Last (2 12) 9th to Last (2 11) 10th to Last (2 10) 11th to Last (2 9) 12th to Last (2 8) 13th to Last dN(27) 14th to Last (2 6) 15th to Last (2 5) 16th to Last (2 4) 17th to Last (2 3) 18th to Last (2 2) 19th to Last (2 1) 20th to Last LSB of N (2 0) - Note. The actual divide code is N a1, i.e., the number loaded plus 1.

Electronically Tuned Radio Controller System; Direct Drive LED TL/F/5775–12

TL/F/5775–13 *Sections operating from V CCM supply **Address (1, 1)

DS8906 AM/FM Digital Phase-Locked Loop Synthesizer Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number DS8906N LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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