DS8830

DS8830 TI | Alldatasheet

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DS8830, SN55183, SN75183 DUAL DIFFERENTIAL LINE DRIVERS SLLS093D – OCTOBER 1972 – REVISED APRIL 1998 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Single 5-V Supply /C0068Differential Line Operation /C0068Dual Channels /C0068TTL Compatibility /C0068Short-Circuit Protection of Outputs /C0068Output Clamp Diodes to Terminate Line Transients /C0068High-Current Outputs /C0068Quad Inputs /C0068Single-Ended or Differential AND/NAND Outputs /C0068Designed for Use With Dual Differential Drivers SN55182 and SN75182 /C0068Designed to Be Interchangeable With National Semiconductor DS7830 and DS8830

description

The DS8830, SN55183, and SN75183 dual differential line drivers are designed to provide differential output signals with high current capability for driving balanced lines, such as twisted pair, at normal line impedances without high power dissipation. These devices can be used as TTL expander/phase splitters, because the output stages are similar to TTL totem-pole outputs. The driver is of monolithic single-chip construction, and both halves of the dual circuits use common power supply and ground terminals. The SN55183 is characterized for operation over the full military temperature range of –55°C to 125°C. The DS8830 and SN75183 are characterized for operation from 0°C to 70°C. Copyright  1998, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. GND VCC SN55183 ...J O R W PACKAGE SN75183 ...D O R N PACKAGE DS8830 ... N PACKAGE (TOP VIEW) 3 2 1 20 19 91 01 11 2 1 3 NC NC NC NC SN55183 . . . FK PACKAGE (TOP VIEW)1B NC 2Y 2D GND NC CCV THE DS8830 AND SN55183 ARE NOT RECOMMENDED FOR NEW DESIGNS NC – No internal connection

DS8830, SN55183, SN75183 DUAL DIFFERENTIAL LINE DRIVERS SLLS093D – OCTOBER 1972 – REVISED APRIL 1998

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logic symbol† † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, and W packages. logic diagram (positive logic) Pin numbers shown are for the D, J, N, and W packages. Positive logic: y = ABCD, Z = ABCD

DS8830, SN55183, SN75183 DUAL DIFFERENTIAL LINE DRIVERS SLLS093D – OCTOBER 1972 – REVISED APRIL 1998 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 schematic (each driver) A B C D 4 kΩ 3.2 kΩ GND Y 9 Ω 300 Ω Z VCC 3 kΩ 545 Ω 2 kΩ 545 Ω 3 kΩ 300 Ω2 kΩ 9 Ω V V 1, 10 2, 11 3, 12 4, 13 6, 8 5, 9 Resistor values shown are nominal. Pin numbers shown are for the D, J, N, and W packages.

DS8830, SN55183, SN75183 DUAL DIFFERENTIAL LINE DRIVERS SLLS093D – OCTOBER 1972 – REVISED APRIL 1998

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to network ground terminal. 2. Not more than one output should be shorted to ground at any one time. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING TA = 125°C POWER RATING D 950 mW 7.6 mW/°C 608 mW – FK ‡ 1375 mW 11.0 mW/ °C 880 mW 275 mW J‡ 1375 mW 11.0 mW/ °C 880 mW 275 mW N 1150 mW 9.2 mW/ °C 736 mW – W ‡ 1000 mW 8.0 mW/°C 640 mW 200 mW ‡ In the FK, J, and W packages, SN55183 chips are alloy mounted and SN75183 chips are glass mounted. recommended operating conditions SN55183 DS8830, SN75183 UNIT MIN NOM MAX MIN NOM MAX Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V High-level input voltage, VIH 2 2 V Low-level input voltage, VIL 0.8 0.8 V High-level output current, IOH –40 –40 mA Low-level output current, IOL 40 40 mA Operating free-air temperature, TA –55 125 0 70 °C

DS8830, SN55183, SN75183 DUAL DIFFERENTIAL LINE DRIVERS SLLS093D – OCTOBER 1972 – REVISED APRIL 1998 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended ranges of VCC and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High level output voltageY (AND) outputs VIH =2V IOH = –0.8 mA 2.4 VVOH High-level output voltage Y (AND) outputs VIH = 2 V IOH = –40 mA 1.8 3.3 V VOL Low level output voltage Y (AND) outputs VIL=08V IOL = 32 mA 0.2 VVOL Low-level output voltage Y (AND) outputs VIL = 0.8 V IOL = 40 mA 0.22 0.4 V VOH High level output voltageZ (NAND) outputs VIL=08V IOH = –0.8 mA 2.4 VVOH High-level output voltage Z (NAND) outputs VIL = 0.8 V IOH = –40 mA 1.8 3.3 V VOL Low level output voltage Z (NAND) outputs VIH =2V IOL = 32 mA 0.2 VVOL Low-level output voltage Z (NAND) outputs VIH = 2 V IOL = 40 mA 0.22 0.4 V IIH High-level input current VIH = 2.4 V 120 µA II Input current at maximum input voltage VIH = 5.5 V 2 mA IIL Low-level input current VIL = 0.4 V –4.8 mA IOS Short-circuit output current‡ VCC = 5 V, TA =125°C § –40 –100 –120 mA ICC Supply current (average per driver) VCC = 5 V, All inputs at 5 V,No load 10 18 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second. § TA = 125°C is applicable to SN55183 only. switching characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low- to high-level Y outputAND gates C L = 15 pF, See FIgure 1(a) 8 12 ns tPHL Propagation delay time, high- to low-level Y outputAND gates C L = 15 pF, See FIgure 1(a) 12 18 ns tPLH Propagation delay time, low- to high-level Z outputNAND gates C L = 15 pF, See FIgure 1(a) 6 12 ns tPHL Propagation delay time, high- to low-level Z outputNAND gates C L = 15 pF, See FIgure 1(a) 6 8 ns tPLH Propagation delay time, low- to high-level differential output Y output with respect to Z output, R L = 100 Ω in series with 5000 pF, See Figure 1(b) 9 16 ns tPHL Propagation delay time, high- to low-level differential output Y output with respect to Z output, R L = 100 Ω in series with 5000 pF, See Figure 1(b) 8 16 ns

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1.5 VInput

NOTES: A. The pulse generators have the following characteristics: ZO = 50 Ω , tr ≤ 10 ns, tf ≤ 10 ns, tw = 0.5 µs, PRR ≤ 1 MHz. B. C L includes probe and jig capacitance. C. Waveforms are monitored on an oscilloscope with ri ≥ 1 MΩ . Figure 1. Test Circuits and Voltage Waveforms

DS8830, SN55183, SN75183 DUAL DIFFERENTIAL LINE DRIVERS SLLS093D – OCTOBER 1972 – REVISED APRIL 1998

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TYPICAL CHARACTERISTICS † Figure 6 TA – Free-Air Temperature – °C – Propagation Delay Time – ns PROPAGATION DELAY TIME (DIFFERENTIAL OUTPUT) vs FREE-AIR TEMPERATURE ÏÏÏÏÏÏ ÏÏÏÏÏÏ VCC = 5 V See Figure 1(b) ÏÏÏ ÏÏÏ tPHL ÏÏÏ ÏÏÏ tPLH tpd –50 –25 0 25 125–75 100 7550 Figure 7 – Total Power Dissipation – mW TOTAL POWER DISSIPATION (BOTH DRIVERS) vs FREQUENCY f – Frequency – MHz ÁÁ ÁÁ ÁÁ PD ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ VCC = 5 V No Load Input: 3-V Square Wave TA = 25°C 240 220 200 180 160 140 120 100 0.1 1 0.4 4 10 40 100 † Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.

DS8830, SN55183, SN75183 DUAL DIFFERENTIAL LINE DRIVERS SLLS093D – OCTOBER 1972 – REVISED APRIL 1998 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

(see Note B)Noninverting Input Strobe 0.002 µF (see Note A) 1/2 ’182 VCC = 5 V GND Y Z GND VCC = 5 V 1/2 ’183 Inputs D C B A R T NOTES: A. When the inputs are open circuited, the output is high. A capacitor may be used for dc isolation of the line-terminating resistor. At the frequency of operation, the impedance of the capacitor should be relatively small. B. Use of a capacitor to control response time is optional. Example: let f = 5 MHz C = 0.002 µF Z(circuit) /C009116/C0087 Z(circuit) /C00431 2/C0112fC /C0043 1 2/C0112/C04665 /C0032106/C0467/C04660.002/C003210/C00426/C0467 Inverting Input Figure 8. Transmission of Digital Data Over Twisted-Pair Line

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 7900901CA ACTIVE CDIP J 14 1 None A42 SNPB Level-NC-NC-NC 7900901DA ACTIVE CFP W 14 1 None A42 SNPB Level-NC-NC-NC DS8830N OBSOLETE PDIP N 14 None Call TI Call TI SN55183J ACTIVE CDIP J 14 1 None A42 SNPB Level-NC-NC-NC SN75183D ACTIVE SOIC D 14 50 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN75183DR ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN75183N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN75183NSR ACTIVE SO NS 14 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SNJ55183FK ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC SNJ55183J ACTIVE CDIP J 14 1 None A42 SNPB Level-NC-NC-NC SNJ55183W ACTIVE CFP W 14 1 None A42 SNPB Level-NC-NC-NC (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 4-Mar-2005 Addendum-Page 1

MLCC006B – OCTOBER 1996 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 4040140/D 10/96

28 TERMINAL SHOWN

B 0.358 (9,09) MAX (11,63) 0.560 (14,22) 0.560 0.458 0.858 (21,8) 1.063 (27,0) (14,22) ANO. OF MINMAX 0.358 0.660 0.761 0.458 0.342 (8,69) MIN (11,23) (16,26) 0.640 0.739 0.442 (9,09) (11,63) (16,76) 0.962 1.165 (23,83) 0.938 (28,99) 1.141 (24,43) (29,59) (19,32)(18,78) 0.020 (0,51) TERMINALS 0.080 (2,03) 0.064 (1,63) (7,80) 0.307 (10,31) 0.406 (12,58) 0.495 (12,58) 0.495 (21,6) 0.850 (26,6) 1.047 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.035 (0,89) 0.010 (0,25) 121314151618 17 432 0.020 (0,51) 0.010 (0,25) 12826 27 B SQ A SQ 0.055 (1,40) 0.045 (1,14) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

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