DS8102

DS8102 MAXIM | Alldatasheet

Document overview

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Technical content

Features

♦ Dual Delta-Sigma 2nd-Order Modulators Channel 0: Pin-Selectable Gain of 1x, 4x, 16x, or 32x Channel 1: Fixed Gain of 1x ♦ Selectable Internal or External Voltage Reference ♦ Manchester-Encoded Bit Stream Output Includes Synchronization Bits to Allow Clock Recovery Single-Pin Transmission Scheme Simplifies Electrical Isolation Using Capacitive Coupling ♦ Selectable Internal or External Clock Source ♦ Integrated Low-Power 8MHz Oscillator ♦ Operating Mode Active Mode (8MHz, VDD = 3.6V): 3.5mA DS8102 Dual Delta-Sigma Modulator and Encoder TOP VIEW TSSOP

134 MNOUTAN1-

143 RSTVREF

152 APDREFAGND

107 G0AN0+

116 G1AN0-

98 CLKSELVDD

125 CLKIOAN1+

Ordering Information

Rev 1; 2/09 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. +Denotes a lead(Pb)-free/RoHS-compliant package. PART TEMP RANGE PIN-PACKAGE DS8102+ -40 °C to +85°C 16 TSSOP Typical Operating Circuit appears at end of data sheet. MAXQ is a registered trademark of Maxim Integrated Products, Inc.

Dual Delta-Sigma Modulator and Encoder ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD = 2.7V to 3.6V, TA = -40°C to +85°C, f CLK = 8MHz, VREF = internal, OSR = 128, unless otherwise noted.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on Any Pin Relative to DGND Voltage Range on AN0+, AN0-, AN1+, and AN1- J-STD-020 Specification. PARAMETER SYMBOL CONDITIONS MIN TYP (Note 2) MAX UNITS Supply Voltage V DD V RST 3.3 3.6 V Power-Fail Reset Voltage V RST Monitors V DD 2.7 2.8 2.99 V Active V DD Current I DD Normal operation 3.5 5.0 mA Shutdown (Power-Down) VDD Current ISTOP RST = 0 or V DD < VRST 2 nA Input Low Voltage V IL DGND 0.3 x V DD V Input High Voltage V IH 0.7 x V DD V DD V Output Low Voltage (CLKIO, MNOUT) VOL I OL = 4mA DGND 0.4 V Output High Voltage (CLKIO, MNOUT) VOH I OH = -4mA V DD - 0.4 V Input/Output Pin Capacitance C IO (Note 3) 15 pF Input Leakage Current (All Inputs) I L -100 +100 nA CLOCK SOURCE External Clock Input Frequency f XCLK CLKSEL = 1 DC 8 MHz External Clock Input Period t XCLK-CLCL CLKSEL = 1 125 ns External Clock Input Duty Cycle t XCLK-DUTY CLKSEL = 1 40 60 % Internal Oscillator Output Frequency fICLK CLKSEL = 0 7.5 8.0 8.5 MHz Internal Oscillator Output Duty Cycle tICLK-DUTY CLKSEL = 0 47.8 49.1 49.7 % ANALOG-TO-DIGITAL CONVERTER AFE Warmup Delay t WU1 f ICLK = 8MHz (Notes 1, 4) 1.02 ms Reference Buffer Warmup Delay t WU2 f ICLK = 8MHz (Notes 1, 5) 7.17 ms OSR = 32 16 OSR = 64 19 OSR = 128 22 Decimator Output (Note 6) OSR = 256 24 Bits Integral Nonlinearity INL (Notes 1, 6) ±0.01 %FSR Offset Error Gain = 1 (Note 6) 1.4 mV

Dual Delta-Sigma Modulator and Encoder ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 3.6V, TA = -40°C to +85°C, f CLK = 8MHz, VREF = internal, OSR = 128, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP (Note 2) MAX UNITS ANALOG-TO-DIGITAL CONVERTER DYNAMIC SPECIFICATIONS DC Power-Supply Rejection Ratio PSRR VDD = 3.0V to 3.6V, AN0+ = AN0- = AGND, 100mV ripple on VDD 95 dB VDD = 3.6V, gain = 1, AN0 = 500mV P-P, sinewave at 62.5Hz 70 85 Signal-to-Noise Ratio SINAD VDD = 3.6V, gain = 32, AN0 = 20mV P-P, sinewave at 62.5Hz 70 85 dB Total Harmonic Distortion (to 21st Harmonic) THD VDD = 3.6V, gain = 32, AN0 = 20mV P-P, sinewave at 62.5Hz -95 -70 dB ANALOG-TO-DIGITAL CONVERTER INPUTS Input Voltage Range AN0+, AN0-, AN1+, and AN1- to AGND -1 +1 V Gain = 1 1 Gain = 4 4 Gain = 16 16 Input Sampling Capacitance (Note 1) CIN Gain = 32 32 pF Input Sampling Rate f S Clock at 8MHz (Note 7) 0.667 MHz Gain = 1 750 Gain = 4 187 Gain = 16 47 Input Impedance to AGND for 8MHz (Note 8) Gain = 32 23.4 k Gain = 1 1500 Gain = 4 375 Gain = 16 94 Differential Input Impedance for 8MHz (Note 9) Gain = 32 46.9 k Input Bandwidth (-3dB) 7 kHz External Reference Input Voltage V REF 1.2 1.25 1.3 V External Reference Input Sampling Capacitance 2 pF Reference Input Sampling Rate f S 0.67 1 MHz INTERNAL REFERENCE Reference Output Voltage 1.24 V Reference Output Temperature Coefficient ±30 ppm/°C Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: Typical values are not guaranteed. These values are measured at room temperature, VDD = 3.3V. Note 3: These numbers are guaranteed by design and are not tested. Note 4: Calculated as tWU1 = 1/fICLK x 8192. Note 5: Calculated as tWU2 = 1/fICLK x 57,344. Note 6: Parameter specifications are based upon the presence of an external cubic sinc filter (as implemented in the MAXQ3108) for generating full ADC output codewords. Note 7: fS = fCLK/12. fCLK is the system clock frequency. Note 8: This is a function of input sampling capacitance (CIN) and sampling frequency, and can be approximated as 6/(fCLK x CIN). Note 9: ZIN (differential) = 2 x ZIN (single-ended).

Dual Delta-Sigma Modulator and Encoder Pin Description PIN NAME FUNCTION

1 DGND Digital Ground

2 AGND Analog Ground

3 V REF

Reference Voltage Input/Output. When APDREF = 0, the buffered internal voltage reference is driven on this pin as an output and can be used by other devices. When APDREF = 1, an external voltage reference must be provided on this pin.

4 AN1- Negative Input for Differential Analog Input Channel 1

5 AN1+ Positive Input for Differential Analog Input Channel 1

6 AN0- Negative Input for Differential Analog Input Channel 0

7 AN0+ Positive Input for Differential Analog Input Channel 0

8, 16 V DD Digital and Analog Power Supply

9 CLKSEL

Clock Select Input. When CLKSEL = 0, the DS8102 uses its internal 8MHz oscillator as a clock source. When CLKSEL = 1, the DS8102 operates from an external clock source (which must be provided at CLKIO). 10 G0 Gain Select Input 0. This pin, along with G1, is used to select the gain setting for differential analog input channel 0. 11 G1 Gain Select Input 1. This pin, along with G0, is used to select the gain setting for differential analog input channel 0.

12 CLKIO

Clock Input/Output. When CLKSEL = 0 (internal clock selected), the internal 8MHz clock is output on this pin and can be used by external devices. When CLKSEL = 1 (external clock selected), an external clock must be provided on this pin. 13 MNOUT Manchester Encoder Output. This output pin provides a Manchester-encoded bit stream containing output bits from both modulators interleaved with an alternating synchronization bit.

14 RST

Reset. This input pin can be used to force the DS8102 into a shutdown (low-power) state by driving RST = 0. If the external reset function is not used, this pin must be connected to V DD for proper operation. An RC circuit is not required on this pin for power-up, as this function is provided internally.

15 APDREF

Analog Power-Down Reference. This input pin controls whether the internal voltage reference is enabled. If APDREF = 0, the internal voltage reference is enabled and the voltage reference level is driven out on V REF. If APDREF = 1, the internal voltage reference is disabled and an external voltage reference must be provided on V REF.

Dual Delta-Sigma Modulator and Encoder Detailed Description Operating Modes The DS8102 has two operating modes: shutdown (or power-down) mode and active mode. Shutdown Mode In shutdown mode, the DS8102 is in an inactive state and consumes a minimal amount of current. No analog- to-digital conversion or encoding is performed, and the internal 8MHz oscillator and internal voltage reference are disabled. An integrated power-supply monitor holds the DS8102 in shutdown mode whenever V DD ≤ VRST. Additionally, the RST pin can be driven low by an external compan- ion microcontroller (such as the MAXQ3108) to force the DS8102 to remain in shutdown mode, regardless of the supply level at V DD. This is useful in nonisolated config- urations (when a power supply is shared between the DS8102 and the companion microcontroller) to reduce the current consumption of the entire system. In this scenario, the companion microcontroller would perform this sequence of actions when entering stop mode: 1) Drive the RST line on the DS8102 low to force the DS8102 into shutdown mode. 2) Enter stop mode. Both the companion microcon- troller and the DS8102 are now in their lowest cur- rent consumption modes. 3) Exit stop mode. 4) Drive the RST line on the DS8102 high to return the DS8102 to active mode. Note: The RST line on the DS8102 does not include a pullup. This means that if the RST line is not dri- ven by a companion microcontroller, RST must be connected to V DD for proper operation. RST cannot be left unconnected. While the DS8102 is in shutdown mode, the levels on the configuration input pins (APDREF, CLKSEL, G1, and G0) can be changed if they are being driven by a companion microcontroller instead of hardwired to V DD or DGND. However, once the DS8102 enters active mode, the levels on these pins must remain static for proper operation. Functional Diagram DS8102 INTEGRATORS/ COMPARATOR REFERENCE BUFFER DELTA-SIGMA MODULATOR APDREF VREF AN1+ MNOUT AN1- MANCHESTER ENCODER POWER MONITOR 8MHz OSCILLATOR INTERNAL REFERENCE INTEGRATORS/ COMPARATOR DELTA-SIGMA MODULATOR AN0+ AN0- 1x, 4x, 16x, 32x CLKSEL CLKIO RST VDDDGNDAGND

digital conversion and Manchester encoding begins. RST = 1), the 8MHz oscillator is started. lator. This allows the 8MHz oscillator to warm up. 3) The analog front-end (AFE) is enabled. oscillator. This allows the AFE to warm up. clock source provided at CLKIO. RST = 1), the 8MHz oscillator is started. lator. This allows the 8MHz oscillator to warm up. oscillator. This allows the AFE to warm up. 5) The internal voltage reference is enabled. clock source provided at CLKIO. input at CLKIO (if CLKSEL = 1).

• Clock selection—internal or external
• Voltage reference—internal or external
• Gain setting for analog input channel 0—1x, 4x, 16x, or 32x These pins must be set to a valid level for proper oper- ation; they cannot be left disconnected. If any of the configuration inputs are driven by a companion micro- controller (as opposed to being statically connected to V DD or DGND), the inputs can only be changed when the DS8102 is in shutdown mode. Channel 0 Gain Selection Configuration input pins G0 and G1 are used to select the gain setting for analog input channel 0. The avail- able gain configurations are 1x, 4x, 16x, and 32x. The effective input voltage range scales downward propor- tionally with each increased gain selection. For exam- ple, full-scale output at gain = 1x occurs when AN0+ is 2V higher than AN0-. However, with the gain setting at 4x, the output reaches full scale when AN0+ is only 500mV higher than AN0-. Table 1 lists the gain configuration settings available for channel 0. The levels at G0 and G1 should be set when the DS8102 is in shutdown mode. G1 PIN G0 PIN GAIN 0 0 1x 0 1 4x 1 0 16x 1 1 32x

Table 1. Modulator 0 Gain Settings

by external devices if desired. occurs halfway through the bit time slot. CLK/12 as shown in Figure 1. once offset and gain errors have been nullified. verter output (V). It is typically measured in decibels. 1 0 Operation using internal voltage reference (V REF output buffer enabled). 1 1 Operation using external voltage reference (V REF output buffer disabled). Table 2. Voltage Reference Selection and Operating Modes 0 Internal 8MHz oscillator Output: Drives out 8MHz clock. 1 External clock (provided at CLKIO) Input: Accepts external clock. Table 3. Clock Source Selection

Dual Delta-Sigma Modulator and Encoder

143 RST VREF

µC MNIN- DS8102 DC POWER SUPPLY LINE SUPPLY VOLTAGE- DIVIDER AC LINE OUT AC NEUTRAL OUT CURRENT SHUNT AC LINE IN AC NEUTRAL IN Typical Operating Circuit PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

16 TSSOP U16+2 21-0066

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. 11 1 1 1 1 000 0 00 0CLKIO SYNC CHAN0 CHAN1 SYNC CHAN0 CHAN1 SYNC CHAN0 CHAN1 SYNC CHAN0 CHAN1 MNOUT 2 3456789 1 0 1 1 1 2 12 3456789 1 0 1 1 1 2 12 3456789 1 0 1 1 1 2 12 3456789 1 0 1 1 1 2 Figure 1. Manchester Encoder Output Example

Dual Delta-Sigma Modulator and Encoder Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

0 1/09 Initial release. — Changed the part number in the Ordering Information table. 1 In the Electrical Characteristics table, changed f XCLK(MAX) from 12MHz to 8MHz; changed tXCLK-CLCL(MIN) from 83ns to 125ns; changed the Offset Error parameter from 1.4mV (min) to 1.4mV (max); added new conditions and note and changed 1.33MHz (typ) to 0.667MHz (typ) for the Input Sampling Rate parameter. 2, 3 1 2/09 Corrected the reference from CLKSEL to APDREF in the Internal/External Voltage Reference Selection section; corrected the reference from APDREF to CLKSEL in the Internal/External Clock Selection section.