DS80C320_06 MAXIM | Alldatasheet
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Technical content
REV: 101006 Note: Some revisions of this device may incor porate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
FEATURES
80C32-Compatible
8051 Pin and Instruction Set Compatible
Three 16-Bit Timer/Counters
256 Bytes Scratchpad RAM
Addresses 64kB ROM and 64kB RAM High-Speed Architecture
4 Clocks/Machine Cycle (8032 = 12)
DC to 33MHz (DS80C320) DC to 18MHz (DS80C323) Single-Cycle Instruction in 121ns Uses Less Power for Equivalent Work Dual Data Pointer Optional Variable Length MOVX to Access Fast/Slow RAM/Peripherals High-Integration Controller Includes: Power-Fail Reset Programmable Watchdog Timer Early Warning Power-Fail Interrupt Two Full-Duplex Hardware Serial Ports 13 Total Interrupt Sources with Six External Available in 40-Pin DIP, 44-Pin PLCC, and 44-Pin TQFP The High-Speed Microcontroller User’s Guide must be used in conjunction with this data sheet. Download it at: www.maxim-ic.com/microcontrollers. Data sheets contain pin descriptions, feature overviews, and electrical specifications, whereas the user’s guide contains detailed information about device features and operation. PIN CONFIGURATIONS DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers www.maxim-ic.com TOP VIEW
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 2 of 40 DETAILED DESCRIPTION The DS80C320/DS80C323 are fast 80C31/80C32-compa tible microcontrollers. Wasted clock and memory cycles have been removed using a redesigne d processor core. As a result, every 8051 instruction is executed between 1.5 and 3 ti mes faster than the original for the same crystal speed. Typical applications see a speed improvement of 2.5 times usi ng the same code and same crystal. The DS80C320 offers a maximum crystal rate of 33MHz, resul ting in apparent execution speeds of 82.5MHz (approximately 2.5X). The DS80C320/DS80C323 are pin compatible with all th ree packages of the st andard 80C32 and offer the same timer/counters, serial port, and I/O ports. In short, the devices are extremely familiar to 8051 users, but provide the speed of a 16-bit processor. The DS80C320 provides several extras in addition to greater speed. These include a second full hardware serial port, seven additional interrupts, programmable watchdog timer, power-fail interrupt and reset. The device also provides dual data pointers (DPTRs) to speed block data memory moves. It can also adjust the speed of off-chip data memory access to between two a nd nine machine cycles for flexibility in selecting memory and peripherals. The DS80C320 operating voltage ranges from 4.25V to 5.5V, making it ideal as a high-performance upgrade to existing 5V systems. For applications in which power consumption is critical, the DS80C323 offers the same feature set as the DS80C320, but with 2.7V to 5.5V operation. Designers must have two documents to fully use all the features of this device: this data sheet and the High-Speed Microcontroller User’s Guide , available on our website at www.maxim-ic.com/microcontrollers. Data sheets contain pin descri ptions, feature overviews, and electrical specifications, whereas our user’s guides contain detailed information about device features and operation.
ORDERING INFORMATION
COMPLIANT TEMP RANGE MAX CLOCK SPEED (MHz) PIN-PACKAGE DS80C320-MCG DS80C320-MCG+ 0°C to +70°C 25 40 Plastic DIP DS80C320-QCG DS80C320-QCG+ 0°C to +70°C 25 44 PLCC DS80C320-ECG DS80C320-ECG+ 0°C to +70°C 25 44 TQFP DS80C320-MNG DS80C320-MNG+ -40°C to +85°C 25 40 Plastic DIP DS80C320-QNG DS80C320-QNG+ -40°C to +85°C 25 44 PLCC DS80C320-ENG DS80C320-ENG+ -40°C to +85°C 25 44 TQFP DS80C320-MCL DS80C320-MCL+ 0°C to +70°C 33 40 Plastic DIP DS80C320-QCL DS80C320-QCL+ 0°C to +70°C 33 44 PLCC DS80C320-ECL DS80C320-ECL+ 0°C to +70°C 33 44 TQFP DS80C320-MNL DS80C320-MNL+ -40°C to +85°C 33 40 Plastic DIP DS80C320-QNL DS80C320-QNL+ -40°C to +85°C 33 44 PLCC DS80C320-ENL DS80C320-ENL+ -40°C to +85°C 33 44 TQFP DS80C323-MCD DS80C323-MCD+ 0°C to +70°C 18 40 Plastic DIP DS80C323-QCD DS80C323-QCD+ 0°C to +70°C 18 44 PLCC DS80C323-ECD DS80C323-ECD+ 0°C to +70°C 18 44 TQFP DS80C323-QND DS80C323-QND+ -40°C to +85°C 18 44 PLCC DS80C323-END DS80C323-END+ -40°C to +85°C 18 44 TQFP + Denotes a Pb-free/RoHS-compliant device.
Figure 1. Block Diagram provides this function internally. serves as the output of the crystal amplifier. accessed through the bus and during a reset condition.
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 4 of 40 PIN DESCRIPTION (continued) PIN DIP PLCC TQFP NAME FUNCTION 30 33 27 ALE Address Latch-Enable Output. This pin functions as a clock to latch the external address LSB from the multiplexed address/data bus. This signal is commonly connected to the latch enable of an external 373 family transparent latch. ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced high when the device is in a reset condition. 39 43 37 AD0 38 42 36 AD1 37 41 35 AD2 36 40 34 AD3 35 39 33 AD4 34 38 32 AD5 33 37 31 AD6 32 36 30 AD7 Port 0, Input/Output. Port 0 is the multiplexed address/data bus. During the time when ALE is high, the LSB of a memory address is presented. When ALE falls, the port transitions to a bi-directional data bus. This bus is used to read external ROM and read/write external RAM memory or peripherals. The Port 0 has no true port latch and cannot be written directly by software. The reset condition of Port 0 is high. No pullup resistors are needed. Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port and an alternate functional interface for Timer 2 I/O, new External Interrupts, and new Serial Port 1. The reset condition of Port 1 is with all bits at logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. When software writes a 0 to any port pin, the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again becomes the output high (and input) state. The alternate modes of Port 1 are outlined as follows: PIN DIP PLCC TQFP PORT ALTERNATE FUNCTION 1 2 40 P1.0 T2 External I/O for Timer/Counter 2 2 3 41 P1.1 T2EX Timer/Counter 2 Capture/Reload Trigger 3 4 42 P1.2 RXD1 Serial Port 1 Input 4 5 43 P1.3 TXD1 Serial Port 1 Output 5 6 44 P1.4 INT2 External Interrupt 2 (Positive-Edge Detect) 6 7 1 P1.5 INT3 External Interrupt 3 (Negative-Edge Detect) 7 8 2 P1.6 INT4 External Interrupt 4 (Positive-Edge Detect) 1–8 2–9 40–44, 1–3 P1.0–P1.7 8 9 3 P1.7 INT5 External Interrupt 5 (Negative-Edge Detect)
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 5 of 40 PIN DESCRIPTION (continued) PIN DIP PLCC TQFP NAME FUNCTION 21 24 18 A8 (P2.0) 22 25 19 A9 (P2.1) 23 26 20 A10 (P2.2) 24 27 21 A11 (P2.3) 25 28 22 A12 (P2.4) 26 29 23 A13 (P2.5) 27 30 24 A14 (P2.6) 28 31 25 A15 (P2.7) Port 2, Output. Port 2 serves as the MSB for external addressing. P2.7 is A15 and P2.0 is A8. The device will automatically place the MSB of an address on P2 for external ROM and RAM access. Although Port 2 can be accessed like an ordinary I/O port, the value stored on the Port 2 latch will never be seen on the pins (due to memory access). Therefore, writing to Port 2 in software is only useful for the instructions MOVX A, @Ri or MOVX @Ri, A. These instructions use the Port 2 internal latch to supply the external address MSB. In this case, the Port 2 latch value will be supplied as the address information. Port 3, Input/Output. Port 3 functions as both an 8-bit, bidirectional I/O port and an alternate functional interface for External Interrupts, Serial Port 0, Timer 0 & 1 Inputs, RD and WR strobes. The reset condition of Port 3 is with all bits at logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. When software writes a 0 to any port pin, the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again becomes both the output high and input state. The alternate modes of Port 3 are outlined below: PIN DIP PLCC TQFP PORT ALTERNATE MODE 10 11 5 P3.0 RXD0 Serial Port 0 Input 11 13 7 P3.1 TXD0 Serial Port 0 Output 12 14 8 P3.2 INT0 External Interrupt 0 13 15 9 P3.3 INT1 External Interrupt 1 14 16 10 P3.4 T0 Timer 0 External Input 15 17 11 P3.5 T1 Timer 1 External Input 16 18 12 P3.6 WR External Data Memory Write Strobe 10–17 11, 13– 19 5, 7–13 P3.0–P3.7 17 19 13 P3.7 RD External Data Memory Read Strobe 31 35 29 EA External Access, Active-Low Input. This pin must be connected to ground for proper operation. — 12, 34, 6, 28, 39* N.C. No Connection (Reserved). These pins should not be connected. They are reserved for use with future devices in this family. *These pins are reserved for additional ground pins on future products.
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 6 of 40 80C32 COMPATIBILITY The DS80C320/DS80C323 are CMOS 80C32-compatible microcontrollers designed for high performance. In most cases, the devices will drop into an existing 80C32 design to significantly improve the operation. Every effort has been made to keep th e devices familiar to 8032 users, yet they have many new features. In general, software written for existing 80C32-based systems will work on the DS80C320 and DS80C323. The exception is critical timing, because the high-speed microcontroller performs its instructions much faster than the original. It may be necessary to use memories with faster access times if the same crystal frequency is used. designer select the proper memories for her or his application. The DS80C320/DS80C323 run the standard 8051 instruction set and is pin compatible with an 80C32 in any of three standard packages. They also provide the same timer/counter res ources, full-duplex serial port, 256 bytes of scratchpad RAM, and I/O ports as the standard 80C32. Timers will default to a 12 clock-per-cycle operation to keep timing compatible w ith original 8051 systems. However, they can be programmed to run at the new 4 clocks per cycle if desired. New hardware features are accessed using special-func tion registers that do not overlap with standard 80C32 locations. A summary of these SFRs is provided below. The DS80C320/DS80C323 address memory in an identi cal fashion to the sta ndard 80C32. Electrical timing appears different due to the high-speed nature of the product. However, the signals are essentially the same. Detailed timing diagrams are provided in the Electrical Specifications section. This data sheet assumes the user is familiar with the basic features of the standard 80C32. In addition to these standard features, the DS80C 320/DS80C323 include many new func tions. This data sheet provides only a summary and overview. Detailed descriptions are available in the High-Speed Microcontroller User’s Guide.
Figure 2. Comparative Timing of the DS80C320/DS80C323 and 80C32 not just from increasing the clock frequency but also from a newer, more efficient design. are faster than the original 80C51. Table 1 shows a summary of the instruction set, including the speed. feature also allows the user to eliminate wasted instructions when moving blocks of memory.
All instructions in the DS80C320/DS80C323 perform the same functions as their 80C32 counterparts. is different. This applies both in absolute and relative number of clocks. Table 1. However, counter/timers default to run at the older 12 clocks per increment. Therefore, while be set to run at 4 clocks per increment cycle to take advantage of higher speed operation. both are faster than their original counterparts, they now have different execution times from each other. changes. Note that a machine cycle now requires just four clocks, and provides one ALE pulse per cycle. or two cycles except for MUL and DIV.
Table 1. Instruction Set Summary
Table 1. Instruction Set Summary (continued)
speed improvement summary is provided below. is accessed according to a variable-speed MOVX instruction as described below. Figure 3. Typical Memory Connection
LCD displays or UARTs that are not fast. The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below. change this value depending on the particular memory or peripheral. only and the only way to slow program memory (ROM) access is to use a slower crystal. without dramatically lengthening the memory access. Table 2. Data Memory Cycle Stretch Values
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 13 of 40 DUAL DATA POINTER Data memory block moves can be accelerated using the Dual Data Pointer (DPTR). The standard 8032 DPTR is a 16-bit value that is used to addr ess off-chip data RAM or peripherals. In the DS80C320/DS80C323, the standard 16-bit data pointer is called DPTR0 a nd is located at SFR addresses 82h and 83h. These are the standard locations. The new DPTR is located at SFR 84h and 85h and is called DPTR1. The DPTR Select bit (DPS) chooses the active pointer and is located at the LSB of the SFR location 86h. No other bits in register 86h have any effect and are set to 0. The user switches between data pointers by toggling the LSB of register 86h. The increment (INC) instruction is the fastest way to accomplish this. All DPTR-related instructions use the currently selected DPTR for any activity. Therefore only one instruction is required to switch from a source to a destination address. Using the Dual-Data Pointer saves code from needing to save source and destination addresses when doing a block move. Once loaded, the software simply switches betw een DPTR and 1. The releva nt register locations are as follows. DPL 82h Low byte original DPTR DPH 83h High byte original DPTR DPL1 84h Low byte new DPTR DPH1 85h High byte new DPTR DPS 86h DPTR Select (LSB) Sample code listed below illustrates the saving from using the dual DPTR. The example program was original code written for an 8051 and requires a total of 1869 DS80C320/DS80C323 machine cycles. This takes 299 /g109s to execute at 25MHz. The new code usin g the Dual DPTR requires only 1097 machine cycles taking 175.5 /g109s. The Dual DPTR saves 77 2 machine cycles or 123.5 /g109s for a 64-byte block move. Since each pass through the loop saves 12 machine cycles when compared to the single DPTR approach, larger blocks gain more efficiency using this feature. 64-Byte Block Move without Dual Data Pointer ; SH and SL are high and low byte source address. ; DH and DL are high and low byte of destination address. # CYCLES MOV R5, #64d ; NUMBER OF BYTES TO MOVE 2 MOV DPTR, #SHSL ; LOAD SOURCE ADDRESS 3 MOV R1, #SL ; SAVE LOW BYTE OF SOURCE 2 MOV R2, #SH ; SAVE HIGH BYTE OF SOURCE 2 MOV R3, #DL ; SAVE LOW BYTE OF DESTINATION 2 MOV R4, #DH ; SAVE HIGH BYTE OF DESTINATION 2 MOVE: ; THIS LOOP IS PERFORMED THE NUMBER OF TIMES LOADED INTO R5, IN THIS EXAMPLE 64 MOVX A, @DPTR ; READ SOURCE DATA BYTE 2 MOV R1, DPL ; SAVE NEW SOURCE POINTER 2 MOV R2, DPH ; 2 MOV DPL, R3 ; LOAD NEW DESTINATION 2 MOV DPH, R4 ; 2 MOVX @DPTR, A ; WRITE DATA TO DESTINATION 2 INC DPTR ; NEXT DESTINATION ADDRESS 3 MOV R3, DPL ; SAVE NEW DESTINATION POINTER 2 MOV R4, DPH ; 2 MOV DPL, R1 ; GET NEW SOURCE POINTER 2 MOV DPH, R2 ; 2 INC DPTR ; NEXT SOURCE ADDRESS 3 DJNZ R5, MOVE ; FINISHED WITH TABLE? 3
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 14 of 40 64-Byte Block Move with Dual Data Pointer ; SH and SL are high and low byte source address. ; DH and DL are high and low byte of destination address. ; DPS is the data pointer select. Reset condition is DPS=0, DPTR0 is selected. # CYCLES EQU DPS, #86h ; TELL ASSEMBLER ABOUT DPS MOV R5, #64 ; NUMBER OF BYTES TO MOVE 2 MOV DPTR, #DHDL ; LOAD DESTINATION ADDRESS 3 INC DPS ; CHANGE ACTIVE DPTR 2 MOV DPTR, #SHSL ; LOAD SOURCE ADDRESS 2 MOVE: ; THIS LOOP IS PERFORMED THE NUMBER OF TIMES LOADED INTO R5, IN THIS EXAMPLE 64 MOVX A, @DPTR ; READ SOURCE DATA BYTE 2 INC DPS ; CHANGE DPTR TO DESTINATION 2 MOVX @DPTR, A ; WRITE DATA TO DESTINATION 2 INC DPTR ; NEXT DESTINATION ADDRESS 3 INC DPS ; CHANGE DATA POINTER TO SOURCE 2 INC DPTR ; NEXT SOURCE ADDRESS 3 DJNZ R5, MOVE ; FINISHED WITH TABLE? 3 PERIPHERAL OVERVIEW Peripherals in the DS80C320/DS80C323 are accessed using the SFRs. The devices provide several of the most commonly needed peripheral functions in micro computer-based systems. These functions are new to the 80C32 family and include a second serial por t, power-fail reset, pow er-fail interrupt, and a programmable watchdog timer. These are briefly described in the following paragraphs. More details are available in the High-Speed Microcontroller User’s Guide. SERIAL PORTS The DS80C320/DS80C323 provide a serial port (UART) that is identical to the 80C32. Many applications require serial communication with multiple devices. Therefore, a second hardware serial port is provided that is a full duplicate of the standard one. It optionally uses pins P1.2 (RXD1) and P1.3 (TXD1). This port has duplicate control functions in cluded in new SFR locations. The second serial port operates in a comparable manner with the first. Both can operate simultaneously but can be at different baud rates. The second serial port has similar control registers (S CON1 at C0h, SBUF1 at C1h) to the original. One difference is that for timer-based baud rates, the original serial port can use Timer 1 or Timer 2 to generate baud rates. This is selected via SFR bits. The new serial port can only use Timer 1. TIMER-RATE CONTROL One important difference exists between th e DS80C320/DS80C323 and 80C32 regarding timers. The original 80C32 used a 12 clock-per-cycle scheme for timers and consequently for some serial baud rates (depending on the mode). The DS80C320/DS80C323 architecture normally runs using 4 clocks per cycle. However, in the area of timers, it will default to a 12 clock-per-cycle scheme on a reset. This allows existing code with real-time dependenc ies such as baud rates to operate properly. If an application needs higher speed timers or serial baud rates, the timers can be set to run at the 4-clock rate. The Clock Control register (CKCON - 8Eh) determin es these timer speeds. When the relevant CKCON bit is a logic 1, the device uses 4 clocks per cycle to generate timer speeds. When the control bit is set to a 0, the device uses 12 clocks for timer speeds. The re set condition is a 0. CKCON.5 selects the speed of Timer 2. CKCON.4 selects Timer 1 a nd CKCON.3 selects Timer 0. Note th at unless a user desires very fast timing, it is unnecessary to alter these bits. Note that the timer controls are independent.
interrupt enable and software must manually clear it. respectively, and are used to select the watchdog timeout period as shown in Table 3. Table 3. Watchdog Timeout Values
application software to determine the source of a reset. Setting the EWT (WDCON.1) bit enables the Watchdog Timer. The bit is protected by timed access. select the timeout. Finally, the Watchdog Interrupt is enabled using EWDI (EIE.4). new to the 8051 family have a lower natural priority than the originals. Table 4. Interrupt Priority
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 17 of 40 POWER MANAGEMENT The DS80C320/DS80C323 provide the standard Idle and power-down (Stop) modes that are available on the standard 80C32. However, the de vice has enhancements that make these modes more useful, and allow more power saving. The Idle mode is invoked by setting the LSB of the Power Control register (PCON to 87h). Idle will leave internal clocks, serial port and timer running. No memory access will be performed so power is dramatically reduced. Since clocks are running, th e Idle power consumption is related to crystal frequency. It should be approximately one-half the operational power. The CPU can exit the Idle state with any interrupt or a reset. The power-down or Stop mode is invoked by setting th e PCON.1 bit. Stop mode is a lower power state than Idle since it turns off all internal clocking. The I CC of a standard Stop mode is approximately 1 µA but is specified in the Electrical Specifications section. The CPU will exit Stop mode from an external interrupt or a reset condition. Note that internally generated inte rrupts (timer, serial port, watchdog) ar e not useful in Idle or Stop since they require clocking activity. IDLE MODE ENHANCEMENTS A simple enhancement to Idle mo de makes it substantially more us eful. The innovation involves not the Idle mode itself, but the watchdo g timer. As mentioned above, the Wa tchdog Timer provides an optional interrupt capability. This interrupt can provide a periodic interval timer to bring the DS80C320/DS80C323 out of Idle mode. This can be usef ul even if the Watchdog is not normally used. By enabling the Watchdog Timer and its interrupt prior to invoking Idle, a user can periodically come out of Idle perform an operation, then return to Idle until the next operation. This will lower the overall power consumption. When using the Watchdog Interrupt to can cel the Idle state, make sure to restart the Watchdog Timer or it will cause a reset. STOP MODE ENHANCEMENTS The DS80C320/DS80C323 provide two enhancements to the Stop mode. As documented above, the device provides a bandgap reference to determine Powe r-fail Interrupt and Reset thresholds. The default state is that the bandgap reference is off when Stop mode is invoked. This allows the extremely low power state mentioned above. A user can optionall y choose to have the bandgap enabled during Stop mode. This means that PFI and power-fail reset will be activated and are valid means for leaving Stop mode. In Stop mode with the bandgap on, I CC will be approximately 50/g109A compared with 1/g109A with the bandgap off. If a user does not require a Po wer-fail Reset or Interrupt while in Stop mode, the bandgap can remain turned off. Note that only the most power sensitiv e applications should turn off the bandgap, as this results in an uncontrolled power-down condition. The control of the bandgap reference is located in the Extended Interrupt Flag register (EXIF to 91h). Setting BGS (EXIF.0) to a 1 will leave the bandgap reference enabled during Stop mode. The default or reset condition is with the bit at a logic 0. This results in the bandgap being turned off during Stop mode. Note that this bit has no control of the reference during full power or Idle modes. Be aware that the DS80C320 and DS80C323 require that the reset watchdog timer bit (RWT ;WDCON.0) be set
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 18 of 40 immediately preceding the setting of the Stop bit to guarantee a correct power-on delay when exiting Stop mode. The second feature allows an additional power saving option. This is the ability to start instantly when exiting Stop mode. It is accomplished using an internal ring oscillator that can be used when exiting Stop mode in response to an interrupt. The benefit of the ring oscillator is as follows. Using Stop mode turns off the crystal oscillator and all internal clocks to save power. This requires that the oscillator be restarted when exiting Stop mode. Actual start-up time is crystal dependent, but is normally at least 4ms. A common recommendation is 10ms. In an application that will wakeup, perform a short operation, then return to sleep, the crystal startup can be longer than the real transaction. However, the ring oscillator will start instantly. The user can perform a simple operation and return to sleep before the crystal has even stabilized. If the ring is used to start and the processor remains running, hardware will automatically switch to the crystal once a power-on re set interval (65,536 clocks) has expired. This value is used to guarantee stability even though power is not being cycled. If the user returns to Stop mode prior to switching of crystal, then all clocks will be turned off again. The ring oscillator runs at approximately 3MHz (1.5MHz at 3V) but will not be a precision value. No real- time precision operations (including serial communication) should be co nducted during this ring period. Figure 4 shows how the operation would compare when using the ring, and when starting up normally. The default state is to come out of Stop mode without using the ring oscillator. This function is controlled using the RGSL - Ring Select bit at EXIF.1 (EXIF to 91h). When EXIF.1 is set, the ring oscillator will be used to come out of Stop mode quickly. As mentioned above, the processor will automatically switch from the ring (if enabled) to the crystal after a delay of 65,536 crystal clocks. For a 3.57MHz crystal, this is approximately 18ms. Th e processor sets a flag called RGMD - Ring Mode to tell software that the ring is being used. This bit at EXIF.2 will be logic 1 when the ring is in use. No serial communication or precision timin g should be attempted while this bit is set, since the operating frequency is not precise.
Figure 4. Ring Oscillator Startup DIAGRAM ASSUMES THAT THE OPERATION FOLLOWING STOP REQUIRES LESS THAN 18ms COMPLETE.
standard 80C32 registers. The High-Speed Microcontroller User’s Guide describes all SFRs. Table 5. Special-Function Register Locations
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 21 of 40 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground…………………………………………-0.3V to (V CC + 0.5V) This is a stress rating only and functional operation of the devi ce at these or any other conditions above those indicated in t he operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS—DS80C320 (VCC = 4.5V to 5.5V, TA = -40°C to +85°C.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Operating Supply Voltage V CC 4.5 5.0 5.5 V 1 Power-Fail Warning Voltage V PFW 4.25 4.38 4.55 V 1 Minimum Operating Voltage V RST 4.0 4.1 4.25 V 1, 12 Supply Current Active Mode at 25MHz I CC 30 45 mA 2 Supply Current Idle Mode at 25MHz I IDLE 15 25 mA 3 Supply Current Active Mode at 33MHz I CC 35 mA 2 Supply Current Idle Mode at 33MHz I IDLE 20 mA 3 Supply Current Stop Mode, Bandgap Reference Disabled I STOP 0.01 1 µA 4 Supply Current Stop Mode, Bandgap Reference Enabled I SPBG 50 80 µA 4, 10 Input Low Level V IL -0.3 +0.8 V 1 Input High Level (Except XTAL1 and RST) V IH1 2.0 V CC + 0.3 V 1 Input High Level XTAL1 and RST V IH2 3.5 V CC + 0.3 V 1 Output-Low Voltage Ports 1, 3 at IOL = 1.6mA VOL1 0.45 V 1 Output-Low Voltage Ports 0, 2, ALE, PSEN at IOL = 3.2mA VOL2 0.45 V 1, 5 Output-High Voltage Ports 1, 3, ALE, PSEN at IOH = -50µA VOH1 2.4 V 1, 6 Output High Voltage Ports 1, 3 at IOH = -1.5mA VOH2 2.4 V 1, 7 Output-High Voltage Ports 0, 2, ALE, PSEN at IOH = -8mA VOH3 2.4 V 1, 5 Input Low Current Ports 1, 3 at 0.45V I IL -55 µA 11 Transition Current from 1 to 0 Ports 1, 3 at 2V ITL -650 µA 8 Input Leakage Port 0, Bus Mode I L -300 +300 µA 9 RST Pulldown Resistance R RST 50 170 k/g87
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 22 of 40 NOTES FOR DS80C320 DC ELECTRICAL CHARACTERISTICS All parameters apply to both commercial and industrial temperatur e operation unless otherwise noted. Specifications to -40°C are guaranteed by design and are not production tested. 1. All voltages are referenced to ground. 2. Active current is measured with a 25MHz clock source driving XTAL1, V CC = RST = 5.5V, all other pins disconnected. 3. Idle mode current is measured with a 25MHz clock source driving XTAL1, V CC = 5.5V, RST at ground, all other pins disconnected. 4. Stop mode current measured with XTAL1 and RST grounded, VCC = 5.5V, all other pins disconnected. 5. When addressing external memory. This specification only applies to the first clock cycle following transition. 6. RST = V CC. This condition mimics operation of pins in I/O mode. 7. During a 0-to-1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects port in transition mode. 8. Ports 1 and 3 source transition current when being pulled down externally. It reaches its maximum at approximately 2V. 9. 0.45<V IN<VCC. Not a high-impedance input. This port is a weak address holding latch because Port 0 is dedicated as an address bus on the DS80C320. Peak curren t occurs near the input transition point of the latch, approximately 2V. 10. Over the industrial temperature range, this specification has a maximum value of 200/g109A. 11. This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is set to 1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin will also have to overcome the transition current. 12. Device operating range is 4.5V to 5.5V; however, device is tested to 4.0V to ensure proper operation at minimum V RST. TYPICAL ICC vs. FREQUENCY
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 23 of 40 AC CHARACTERISTICS—DS80C320 33MHz VARIABLE CLOCK PARAMETER SYMBOL MIN MAX MIN MAX UNITS External Oscillator 0 33 0 33 Oscillator Frequency External Crystal 1/tCLCL 1 33 1 33 MHz ALE Pulse Width t LHLL 34 1.5t CLCL-11 ns Port 0 Address Valid to ALE Low tAVLL 4 0.5t CLCL-11 ns Address Hold After ALE Low tLLAX1 2 (Note 5) 0.25t CLCL-5 (Note 5) ns Address Hold After ALE Low for MOVX WR tLLAX2 6 0.5t CLCL-9 ns ALE Low to Valid Instruction In tLLIV 49 2.5t CLCL-27 ns ALE Low to PSEN Low tLLPL 0.5 0.25t CLCL-7 ns PSEN Pulse Width tPLPH 61 2.25t CLCL-7 ns PSEN Low to Valid Instruction In tPLIV 48 2.25t CLCL-21 ns Input Instruction Hold After PSEN tPXIX 0 0 ns Input Instruction Float After PSEN tPXIZ 25 t CLCL-5 ns Port 0 Address to Valid Instruction In tAVIV1 64 3t CLCL-27 ns Port 2 Address to Valid Instruction In tAVIV2 73 3.5t CLCL-33 ns PSEN Low to Address Float tPLAZ (Note 5) (Note 5) ns NOTES FOR DS80C320 AC ELECTRICAL CHARACTERISTICS All parameters apply to both commercial and industrial temperatur e operation unless otherwise noted. Specifications to -40°C are guaranteed by design and are not production tested. AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency > 16MHz, and are not 100% tested, but are guaranteed by design. 1. All signals rated over operating temperature at 33MHz. 2. All signals characterized with load capacitance of 80pF except Port 0, ALE, PSEN , RD and WR at 100pF. Note that loading should be approximately equal for valid timing. 3. Interfacing to memory devices with float times (turn off times) over 30ns may cause contention. This will not damage the parts but will cause an increase in operating current. 4. Specifications assume a 50% duty cycle for the oscillator. Port 2 timing will change with the duty cycle variations. 5. Address is held in a weak latch until over driven by external memory.
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 24 of 40 MOVX CHARACTERISTICS—DS80C320 VARIABLE CLOCK PARAMETER SYMBOL MIN MAX UNITS STRETCH 2tCLCL-11 t MCS=0 RD Pulse Width tRLRH tMCS-11 ns tMCS>0 2tCLCL-11 t MCS=0 WR Pulse Width tWLWH tMCS-11 ns tMCS>0 2t CLCL-25 t MCS=0 RD Low to Valid Data In tRLDV t MCS-25 ns tMCS>0 Data Hold After Read t RHDX 0 ns t CLCL-5 t MCS=0 Data Float After Read t RHDZ 2t CLCL-5 ns tMCS>0 2.5t CLCL-27 t MCS=0 ALE Low to Valid Data In t LLDV 1.5t CLCL-28+tMCS ns tMCS>0 3t CLCL-27 t MCS=0 Port 0 Address to Valid Data In tAVDV1 2t CLCL-31+tMCS ns tMCS>0 3.5t CLCL-32 t MCS=0 Port 2 Address to Valid Data In tAVDV2 2.5t CLCL-34+tMCS ns tMCS>0 0.5tCLCL-8 0.5t CLCL+6 t MCS=0 ALE Low to RD or WR Low tLLWL 1.5tCLCL-7 1.5t CLCL+8 ns tMCS>0 tCLCL-11 t MCS=0 Port 0 Address Valid to RD or WR Low tAVWL1 2tCLCL-10 ns tMCS>0 1.5tCLCL-9 t MCS=0 Port 2 Address Valid to RD or WR Low tAVWL2 2.5tCLCL-13 ns tMCS>0 -9 t MCS=0 Data Valid to WR Transition tQVWX tCLCL-10 ns tMCS>0 tCLCL-12 t MCS=0 Data Hold After Write t WHQX 2tCLCL-7 ns tMCS>0 RD Low to Address Float tRLAZ (Note 5) ns 0 10 t MCS=0 RD or WR High to ALE High tWHLH tCLCL-5 t CLCL+11 ns tMCS>0 Note: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the value of tMCS for each Stretch selection. M2 M1 M0 MOVX CYCLES t MCS 0 0 0 2 machine cycles 0 0 0 1 3 machine cycles (default) 4 t CLCL 0 1 0 4 machine cycles 8 t CLCL 0 1 1 5 machine cycles 12 t CLCL 1 0 0 6 machine cycles 16 t CLCL 1 0 1 7 machine cycles 20 t CLCL 1 1 0 8 machine cycles 24 t CLCL 1 1 1 9 machine cycles 28 t CLCL
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 25 of 40 DC ELECTRICAL CHARACTERISTICS—DS80C323 PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Operating Supply Voltage V CC 2.7 3.0 5.5 V 1 Power-Fail Warning Voltage V PFW 2.6 2.7 2.8 V 1 Minimum Operating Voltage V RST 2.5 2.6 2.7 V 1, 12 Supply Current Active Mode at 18MHz I CC 10 mA 2 Supply Current Idle Mode at 18MHz I IDLE 6 mA 3 Supply Current Stop Mode, Bandgap Reference Disabled ISTOP 0.1 µA 2 Supply Current Stop Mode, Bandgap Reference Enabled ISPBG 40 µA 4, 10 Input Low Level V IL -0.3 +0.2 x V CC V 1 Input High Level (Except XTAL1 and RST) VIH1 0.7 x V CC V CC+0.3 V 1 Input High Level XTAL1 and RST V IH2 0.7 x VCC +0.25V V CC+0.3 V 1 Output Low Voltage Ports 1, 3 at IOL = 1.6mA VOL1 0.4 V 1 Output Low Voltage Ports 0, 2, PSEN /ALE at IOL = 3.2mA VOL2 0.4 V 1, 5 Output High Voltage Ports 1, 3, PSEN /ALE at IOH = -15µA VOH1 VDD -0.4V V 1, 6 Output High Voltage Ports 1, 3 at IOH = -1.5mA VOH2 VDD -0.4V V 1, 7 Output High Voltage Ports 0, 2, PSEN /ALE at IOH = -2mA VOH3 VDD -0.4V V 1, 5 Input Low Current Ports 1, 3 at 0.45V I IL -30 µA 11 Transition Current from 1 /g179 0, Ports 1, 3 at 2V ITL -400 µA 8 Input Leakage Port 0, Bus Mode I L -300 +300 µA 9 RST Pulldown Resistance R RST 50 170 k/g87 NOTES FOR DS80C323 DC ELECTRICAL CHARACTERISTICS All parameters apply to both commercial and industrial temperatur e operation unless otherwise noted. Specifications to -40°C are guaranteed by design and are not production tested. Device operating range is 2.7V to 5.5V. DC electrical specifications are for operation 2.7V to 3.3V. 1. All voltages are referenced to ground. 2. Active mode current is measured with an 18MHz clock source driving XTAL1, V CC = RST = 3.3V, all other pins disconnected. 3. Idle mode current is measured with an 18MHz clock source driving XTAL1, V CC = 3.3V, all other pins disconnected. 4. Stop mode current measured with XTAL1 and RST grounded, V CC = 3.3V, all other pins disconnected. 5. When addressing external memory. This specification only applies to the first clock cycle following the transition.
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 26 of 40 NOTES FOR DS80C323 DC ELECTRICAL CHARACTERISTICS (continued) All parameters apply to both commercial and industrial temperatur e operation unless otherwise noted. Specifications to -40°C are guaranteed by design and are not production tested. Device operating range is 2.7V to 5.5V. DC electrical specifications are for operation 2.7V to 3.3V. 6. RST = V CC. This condition mimics operation of pins in I/O mode. 7. During a 0-to-1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects port in transition mode. 8. Ports 1, 2, and 3 source transition current when being pulled down externally. It reaches its maximum at approximately 2V. 9. V IN between ground and V CC - 0.3V. Not a high-impedance input. This port is a weak address latch because Port 0 is dedicated as an address bus on the DS80C323. Peak current occurs near the input transition point of the latch, approximately 2V. 10. Over the industrial temperature range, this specification has a maximum value of 200/g109A. 11. This is the current from an external circuit to hold a logic low level on an I/O pin while the corresponding port latch bit is set to 1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin will also have to overcome the transition current. 12. Device operating range is 2.7V to 5.5V, however device is tested to 2.5V to ensure proper operation at minimum VRST.
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 27 of 40 AC ELECTRICAL CHARACTERISTICS—DS80C323
18 MHz VARIABLE CLOCK PARAMETER SYMBOL
Oscillator 0 18 0 18 Oscillator Frequency External Crystal 1/tCLCL 1 18 1 18 MHz ALE Pulse Width t LHLL 68 1.5t CLCL-15 ns Port 0 Address Valid to ALE Low tAVLL 16 0.5t CLCL-11 ns Address Hold After ALE Low tLLAX1 6 (Note 5) 0.25t CLCL-8 (Note 5) ns Address Hold After ALE Low for MOVX WR tLLAX2 14 0.5t CLCL-13 ns ALE Low to Valid Instruction In tLLIV 93 2.5t CLCL-46 ns ALE Low to PSEN Low tLLPL 4 0.25t CLCL-10 ns PSEN Pulse Width tPLPH 118 2.25t CLCL-7 ns PSEN Low to Valid Instruction In tPLIV 87 2.25t CLCL-38 ns Input Instruction Hold After PSEN tPXIX 0 0 ns Input Instruction Float After PSEN tPXIZ 51 t CLCL-5 ns Port 0 Address to Valid Instruction In tAVIV1 128 3t CLCL-39 ns Port 2 Address to Valid Instruction In tAVIV2 139 3.5t CLCL-56 ns PSEN Low to Address Float tPLAZ (Note 5) (Note 5) ns NOTES FOR DS80C323 AC ELECTRICAL CHARACTERISTICS All parameters apply to both commercial and industrial temperatur e operation unless otherwise noted. Specifications to -40°C are guaranteed by design and are not production tested. AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency > 16MHz, and are not 100% production tested, but are guaranteed by design. 1. All signals rated over operating temperature at 18MHz. 2. All signals characterized with load capacitance of 80pF except Port 0, ALE, PSEN , RD , and WR at 100pF. Note that loading should be approximately equal for valid timing. 3. Interfacing to memory devices with float times (turn off times) over 35ns may cause contention. This will not damage the parts, but will cause an increase in operating current. 4. Specifications assume a 50% duty cycle for the oscillator. Port 2 timing will change with the duty cycle variations. 5. Address is held in a weak latch until over-driven by external memory.
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 28 of 40 MOVX CHARACTERISTICS—DS80C323 VARIABLE CLOCK PARAMETER SYMBOL MIN MAX UNITS STRETCH 2tCLCL-11 t MCS=0 RD Pulse Width tRLRH tMCS-11 ns tMCS>0 2tCLCL-11 t MCS=0 WR Pulse Width tWLWH tMCS-11 ns tMCS>0 2t CLCL-32 t MCS=0 RD Low to Valid Data In tRLDV t MCS-36 ns tMCS>0 Data Hold After Read t RHDX 0 ns t CLCL-5 t MCS=0 Data Float After Read t RHDZ 2t CLCL-7 ns tMCS>0 2.5t CLCL-43 t MCS=0 ALE Low to Valid Data In t LLDV 1.5t CLCL-45+tMCS ns tMCS>0 3t CLCL-40 t MCS=0 Port 0 Address to Valid Data In tAVDV1 2t CLCL-42+tMCS ns tMCS>0 3.5t CLCL-58 t MCS=0 Port 2 Address to Valid Data In tAVDV2 2.5t CLCL-59+tMCS ns tMCS>0 0.5tCLCL-18 0.5t CLCL+7 t MCS=0 ALE Low to RD or WR Low tLLWL 1.5tCLCL-11 1.5t CLCL+8 ns tMCS>0 tCLCL-10 t MCS=0 Port 0 Address Valid to RD or WR Low tAVWL1 2tCLCL-10 ns tMCS>0 1.5tCLCL-27 t MCS=0 Port 2 Address Valid to RD or WR Low tAVWL2 2.5tCLCL-25 ns tMCS>0 -14 t MCS=0 Data Valid to WR Transition tQVWX tCLCL-13 ns tMCS>0 tCLCL-15 t MCS=0 Data Hold After Write t WHQX 2tCLCL-13 ns tMCS>0 RD Low to Address Float tRLAZ (Note 5) ns -1 14 t MCS=0 RD or WR High to ALE High tWHLH tCLCL-5 t CLCL+16 ns tMCS>0 Note: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the value of tMCS for each Stretch selection. M2 M1 M0 MOVX CYCLES t MCS 0 0 0 2 machine cycles 0 0 0 1 3 machine cycles (default) 4 t CLCL 0 1 0 4 machine cycles 8 t CLCL 0 1 1 5 machine cycles 12 t CLCL 1 0 0 6 machine cycles 16 t CLCL 1 0 1 7 machine cycles 20 t CLCL 1 1 0 8 machine cycles 24 t CLCL 1 1 1 9 machine cycles 28 t CLCL
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 29 of 40 EXTERNAL CLOCK CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNITS Clock High Time t CHCX 10 ns Clock Low Time t CLCX 10 ns Clock Rise Time t CLCH 5 ns Clock Fall Time t CHCL 5 ns SERIAL PORT MODE 0 TIMING CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SM2 = 0; 12 clocks per cycle 12t CLCL Serial Port Clock Cycle Time tXLXL SM2 = 1; 4 clocks per cycle 4t CLCL ns SM2 = 0 12 clocks per cycle 10t CLCL Output Data Setup to Clock Rising Edge tQVXH SM2 = 1; 4 clocks per cycle 3t CLCL ns SM2 = 0 12 clocks per cycle 2t CLCL Output Data Hold from Clock Rising tXHQX SM2 = 1; 4 clocks per cycle t CLCL ns SM2 = 0; 12 clocks per cycle t CLCL Input Data Hold After Clock Rising tXHDX SM2 = 1; 4 clocks per cycle t CLCL ns SM2 = 0; 12 clocks per cycle 11t CLCL Clock Rising Edge to Input Data Valid tXHDV SM2 = 1 4 clocks per cycle 2t CLCL ns EXPLANATION OF AC SYMBOLS In an effort to remain compatible with the original 80 51 family, this device specifies the same parameter as such devices, using the same symbols. For completeness, the following is an explanation of the symbols. t Time A Address C Clock D Input data H Logic level high L Logic level low I Instruction P PSEN Q Output data R RD signal V Valid W WR signal X No longer a valid logic level Z Tri-state
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 30 of 40 POWER-CYCLE TIMING CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Crystal Startup Time t CSU 1.8 ms 1 Power-On Reset Delay t POR 65,536 t CLCL 2 NOTES FOR POWER CYCLE TIMING CHARACTERISTICS 1. Startup time for crystals varies with load capa citance and manufacturer. Time shown is for an 11.0592MHz crystal manufactured by Fox crystal. 2. Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins when the level on the XTAL1 input meets the VIH2 criteria. At 25MHz, this time is 2.62ms. PROGRAM MEMORY READ CYCLE
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 31 of 40 DATA MEMORY READ CYCLE
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 32 of 40 DATA MEMORY WRITE CYCLE DATA MEMORY WRITE WITH STRETCH = 1
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 33 of 40 DATA MEMORY WRITE WITH STRETCH = 2 4-CYCLE DATA MEMORY WRITE STRETCH VALUE = 2 EXTERNAL CLOCK DRIVE
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 34 of 40 SERIAL PORT MODE 0 TIMING SERIAL PORT 0 (SYNCHRONOUS MODE) HIGH SPEED OPERATION SM2 = 1 ≥ TXD CLOCK = XTAL/4 SERIAL PORT 0 (SYNCHRONOUS MODE) SM2 = 0 ≥ TXD CLOCK = XTAL/12
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 35 of 40 POWER-CYCLE TIMING
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 36 of 40
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 37 of 40 PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 38 of 40 PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 39 of 40 DATA SHEET REVISION SUMMARY The following represent the key differences between the 101006 and 070505 version of the DS80C320/DS80C323 data sheet. Please review this summary carefully. 1. Deleted DS80C323-MND from Ordering Information table (page 2). Device was never manufactured. The following represent the key differences between the 070505 and 051804 version of the DS80C320/DS80C323 data sheet. Please review this summary carefully. 2. Added Pb-free/RoHS-compliant part numbers to Ordering Information table. 3. Deleted the “A” from the IPC/JEDEC J-STD-020 specification in the Absolute Maximum Ratings. The following represent the key differen ces between the 051804 and the 112299 version of the DS80C320/DS80C323 data sheet. Please review this summary carefully. 1. Removed “Preliminary” status as a result of final characterization. 2. Added industrial temperature DS80C323 devices to ordering information. 3. Updated soldering temperature speci fication to reflect JEDEC standards. 4. Updated the following DS80C323 AC timing parameters with final characterization data: t LHLL, tLLAX1, tLLAX2, tLLAX2, tLLIV, tLLPL, tPLIV, tAVIV1, tRLDV, tRHDZ, tLLDV, tAVDV1, tAVDV2, tLLWL, tAVWL1, tAVWL2, tQVWX, tWHQX, tWHLH. 5. Updated the following DS80C320 AC timing parameters with final characterization data: t WHQX, tLHLL, tLLAX2, tLLDV, tAVDV1, tLLWL, tAVWL1, tAVWL2. 6. Added note advising the need to reset watchdog timer before setting the Stop bit. 7. Added note clarifying drive strength of P0, P2, ALE, PSEN. 8. Obsoleted DS80C320 25MHz AC timing tables; merged into 33MHz AC timing tables. 9. Corrected Serial Port Mode 0 Timing diagrams to show correct order of D6, D7. The following represent the key differences between the 041896 and the 052799 version of the DS80C320 data sheet. Please review this summary carefully. 1. Corrected V CC pin description to show DS80C323 operation at +3V. 2. Corrected Timed Access descrip tion to show three-cycle window. 3. Modified absolute Maximum Ratings for any pin relative to around, V CC relative to ground. 4. Changed minimum oscillator frequency to 1MHz when using external crystal. 5. Clarified that t POR begins when XTAL1 reaches VIH2. The following represent the key differences between the 103196 and the 041896 version of the DS80C320 data sheet. Please review this summary carefully. 1. Updated DS80C320 25MHz AC Characteristics. The following represent the key differences between the 041895 and the 031096 version of the DS80C320 data sheet. Please review this summary carefully. 1. Remove Port 0, Port 2 from V OH1 specification (PCN B60802). 2. V OH1 test specification clarified (RST = VCC). 3. Add t AVWL2 marking to External Memory Read Cycle figure. 4. Correct TQFP drawing to read 44-pin TQFP. 5. Rotate page 1 TQFP illustration to match assembly specifications. The following represent the key differences between the 031096 and the 052296 version of the DS80C320 data sheet. Please review this summary carefully. 1. Added Data Sheet Revision Summary section. The following represent the key differences between 05/23/96 and 05/22/96 version of the DS80C320 data sheet and between 05/23/96 and 03/27/95 version of the DS80C323 data sheet. Please review this summary carefully. DS80C320: 1. Add DS80C323 Characteristics. 2. Change DS80C320 V PFW specification from 4.5V to 4.55V (PCN E62802). 3. Update DS80C320 33MHz AC Characteristics. DS80C323: 1. Delete Data Sheet. Contents moved to DS80C320/DS80C323.
DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers 40 of 40 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. DATA SHEET REVISION SUMMARY (continued) The following represent the key differen ces between the 05/22/96 and the 10/21/97 version of the DS80C320 data sheet. Please review this summary carefully. DS80C320 1. Added note to clarify I IL specification. 2. Added note to clarify AC timing conditions. 3. Corrected erroneous t QVXL label on figure “Serial Port Mode 0 Timing” to read tQVXH. 4. Added note to prevent accidental corruption of Watchdog Timer count while changing counter length. DS80C323 1. Added note to clarify I IL specification. 2. Remove port 2 from V OH1 specification, add port 3. 3. I OH for VOH3 specification changed from -3mA to -2mA. 4. Added note to clarify AC timing conditions.