DS8024-RJX+

DS8024_V3 MAXIM | Alldatasheet

Document overview

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Technical content

Features

♦ Analog Interface and Level Shifting for IC Card Communication ♦ ±8kV (min) ESD (IEC) Protection on Card Interfaces ♦ Internal IC Card Supply-Voltage Generation: 5.0V ±5%, 80mA (max) 3.0V ±8%, 65mA (max) ♦ Automatic Card Activation and Deactivation Controlled by Dedicated Internal Sequencer ♦ I/O Lines from Host Directly Level Shifted for Smart Card Communication ♦ Flexible Card Clock Generation, Supporting External Crystal Frequency Divided by 1, 2, 4, or 8 ♦ High-Current, Short-Circuit and High-Temperature Protection

Ordering Information

Note: Contact the factory for availability of other variants and package options. +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive-qualified part. EMV is a registered trademark of EMVCo LLC. EMV Level 1 library and hardware reference design available. Contact factory for details. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of a ny device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. PART TEMP RANGE PIN-PACKAGE DS8024-RJX+ -40 °C to +85°C 28 TSSOP DS8024-RJX/V+ -40 °C to +85°C 28 TSSOP DS8024-RRX+ -40 °C to +85°C 28 SO Selector Guide appears at end of data sheet. PGND AUX2IN AUX1IN I/OIN XTAL2 TOP VIEW DS8024 XTAL1 OFF GND

21 V DD

20 RSTIN

19 CMDVCC

18 N.C.

17 V CC

16 RST

15 CLK

V DDA VUP PRES PRES I/O AUX2 AUX1 14CGND CP2 SO/TSSOP Pin Configuration

RECOMMENDED DC OPERATING CONDITIONS (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on CP1, CP2, and VUP Voltage Range on All Other Pins Continuous Power Dissipation (multilayer board, TA = +70°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Digital Supply Voltage V DD 2.7 6.0 V VCC = 5V, |ICC| < 80mA 4.0 6.0 Card Voltage-Generator Supply Voltage V DDA VCC = 5V, |ICC| < 30mA 3.0 6.0 V VTH2 Threshold voltage (falling) 2.30 2.45 2.60 V Reset Voltage Thresholds VHYS2 Hysteresis 50 100 150 mV CURRENT CONSUMPTION Active VDD Current 5V Cards (Including 80mA Draw from 5V Card) IDD_50V ICC = 80mA, fXTAL = 20MHz, fCLK = 10MHz, VDDA = 5.0V 215 mA Active VDD Current 5V Cards (Current Consumed by DS8024 Only) IDD_IC ICC = 80mA, fXTAL = 20MHz, fCLK = 10MHz, VDDA = 5.0V (Note 2) 135 mA Active VDD Current 3V Cards (Including 65mA Draw from 3V Card) IDD_30V ICC = 65mA, fXTAL = 20MHz, fCLK = 10MHz, VDDA = 5.0V 100 mA Active VDD Current 3V Cards (Current Consumed by DS8024 Only) IDD_IC ICC = 65mA, fXTAL = 20MHz, fCLK = 10MHz, VDDA = 5.0V (Note 2) 35 mA Inactive-Mode Current I DD Card inactive 500 μA CLOCK SOURCE Crystal Frequency f XTAL External crystal 0 20 MHz fXTAL1 0 20 MHz VIL_XTAL1 Low-level input on XTAL1 (Note 3) -0.3 0.3 x VDDXTAL1 Operating Conditions VIH_XTAL1 High-level input on XTAL1 (Note 3) 0.7 x VDD VDD + 0.3 V External Capacitance for Crystal CXTAL1, CXTAL2 (Note 3) 15 pF Internal Oscillator f INT 2.7 MHz SHUTDOWN TEMPERATURE Shutdown Temperature T SD (Note 3) +150 °C

RECOMMENDED DC OPERATING CONDITIONS (continued) (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RST PIN Output Low Voltage V OL_RST1 I OL_RST = 1mA 0 0.3 V Card-Inactive Mode Output Current I OL_RST1 V O_LRST = 0V 0 -1 mA Output Low Voltage V OL_RST2 I OL_RST = 200μA 0 0.3 V Output High Voltage VOH_RST2 I OH_RST = -200μA VCC -

0.5 V CC V

Rise Time t R_RST C L = 30pF (Note 3) 0.1 μs Fall Time t F_RST C L = 30pF (Note 3) 0.1 μs Shutdown Current Threshold IRST(SD) -20 mA Current Limitation I RST(LIMIT) -20 +20 mA Card-Active Mode RSTIN to RST Delay t D(RSTIN-RST) 2 μs CLK PIN Output Low Voltage V OL_CLK1 IOLCLK = 1mA 0 0.3 V Card-Inactive Mode Output Current I OL_CLK1 V OLCLK = 0V 0 -1 mA Output Low Voltage V OL_CLK2 I OLCLK = 200μA 0 0.3 V Output High Voltage VOH_CLK2 IOHCLK = -200μA VCC - Rise Time t R_CLK C L = 30pF (Note 3) 8 ns Fall Time t F_CLK C L = 30pF (Note 3) 8 ns Current Limitation I CLK(LIMIT) -70 +70 mA Clock Frequency f CLK Operational (Note 3) 0 10 MHz Duty Factor C L = 30pF (Note 3) 45 55 % Card-Active Mode Slew Rate SR C L = 30pF (Note 3) 0.2 V/ns VCC PIN Output Low Voltage V CC1 I CC = 1mA 0 0.3 V Card-Inactive Mode Output Current I CC1 V CC = 0V 0 -1 mA ICC(5V) < 80mA 4.75 5.00 5.25 ICC(3V) < 65mA 2.78 3.00 3.22 5V card: current pulses of 40nC with I < 200mA, t < 400ns, f < 20MHz (Note 3) 4.6 5.4 Output Low Voltage V CC2 3V card: current pulses of 24nC with I < 200mA, t < 400ns, f < 20MHz (Note 3) 2.75 3.25 V VCC(5V) = 0 to 5V -80 Output Current I CC2 VCC(3V) = 0 to 3V -65 mA Shutdown Current Threshold ICC(SD) 120 mA Card-Active Mode Slew Rate V CCSR Up/down, C < 300nF 0.05 0.16 0.22 V/μs

RECOMMENDED DC OPERATING CONDITIONS (continued) (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DATA LINES (I/O AND I/OIN) I/O I/OIN Falling Edge Delay t D(IO-IOIN) (Note 3) 200 ns Pullup Pulse Active Time t PU (Note 3) 100 ns Maximum Frequency f IOMAX 1 MHz Input Capacitance C I (Note 3) 10 pF I/O, AUX1, AUX2 PINS Output Low Voltage V OL_IO1 I OL_IO = 1mA 0 0.3 V Output Current I OL_IO1 V OL_IO = 0V 0 -1 mA Card-Inactive Mode Internal Pullup Resistor RPU_IO To V CC 9 11 19 k Output Low Voltage V OL_IO2 IOL_IO = 1mA 0 0.3 V Output High Voltage VOH_IO2 I OH_IO = < -40μA (3V/5V) 0.75 x V CC V CC V Output Rise/Fall Time tOT C L = 30pF (Note 3) 0.1 μs Input Low Voltage V IL_IO -0.3 +0.8 Input High Voltage V IH_IO 1.5 V CC V Input Low Current I IL_IO VIL_IO = 0V 700 μA Input High Current I IH_IO V IH_IO = VCC 20 μA Input Rise/Fall Time t IT (Note 3) 1.2 μs Current Limitation I IO(LIMIT) C L = 30pF -15 +15 mA Card-Active Mode Current When Pullup Active IPU CL = 80pF, VOH = 0.9 x VDD (Note 3) -1 mA I/OIN, AUX1IN, AUX2IN PINS Output Low Voltage V OL I OL = 1mA 0 0.3 V Output High Voltage V OH I OH < -40μA 0.75 x VDD VDD + 0.1 V Output Rise/Fall Time t OT C L = 30pF, 10% to 90% (Note 3) 0.1 μs Input Low Voltage V IL -0.3 0.3 x VDD V Input High Voltage V IH 0.7 x VDD VDD + 0.3 V Input Low Current I IL_IO V IL = 0V 600 μA Input High Current I IH_IO V IH = VDD 10 μA Input Rise/Fall Time t IT V IL to VIH (Note 3) 1.2 μs Integrated Pullup Resistor R PU Pullup to V DD 9 11 13 k Current When Pullup Active I PU CL = 30pF, VOH = 0.9 x VDD (Note 3) -1 mA

RECOMMENDED DC OPERATING CONDITIONS (continued) (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONTROL PINS (CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V) Input Low Voltage V IL -0.3 0.3 x VDD V Input High Voltage V IH 0.7 x VDD VDD + 0.3 V Input Low Current I IL_IO 0 < V IL < VDD 5 μA Input High Current I IH_IO 0 < V IH < VDD 5 μA Integrated Pullup Resistor R PU Pullup to V DD, 5V/3V only 50 85 120 k INTERRUPT OUTPUT PIN (OFF) Output Low Voltage V OL I OL = 2mA 0 0.3 V Output High Voltage V OH I OH = -15μA 0.75 x VDD V Integrated Pullup Resistor R PU Pullup to V DD 12 20 28 k PRES, PRES PINS Input Low Voltage V IL_PRES 0.3 x VDD V Input High Voltage V IH_PRES 0.7 x VDD V Input Low Current I IL_PRES VIL_PRES = 0V 40 μA Input High Current I IH_PRES VIH_PRES = VDD 40 μA TIMING Activation Time t ACT 160 μs Deactivation Time t DEACT 80 μs Window Start t 3 95 CLK to Card Start Time Window End t 5 160 μs PRES/PRES Debounce Time t DEBOUNCE 8 ms Note 1: Operation guaranteed at TA = -40°C and TA = +85°C, but not tested. Note 2: IDD_IC measures the amount of current used by the DS8024 to provide the smart card current minus the load. Note 3: Guaranteed by design, but not production tested.

1, 2 CLKDIV1, CLKDIV2 Clock Divider. Determines the divided-down input clock frequency (presented at XTAL1 or from a crystal at XTAL1 and XTAL2) on the CLK output pin. Dividers of 1, 2, 4, and 8 are available. 3 5V/ 3V 5V/3V Selection Pin. Allows selection of 5V or 3V for communication with an IC card. Logic-high selects 5V operation; logic-low selects 3V operation. See Table 3 for a complete description of choosing card voltages.

4 PGND Analog Ground

5, 7 CP2, CP1 Step-Up Converter Contact. Charge-pump capacitor. Connect a 100nF capacitor (ESR < 100m ) between CP1 and CP2. 6 V DDA Charge-Pump Supply. Must be equal to or higher than V DD. Connect a supply of at least 3.3V. 8 V UP Charge-Pump Output. Connect a 100nF capacitor (ESR < 100m ) between VUP and GND. 9 PRES Card Presence Indicator. Active-low card presence inputs. When the presence indicator becomes active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active. 10 PRES Card Presence Indicator. Active-high card presence inputs. When the presence indicator becomes active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active. 11 I/O Smart Card Data-Line Output. Card data communication line, contact C7. 12, 13 AUX2, AUX1 Smart Card Auxiliary Line (C4, C8) Output. Data line connected to card reader contacts C4 (AUX1) and C8 (AUX2).

14 CGND Smart Card Ground

15 CLK Smart Card Clock. Card clock, contact C3. 16 RST Smart Card Reset. Card reset output from contact C2. Smart Card Supply Voltage. Decouple to CGND (card ground) with 2 x 100nF or 100 + 220nF capacitors (ESR < 100m). 18 N.C. No Connection. Unused on the DS8024. 19 CMDVCC Activation Sequence Initiate. Active-low input from host. 20 RSTIN Card Reset Input. Reset input from the host.

21 V DD Supply Voltage

22 GND Digital Ground

23 OFF Status Output. Active-low interrupt output to the host. Use a 20k integrated pullup resistor to VDD. 24, 25 XTAL1, XTAL2 Crystal/Clock Input. Connect an input from an external clock to XTAL1 or connect a crystal across XTAL1 and XTAL2. For the low idle-mode current variant, an external clock must be driven on XTAL1. 26 I/OIN I/O Input. Host-to-interface chip data I/O line. 27, 28 AUX1IN, AUX2IN C4/C8 Input. Host-to-interface I/O line for auxiliary connections to C4 and C8.

VDD has reached a level higher than V TH2 + V HYS2. XTAL, f XTAL/2, f XTAL/4, or f XTAL/8. CLKDIV2 and the frequency of CLK. of CLK is 8 periods of XTAL1. the instant of change have the correct width. XTAL1 should be less than 5% of the period. tal characteristics and frequency. completion of the activation sequence). The three data lines I/O, AUX1, and AUX2 are identical. thus transmitting the logic 0 present on the master side. for the host to initiate a smart card session.

• All card contacts are inactive (approximately 200 Ω to GND).
• Pins I/OIN, AUX1IN, and AUX2IN are in the high- impedance state (11kΩ pullup resistor to V DD).
• Voltage generators are stopped.
• XTAL oscillator is running (if included in the device).
• Voltage supervisor is active.
• The internal oscillator is running at its low frequency. Activation Sequence After power-on and the reset delay, the host microcon- troller can monitor card presence with signals OFF and CMDVCC, as shown in Table 2.

Table 1. Clock Frequency Selection Table 2. Card Presence Indication

1) Host: CMDVCC is pulled low. internal oscillator period (approximately 25µs). when the clock is applied to the card. 5) DS8024: RSTIN has no further effect on CLK after t5. vation with RSTIN held permanently high. Figure 3. Activation Sequence Using RSTIN and CMDVCC

returns the card interface to the inactive mode. tion sequence is complete (at tDE). up through an 11kΩ resistor). 7) The internal oscillator returns to its lower frequency. overload detector triggers at approximately 120mA. to 200mA to be drawn without causing deactivation. dations to help maintain VCC voltage accuracy.

• Short-circuit or high current on V CC
• Card removal while the interface is activated DD dropping below threshold
• Card voltage generator operating out of the speci- fied values (V DDA too low or current consumption too high)
• Overheating There are two different cases for how the DS8024 reacts to fault detection (Figure 6):
• Outside a Card Session (CMDVCC High). Output OFF is low if a card is not in the card reader and high if a card is in the reader. The V DD supply is monitored—a decrease in input voltage generates an internal power-on reset pulse but does not affect the OFF signal. Short-circuit and tempera- ture detection are disabled because the card is not powered up.
• Within a Card Session ( CMDVCC Low). Output OFF goes low when a fault condition is detected, and an emergency deactivation is performed auto- matically (Figure 7). When the system controller resets CMDVCC to high, it may sense the OFF level again after completing the deactivation sequence. This distinguishes between a card extraction and a hardware problem (OFF goes high again if a card is present). Depending on the con- nector’s card-present switch (normally closed or normally open) and the mechanical characteristics of the switch, bouncing can occur on the PRES sig- nals at card insertion or withdrawal. The DS8024 has a debounce feature with an 8ms typi- cal duration (Figure 6). When a card is inserted, output OFF goes high after the debounce time delay. When the card is extracted, an automatic deactivation sequence of the card is performed on the first true/false transition on PRES and output OFF goes low. Stop Mode (Low-Power Mode) The DS8024 (like the TDA8024) does not support a low- power stop mode. For applications requiring low-power support, refer to the DS8113. Smart Card Power Select The DS8024 supports two smart card V CC voltages: 3V and 5V. The power select is controlled by the 5V/ 3V signal as shown in Table 3. VCC is 5V if 5V/3V is assert- ed to a logic-high state, and VCC is 3V if 5V/3V is pulled to a logic-low state.

Table 3. VCC Select and Operation Mode

*PLACE A 100nF CAPACITOR CLOSE TO DS8024 AND PLACE A 220nF CAPACITOR CLOSE TO CARD CONTACT. **SCHEMATIC ASSUMES A NORMALLY CLOSED CONNECTION TO GROUND IN THE SOCKET. INSERTING A CARD BREAKS THE CONNECTION AND PULLS PRES HIGH. Figure 8. Typical Application Diagram

Performance can be affected by the layout of the appli- cation. For example, an additional cross-capacitance of 1pF between card reader contacts C2 (RST) and C3 (CLK) or C2 (RST) and C7 (I/O) can cause contact C2 to be polluted with high-frequency noise from C3 (or C7). In this case, include a 100pF capacitor between contacts C2 and CGND. Application recommendations include the following:

• Ensure there is ample ground area around the DS8024 and the connector; place the DS8024 very near to the connector; decouple the V DD and VDDA lines separately. These lines are best posi- tioned under the connector.
• The DS8024 and the host microcontroller must use the same V DD supply. Pins CLKDIV1, CLKDIV2, RSTIN, PRES, AUX1IN, I/OIN, AUX2IN, 5V/ 3V, CMDVCC, and OFF are referenced to V DD; if pin XTAL1 is to be driven by an external clock, also reference this pin to V DD.
• Trace C3 (CLK) should be placed as far as possi- ble from the other traces.
• The trace connecting CGND to C5 (GND) should be straight (the two capacitors on C1 (VCC) should be connected to this ground trace).
• Avoid ground loops among CGND, PGND, and GND.
• Decouple V DDA and V DD separately; if the two supplies are the same in the application, they should be connected in a star on the main trace.
• Connect a 100nF capacitor (ESR < 100m Ω) between V CC and CGND and place near the DS8024’s VCC pin.
• Connect a 100nF or 220nF capacitor (220nF pre- ferred, ESR < 100m Ω) between V CC and CGND and place near the smart card socket’s C1 contact. With all these layout precautions, noise should be kept to an acceptable level and jitter on C3 (CLK) should be less than 100ps. Technical Support For technical support, go to https://support.maxim- ic.com/micro. Selector Guide Note: Contact the factory for availability of other variants and package options. +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. PART CURRENT VOLTAGES SUPPORTED (V) SUPPORTS STOP MODE? PIN- PACKAGE DS8024-RJX+ 3.0, 5.0 No 28 TSSOP DS8024-RJX/V+ 3.0, 5.0 No 28 TSSOP DS8024-RRX+ 3.0, 5.0 No 28 SO

Package Information

For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

28 SO (300 mils) W28+6 21-0042 90-0109

28 TSSOP U28+1 21-0066 90-0171

EMVCo approval of the interface module (IFM) contained in this Terminal shall mean only that the IFM has been tested in accorda nce and for sufficient conformance with the EMV Specifications, Version 3.1.1, as of the date of testing. EMVCo approval is not in any way an endorsement or warranty regarding the completeness of the approval process or the functionality, quality or performance of any particular product or service. EMV Co does not warrant any products or services provided by third parties, including, but not limited to, the producer or provider of the IFM and EMVCo ap proval does not under any circumstances include or imply any product warranties from EMVCo, including, without limitation, any implied warranties of merc hantability, fitness for pur- pose, or noninfringement, all of which are expressly disclaimed by EMVCo. All rights and remedies regarding products and servic es which have received EMVCo approval shall be provided by the party providing such products or services, and not by EMVCo and EMVCo accepts no liabil ity whatsoever in connection therewith. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________ 15 © 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

0 6/08 Initial release — 1 8/08 Clarified the V DDA specification in the Recommended DC Operating Conditions table 2 2 2/12 Added the automotive TSSOP version to the Ordering Information and Selector Guide; updated the Absolute Maximum Ratings 1, 2, 14 3 7/12 Added footnote to the resistor value on the PRES pin in Figure 8 13