DS8005 MAXIM | Alldatasheet

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Technical content

Features

♦ Analog Interface and Level Shifting for IC Card Communication ♦ ±8kV (min) ESD (HBM) Protection on Card Interfaces ♦ Ultra-Low Stop-Mode Current, Less than 10nA Typical ♦ Internal IC Card Supply-Voltage Generation 5.0V ±5%, 80mA (max) 3.0V ±8%, 65mA (max) 1.8V ±10%, 30mA (max) ♦ Automatic Card Activation and Deactivation Controlled by Dedicated Internal Sequencer ♦ I/O Lines from Host Directly Level Shifted for Smart Card Communication ♦ Flexible Card Clock Generation, Supporting External Crystal Frequency Divided by 1, 2, 4, or 8 ♦ High-Current, Short-Circuit and High-Temperature Protection ♦ Low Active-Mode Current ♦ Internal Multiplexing Allows One ISO 7816 UART Implementation to Control Two Smart Card Sockets DS8005 Smart Card Interface

Ordering Information

19-5257; Rev 0; 4/10 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. PART TEMP RANGE PIN-PACKAGE DS8005-RRX+ -40 °C to +85°C 28 SO +Denotes a lead(Pb)-free/RoHS-compliant package. Typical Application Circuit appears at end of data sheet. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of a ny device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. EMV is a registered trademark of EMVCo LLC. Selector Guide PART CARD VOLTAGES SUPPORTED LOW STOP-MODE POWER LOW ACTIVE- MODE POWER PRES_ POLARITY V DDA INPUTS DS8005-RRX+ 1.8V, 3V, 5V Yes Yes Positive 2

RECOMMENDED DC OPERATING CONDITIONS (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted. All specifications apply to the device, unless otherwise noted in the CONDITIONS column.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on All Other Pins Maximum Power Dissipation Range (TA = -25°C to +85°C)..700mW PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Digital Supply Voltage V DD 2.7 6.0 V Card Voltage-Generator Supply Voltage V DDA Must be VDD 4.75 6.0 V VTH2 Threshold voltage (falling) 2.20 2.45 2.65 V Reset Voltage Thresholds VHYS2 Hysteresis 50 100 200 mV CURRENT CONSUMPTION Active V DD Current 5V Cards (Including 80mA Draw from 5V Card) IDD_50V ICC = 80mA, f XTAL = 20MHz, fCLK = 10MHz, V DDA = 5.0V 80.75 85 mA Active V DD Current 5V Cards (Current Consumed by Device Only) IDD_IC ICC = 80mA, fXTAL = 20MHz, fCLK = 10MHz, VDDA = 5.0V (Note 2) 0.75 5 mA Active V DD Current 3V Cards (Including 65mA Draw from 3V Card) IDD_30V ICC = 65mA, f XTAL = 20MHz, fCLK = 10MHz, V DDA = 5.0V 65.75 70 mA Active V DD Current 3V Cards (Current Consumed by Device Only) IDD_IC ICC = 65mA, fXTAL = 20MHz, fCLK = 10MHz, VDDA = 5.0V (Note 2) 0.75 5 mA Active V DD Current 1.8V Cards (Including 30mA Draw from 1.8V Card) IDD_18V ICC = 30mA, f XTAL = 20MHz, fCLK = 10MHz, V DDA = 5.0V 30.75 40 mA Active V DD Current 1.8V Cards (Current Consumed by Device Only) IDD_IC ICC = 30mA, fXTAL = 20MHz, fCLK = 10MHz, VDDA = 5.0V (Note 2) 0.75 5 mA Inactive-Mode Current I DD Card inactive, active-high PRES_, device not in stop mode 50 400 μA Stop-Mode Current I DD_STOP Device in ultra-low-power stop mode (CMDVCC, 5V/3V, and 1_8V set to logic 1) (Note 3) 0.01 2 μA

RECOMMENDED DC OPERATING CONDITIONS (continued) (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted. All specifications apply to the device, unless otherwise noted in the CONDITIONS column.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CLOCK SOURCE Crystal Frequency f XTAL External crystal (Note 1) 0 20 MHz fXTAL1 (Note 1) 0 20 MHz VIL_XTAL1 Low-level input on XTAL1 -0.3 0.3 x VDDXTAL1 Operating Conditions VIH_XTAL1 High-level input on XTAL1 0.7 x VDD VDD + 0.3 V External Capacitance for Crystal CXTAL1, CXTAL2 15 pF Internal Oscillator f INT 2.2 2.7 3.4 MHz SHUTDOWN TEMPERATURE Shutdown Temperature T SD +150 °C RSTA AND RSTB PINS Output Low Voltage V OL_RST1 I OL_RST = 1mA 0.3 V Card-Inactive Mode Output Current I OL_RST1 V OL_RST = 0V -1 mA Output Low Voltage V OL_RST2 I OL_RST = 200μA 0.3 V Output High Voltage VOH_RST2 I OH_RST = -200μA VCC - 0.5 V Rise Time t R_RST C L = 30pF (Note 1) 0.1 μs Fall Time t F_RST C L = 30pF (Note 1) 0.1 μs Current Limitation I RST(LIMIT) -20 +20 mA Card-Active Mode RSTIN to RST Delay t D(RSTIN-RST) 2 μs CLKA AND CLKB PINS Output Low Voltage V OL_CLK1 IOLCLK = 1mA 0.3 V Card-Inactive Mode Output Current I OL_CLK1 V OLCLK = 0V -1 mA Output Low Voltage V OL_CLK2 I OLCLK = 200μA 0.3 V Output High Voltage VOH_CLK2 IOHCLK = -200μA VCC - 0.5 V Rise Time t R_CLK C L = 30pF (Notes 1, 4) 8 ns Fall Time t F_CLK C L = 30pF (Notes 1, 4) 8 ns Current Limitation I CLK(LIMIT) -75 +75 mA Clock Frequency f CLK Operational 0 10 MHz Duty Factor C L = 30pF 45 55 % Card-Active Mode Slew Rate SR C L = 30pF (Note 1) 0.2 V/ns VCCA AND VCCB PINS Output Low Voltage V CC1 I CC = 1mA 0.3 V Card-Inactive Mode Output Current I CC1 V CC = 0V 0 -1 mA

RECOMMENDED DC OPERATING CONDITIONS (continued) (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted. All specifications apply to the device, unless otherwise noted in the CONDITIONS column.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Device: I CC(5V) < 30mA, VDDA = 4.75V (Note 1) 4.65 5 5.25 Device: I CC(5V) < 80mA 4.75 5 5.25 Device: I CC(3V) < 65mA 2.78 3 3.24 Device: I CC(1.8V) < 30mA 1.64 1.8 1.98 5V card; current pulses of 40nC with I < 200mA, t < 400ns, f < 20MHz 4.6 5.4 3V card; current pulses of 24nC with I < 200mA, t < 400ns, f < 20MHz 2.75 3.25 Output Low Voltage V CC2 1.8V card; current pulses of 12nC with I < 200mA, t < 400ns, f < 20MHz 1.62 1.98 V VCC(5V) = 0 to 5V -80 VCC(3V) = 0 to 3V -65 Output Current I CC2 VCC(1.8V) = 0 to 1.8V -30 mA Shutdown Current Threshold ICC(SD) (Note 1) 120 mA Card-Active Mode Slew Rate V CCSR Up/down; C < 300nF (Note 5) 0.05 0.16 0.22 V/μs DATA LINES (I/O_ AND I/OIN) I/O_ I/OIN Falling Edge Delay t D(IO-IOIN) (Note 1) 200 ns Pullup Pulse Active Time t PU (Note 1) 100 ns Maximum Frequency f IOMAX 1 MHz Input Capacitance C I 10 pF I/OA AND I/OB PINS Output Low Voltage V OL_IO1 I OL_IO = 1mA 0.3 V Output Current I OL_IO1 V OL_IO = 0V 0 -1 mA Card-Inactive Mode Internal Pullup Resistor RPU_IO To V CC 6 11 19 k Output Low Voltage V OL_IO2 IOL_IO = 1mA 0.3 V IOH_IO = < -20μA 0.8 x V CC Output High Voltage VOH_IO2 IOH_IO = < -40μA (3V/5V) 0.75 x V CC V Output Rise/Fall Time tOT C L = 30pF (Note 1) 0.1 μs Input Low Voltage V IL_IO -0.3 +0.8 Card-Active Mode Input High Voltage V IH_IO 1.5 V CC V

RECOMMENDED DC OPERATING CONDITIONS (continued) (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted. All specifications apply to the device, unless otherwise noted in the CONDITIONS column.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Low Current I IL_IO VIL_IO = 0V 700 μA Input High Current I IH_IO V IH_IO = VCC -20 +20 μA Input Rise/Fall Time t IT 1.2 μs Card-Active Mode Current Limitation I IO(LIMIT) C L = 30pF -15 +15 mA I/OIN PIN Output Low Voltage V OL I OL = 1mA 0.3 V Output High Voltage V OH I OH < -40μA 0.75 x VDD VDD + 0.1 V Output Rise/Fall Time t OT C L = 30pF, 10% to 90% 0.1 μs Input Low Voltage V IL -0.3 +0.3 x VDD V Input High Voltage V IH 0.7 x VDD VDD + 0.3 V Input Low Current I IL_IO V IL = 0V 700 μA Input High Current I IH_IO V IH = VDD -10 +10 μA Input Rise/Fall Time t IT V IL to VIH 1.2 μs Integrated Pullup Resistor R PU Pullup to V DD 6 11 19 k CONTROL PINS (CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/ 3V, 1_8V) Input Low Voltage V IL -0.3 +0.3 x VDD V Input High Voltage V IH 0.7 x VDD VDD + 0.3 V Input Low Current I IL_IO 0 < V IL < VDD -5 +5 μA Input High Current I IH_IO 0 < V IH < VDD -5 +5 μA INTERRUPT OUTPUT PINS (OFF AND OFF2) Output Low Voltage V OL I OL = 2mA 0.3 V Output High Voltage V OH I OH = -15μA 0.75 x VDD V Integrated Pullup Resistor R PU Pullup to V DD 12 24 38 k PRESA AND PRESB PINS Input Low Voltage V IL_PRES 0.3 x VDD V Input High Voltage V IH_PRES 0.7 x VDD V Input Low Current I IL_PRES VIL_PRES = 0V -5 +5 μA Input High Current I IH_PRES VIH_PRES = VDD 10 μA

RECOMMENDED DC OPERATING CONDITIONS (continued) (VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted. All specifications apply to the device, unless otherwise noted in the CONDITIONS column.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING Activation Time t ACT 50 160 220 μs Deactivation Time t DEACT 50 80 100 μs Window Start t 3 50 95 130 CLK_ to Card Start Time Window End t 5 140 160 220 μs PRES Debounce Time t DEBOUNCE 5 8 11 ms Note 1: Operation guaranteed at -40°C and +85°C but not tested. Note 2: IDD_IC measures the amount of current used by the device to provide the smart card current minus the load. Note 3: Stop mode is enabled by setting CMDVCC, 5V/3V, and 1_8V to a logic-high. Note 4: Parameters are guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the maximum rise and fall time is 10ns. Note 5: Parameter is guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the minimum slew rate is 0.05V/µs and the maximum slew rate is 0.5V/µs.

1, 2 CLKDIV1, CLKDIV2 Clock Divider. Determines the divided-down input clock frequency (presented at XTAL1 or from a crystal at XTAL1 and XTAL2) on the CLK_ output pin. Dividers of 1, 2, 4, and 8 are available. 3 5V/ 3V 5V/3V Selection Pin. Allows selection of 5V or 3V for communication with an IC card. Logic-high selects 5V operation; logic-low selects 3V operation. The 1_8V pin overrides the setting on this pin if active. See Table 3 for a complete description of choosing card voltages. 4 1_8V 1.8V Operation Selection. This active-high input puts the device into 1.8V smart card communication mode. The selected interface (when activated) powers a card with a 1.8V supply and all I/O lines operate at 1.8V.

5 V CCB

Smart Card Supply Voltage, Interface B. Decouple to CGND (card ground) with 2 x 100nF or 100 + 200nF capacitors (ESR < 100m ). 6 V DDA Smart Card Interface Supply. 5V power supply for powering the card interface. 7 RSTB Smart Card Reset, Interface B. Card reset output from contact C2. 8 CLKB Smart Card Clock, Interface B. Card clock, contact C3. 9, 14 CGND Smart Card Ground

10 PRESA

Interface A Card Presence Indicator. Active-high card presence input for the first card interface. When the presence indicator becomes active, a debounce tim eout begins. After 8ms (typ), the OFF signal becomes active if the first card interface is selected (SEL_AB low), else the OFF2 signal becomes active.

11 I/OA

Smart Card Data-Line Output, Interface A. Card data communication line, contact C7. This pin is only active if the first card interface is selected (SEL_AB low) and the interface has gone through an activation sequence. 1_8V SEL_AB OFF2 I/OIN XTAL2 TOP VIEW XTAL1 OFF GND

21 V DD

20 RSTIN

19 CMDVCC

18 V DDA2

17 V CCA

16 RSTA

15 CLKA

V CCB SO DS8005 Pin Configuration

Pin Description (continued) PIN NAME FUNCTION

12 I/OB

Smart Card Data-Line Output, Interface B. Card data communication line, contact C7. This pin is only active if the second card interface is selected (SEL_AB high) and the interface has gone through an activation sequence.

13 PRESB

Interface B Card Presence Indicator. Active-high card presence input for the second card interface. When the presence indicator becomes active, a debounce tim eout begins. After 8ms (typ), the OFF signal becomes active if the second card interface is selected (SEL_AB high), else the OFF2 signal becomes active. 15 CLKA Smart Card Clock, Interface A. Card clock, contact C3. 16 RSTA Smart Card Reset, Interface A. Card reset output from contact C2. Smart Card Supply Voltage, Interface A. Decouple to CGND (card ground) with 2 x 100nF or 100 + 220nF capacitors (ESR < 100m ). Smart Card Interface Supply. 5V power supply for powering the card interface. While this pin is not required to be connected to 5V (it can be left not connected (N.C.)), it is recommended for the best performance when delivering power to a 5V smart card. 19 CMDVCC Activation Sequence Initiate. Active-low input from host. 20 RSTIN Card Reset Input. Reset input from the host.

21 V DD Supply Voltage

22 GND Digital Ground

23 OFF

Status Output for Selected Interface. Active-low interrupt output to the host. Includes a 20k integrated pullup resistor to V DD. This pin reflects fault events and PRES_ events on the currently selected interface only (behaving as if it were a DS8024 with only one interface). The OFF2 pin should be used to monitor presence events on the nonselected interface. 24, 25 XTAL1, XTAL2 Crystal/Clock Input. Connect an input from an external clock to XTAL1 or connect a crystal across XTAL1 and XTAL2. 26 I/OIN I/O Input. Host-to-interface chip data I/O line.

27 OFF2

Status Output for Nonselected Interface. This pin passes through the presence signal for the nonselected interface. If SEL_AB is low (the A interface is selected), this pin reflects the state of the PRESB input. If SEL_AB is high (the B interface is selected), this pin reflects the state of the PRESA input.

28 SEL_AB

Interface Selection. This pin selects the interface the input pins (I/OIN, RSTIN, etc.) communicate with and control. If SEL_AB is low, the A interface is selected. Activation sequences power up V CCA and communication occurs with CLKA, I/OA, and RSTA. If SEL_AB is high, the B interface is selected. Both interfaces can be powered and clocking at the same time. See the Switching A/B Interfaces section for more information.

Figure 1. Functional Diagram ply for generating correct smart card supply voltages. ply voltage for 5V smart cards.

deactivation sequence if the card interface is active. at up to 20MHz connected between XTAL1 and XTAL2. XTAL, f XTAL/2, f XTAL/4, or f XTAL/8. signal given the inputs to CLKDIV1 and CLKDIV2. of CLK_ is eight periods of XTAL1. about the instant of change have the correct width. sition times less than 5% of the period. (I/O_ to V CC_ and I/OIN to V DD) in the inactive state. ting the logic 0 present on the master side. Figure 2. Voltage Supervisor Behavior Table 1. Clock Frequency Selection

for the host to initiate a smart card session.

  • All card contacts are inactive (approximately 200 Ω to GND).
  • The I/OIN pin in the high-impedance state (11k Ω pullup resistor to V DD).
  • Voltage generators are stopped.
  • XTAL oscillator is running (if included in the device).
  • Voltage supervisor is active.
  • The internal oscillator is running at its low frequency. Activation Sequence After power-on and the reset delay, the host microcon- troller can monitor card presence with signals OFF and CMDVCC, as shown in Table 2. If the card is in the reader (if PRES_ is active), the host microcontroller can begin an activation sequence (start a card session) by pulling CMDVCC low. The following events form an activation sequence (Figure 3): 1) CMDVCC is pulled low. 2) The internal oscillator changes to high frequency (t 0). 3) The voltage generator is started (between t0 and t1). ATR CMDVCC RST_ RSTIN CLK_ VCC_ I/O_ I/OIN t0 t1 t2 t3 t4 t5 = tACT

Figure 3. Activation Sequence Using RSTIN and CMDVCC Table 2. Card Presence Indication Low High High Card A present. Low Low High Card A not present. High High High Card B present. High Low High Card B not present. Low High High Card B present. Low Low High Card B not present. High High High Card A present. High Low High Card A not present.

4) V CC_ rises from 0 to 5V, 3V, or 1.8V with a controlled slope (t 2 = t 1 + 1.5 × T). T is 64 times the internal oscillator period (approximately 25µs). 5) I/O_ pin is enabled (t 3 = t1 + 4T) (they were previ- ously pulled low). 6) The CLK_ signal is applied to the C3 contact (t 4). 7) RST_ is enabled (t 5 = t1 + 7T). To apply the clock to the card interface: 1) Set RSTIN high. 2) Set CMDVCC low. 3) Set RSTIN low between t 3 and t5; CLK_ now starts. 4) RST_ stays low until t 5, then RST becomes the copy of RSTIN. 5) RSTIN has no further effect on CLK_ after t 5. If the applied clock is not needed, set CMDVCC low with RSTIN low. In this case, CLK_ starts at t3 (minimum 200ns after the transition on I/O; see Figure 4); after t 5, RSTIN can be set high to obtain an answer to request (ATR) from an inserted smart card. Do not perform acti- vation with RSTIN held permanently high. Active Mode When the activation sequence is completed, the card interface is in active mode. The host microcontroller and the smart card exchange data on the I/O lines. Deactivation Sequence When a session is completed, the host microcontroller sets the CMDVCC line high to execute an automatic deactivation sequence and returns the card interface to the inactive mode (Figure 5). 1) RST_ goes low (t 10). 2) CLK_ is held low (t 12 = t10 + 0.5 × T) where T is 64 times the period of the internal oscillator (approxi- mately 25µs). 3) I/O_ pin is pulled low (t 13 = t10 + T). 4) V CC starts to fall (t14 = t10 + 1.5 × T). 5) When V CC_ reaches its inactive state, the deactiva- tion sequence is complete (at tDE). 6) All card contacts become low impedance to GND; I/OIN remains at V DD (pulled up through an 11k Ω resistor). 7) The internal oscillator returns to its lower frequency. VCC Generator Each V CC_ generator has a capacity to supply up to 80mA continuously at 5V, 65mA at 3V, and 30mA at 1.8V. An internal overload detector triggers at approxi- mately 120mA. Current samples to the detector are fil- tered. This allows spurious current pulses (with a duration of a few µs) up to 200mA to be drawn without causing deactivation. The average current must stay below the specified maximum current value. To main- tain V CC voltage accuracy, a 100nF capacitor (with an ESR < 100m Ω) should be connected to CGND and placed near the V CC_ pin, and a 100nF or 220nF capacitor (220nF is the best choice) with the same ESR should be connected to CGND and placed near the smart card reader’s C1 contact. Fault Detection The following fault conditions are monitored:

  • Short-circuit or high current on VCC_
  • Removal of a card during a transaction DD dropping
  • Card voltage generator operating out of the specified values (V DDA too low or current consumption too high)
  • Overheating There are two different cases (Figure 6):
  • CMDVCC High Outside a Card Session. Output OFF_ is low if a card is not in the card reader and high if a card is in the reader. The V DD supply is mon- itored—a decrease in input voltage generates an internal power-on reset pulse but does not affect the OFF_ signal. Short-circuit and temperature detection is disabled because the card is not powered up.
  • CMDVCC Low Within a Card Session. Output OFF_ goes low when a fault condition is detected, and an emergency deactivation is performed automatically (Figure 7). When the system controller resets CMD- VCC to high, it may sense the OFF_ level again after completing the deactivation sequence. This distin- guishes between a card extraction and a hardware problem (OFF_ goes high again if a card is present). Depending on the connector’s card-present switch (normally closed or normally open) and the mechani- cal characteristics of the switch, bouncing can occur on the PRES_ signals at card insertion or withdrawal. The device has a debounce feature with an 8ms typical duration (Figure 6). When a card is inserted, output OFF_ goes high after the debounce time delay. When the card is extracted, an automatic deactivation sequence of the card is performed on the first true/false transition on PRES_ and output OFF_ goes low. Smart Card Interface

before the device enters low-power stop mode. Figure 8. Stop-Mode Sequence

Figure 9. Smart Card Power Select Table 3. VCC Select and Operation Mode

to leave both interfaces powered at the same time. Figure 10. Switching A/B Interfaces

Performance can be affected by the layout of the appli- cation. For example, an additional cross-capacitance of 1pF between card reader contacts C2 (RST_) and C3 (CLK_) or C2 (RST_) and C7 (I/O_) can cause contact C2 to be polluted with high-frequency noise from C3 (or C7). In this case, include a 100pF capacitor between contacts C2 and CGND. Application recommendations include the following:

  • Ensure there is ample ground area around the device and the connector; place the device very near to the connector; decouple the V DD and V DDA lines sepa- rately. These lines are best positioned under the con- nector.
  • The device and the host microcontroller must use the same V DD supply. Pins CLKDIV1, CLKDIV2, RSTIN, PRES_, I/OIN, 5V/ 3V, 1_8V, CMDVCC, and OFF are referenced to VDD; if pin XTAL1 is to be driven by an external clock, also reference this pin to VDD.
  • Trace C3 (CLK) should be placed as far as possible from the other traces.
  • The trace connecting CGND to C5 (GND) should be straight (the two capacitors on C1 (V CC_) should be connected to this ground trace).
  • Avoid ground loops between CGND and GND.
  • Decouple V DDA and V DD separately. If two supplies are the same in the application, they should be con- nected in a star on the main trace With all these layout precautions, noise should be kept to an acceptable level and jitter on C3 (CLK_) should be less than 100ps. Reference layouts are available on request. Technical Support For technical support, go to https://support.maxim- ic.com/micro.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

28 SO W28+1 21-0042

+3.3V +3.3V +3.3V 100kΩ 100kΩ 33pF 100nF* 220nF* *PLACE A 100nF CAPACITOR CLOSE TO THE DS8005 AND PLACE A 220nF CAPACITOR CLOSE TO CARD CONTACT. 33pF CLKDIV1 PRESA PRESB CLKDIV2 5V/3V 1_8V RSTIN CMDVCC I/OIN OFF2 PRES GPIO ... ... GPIO ISO_DATA OFF SEL_AB GPIO GPIO GPIO VCCA RSTA INTERFACE A CLKA I/OA RSTB CLKB I/OB CGND XTAL1 XTAL2 GND VDD 10μF VDDA2 VDDA 100nF 100nF* 220nF* VDD PRESB VCCB INTERFACE B Typical Application Circuit

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to th e package regardless of RoHS status.

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

0 4/10 Initial release —