DS78LS120 NSC | Alldatasheet

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n Meets EIA standards RS232-C, RS422 and RS423, Federal Standards 1020, 1030 and MIL-188-114 n Input voltage range of ±15V (differential or common-mode) n Separate strobe input for each receiver n 5k typical input impedance n Optional 180Ω termination resistor n 50mV input hysteresis n 200mV input threshold n Separate fail-safe mode Connection Diagram Dual-In-Line-Package 00749901 Top View see RETS Data Sheet. Order Number DS78LS120J/883 or DS78LS120W/883 See NS Package Number J16A or W16A September 1999 DS78LS120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe) © 2004 National Semiconductor Corporation DS007499 www.national.com

Absolute Maximum Ratings(Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage 7V Input Voltage ±25V Strobe Voltage 7V Output Sink Current 50 mA Storage Temperature Range −65˚C to +150˚C Maximum Power Dissipation at 25˚C (Note 1) 1433 mV Lead Temperature (Soldering, 4 sec) 260˚C Operating Conditions Min Max Units Supply Voltage (VCC) 4.5 5.5 V Temperature (TA) −55 +125 ˚C Common-Mode Voltage (VCM) −15 +15 V Electrical Characteristics(Notes 3, 4) Symbol Parameter Conditions Min Typ Max Units VTH Differential Threshold Voltage I OUT = −400 µA, V OUT ≥ 2.5V −7V ≤ VCM ≤ 7V 0.06 0.2 V −15 ≤ VCM ≤15V 0.06 0.3 V VTL Differential Threshold Voltage I OUT = 4 mA, V OUT ≤ 0.5V −7V ≤ VCM ≤7V −0.08 −0.2 V −15V ≤ VCM ≤ 15V −0.08 −0.3 V VTH Differential Threshold Voltage I OUT = −400 µA, V OUT ≥ 2.5V −7V ≤ VCM ≤ 7V 0.47 0.7 V VTL with Fail-Safe Offset = 5V I OUT = 4 mA, V OUT ≤ 0.5V −7V ≤ VCM ≤ 7V −0.2 −0.42 V RIN Input Resistance −15V ≤ VCM ≤ 15V, 0V ≤ VCC ≤ 7V 4 5 k Ω RT Line Termination Resistance T A = 25˚C 100 180 300 Ω RO Offset Control Resistance T A = 25˚C 42 56 70 k Ω IIND Data Input Current (Unterminated) V CM = 10V 2 3.1 mA VCM =0 V 0 V ≤ VCC ≤ 7V 0 −0.5 mA VCM = −10V −2 −3.1 mA VTHB Input Balance I OUT = −400 µA, V OUT ≥ 2.5V, −7V ≤ VCM 7V 0.1 0.4 V (Note 6) R S = 500Ω IOUT = 4 mA, V OUT ≤ 0.5V, −7V ≤ VCM ≤ 7V −0.1 −0.4 V RS = 500Ω VOH Logical “1” Output Voltage I OUT = −400 µA, V DIFF = 1V, VCC = 4.5V 2.5 3 V VOL Logical “0” Output Voltage I OUT = 4 mA, V DIFF = −1V, V CC = 4.5V 0.35 0.5 V ICC Power Supply Current V CC = 5.5V V CM = 15V 10 16 mA VDIFF = −0.5V, (Both Receivers) V CM = −15V 10 16 mA IIN (1) Logical “1” Strobe Input Current V STROBE = 5.5V, VDIFF = 3V 1 100 µA IIN (0) Logical “0” Strobe Input Current V STROBE = 0V, VDIFF = −3V −290 −400 µA VIH Logical “1” Strobe Input Voltage V OL ≤ 0.5, IOUT = 4mA 2.0 1.12 V VIL Logical “0” Strobe Input Voltage V OH ≥ 2.5V, IOUT, = −400 µA 1.12 0.8 V IOS Output Short-Circuit Current V OUT = 0V, VCC = 5.5V, VSTROBE = 0V,(Note 5) −30 −100 −170 mA Note 1: Derate cavity package 9.6 mW/˚C above 25˚C. Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for act ual device operation. Note 3: Unless otherwise specified min/max limits apply across the −55˚C to +125˚C temperature range for the DS78LS120. All typical values are for T A = 25˚C, VCC = 5V and V CM =0 V . Note 4: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values s hown as max or min on absolute value basis. Note 5: Only one output at a time should be shorted. Note 6: Refer to EIA-RS422 for exact conditions. DS78LS120 www.national.com 2

VCC = 5V, TA = 25˚C Symbol Parameter Conditions Min Typ Max Units tpd0(D) Differential Input to “0” Output 38 60 ns tpd1(D) Differential Input to “1” Output Response Pin Open, C L = 15 pF, R L =2k Ω 38 60 ns tpd0(S) Strobe Input to “0” Output 16 25 ns tpd1(S) Strobe Input to “1” Output 12 25 ns AC Test Circuit and Switching Time Waveforms Differential and Strobe Input Signal 00749903 Includes probe and test fixture capacitance 00749904 Note: Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection). Application Hints Balanced Data Transmission 00749905 DS78LS120 www.national.com3

the input signal, and the other input to the driving gate. FIGURE 1. Noise Pulse Width vs

Application Hints (Continued) TRANSMISSION LINE TERMINATION On a transmission line which is electrically long, it is advis- able to terminate the line in its characteristic impedance to prevent signal reflection and its associated noise/cross-talk. A 180Ω termination resistor is provided in the DS78LS120 line receiver. To use the termination resistor, connect pins 2 and 3 together and pins 13 and 14 together. The 180 Ω resistor provides a good compromise between line reflec- tions, power dissipation in the driver, and IR drop in the transmission line. If power dissipation and IR drop are still a concern, a capacitor may be connected in series with the resistor to minimize power loss. The value of the capacitor is recommended to be the line length (time) divided by 3 times the resistor value. Example: if the transmission line is 1,000 feet long, (approximately 1000 ns), and the termination resistor value is 180 Ω, the capacitor value should be 1852 pF. For additional application details, refer to application notes AN-22 and AN-108. FAIL-SAFE OPERATION Communication systems require elements of a system to detect the presence of signals in the transmission lines, and it is desirable to have the system shut-down in a fail-safe mode if the transmission line is open or shorted. To facilitate the detection of input opens or shorts, the DS78LS120 in- corporates an input threshold voltage offset. This feature will force the line receiver to a specific logic state if presence of either fault is a condition. Given that the receiver input threshold is ±200 mV, an input signal greater than ±200 mV insures the receiver will be in a specific logic state. When the offset control input (pins 1 and 15) is connected to V CC = 5V, the input thresholds are offset from 200 mV to 700 mV, referred to the non-inverting input, or −200 mV to −700 mV, referred to the inverting input. Therefore, if the input is open or shorted, the input will be greater than the input threshold and the receiver will remain in a specified logic state. The input circuit of the receiver consists of a 5k resistor terminated to ground through 120 Ω on both inputs. This network acts as an attenuator, and permits operation with common-mode input voltages greater than ±15V. The offset control input is actually another input to the attenuator, but its resistor value is 56k. The offset control input is connected to the inverting input side of the attenuator, and the input voltage to the amplifier is the sum of the inverting input plus 0.09 times the voltage on the offset control input. When the offset control input is connected to 5V the input amplifier will see V IN(INVERTING) +0.45V or VIN(INVERTING) +0.9V when the control input is connected to 10V. The offset control input will not significantly affect the differential performance of the receiver over its common-mode operating range, and will not change the input impedance balance of the receiver. It is recommended that the receiver be terminated (500 Ω or less) to insure it will detect an open circuit in the presence of noise. The offset control can be used to insure fail-safe operation for unbalanced interface (RS-423) or for balanced interface (RS-422) operation. For unbalanced operation, the receiver would be in an inde- terminate logic state if the offset control input was open. Connecting the fail-safe offset pin to 5V, offsets the receiver threshold to 0.45V. The output is forced to a logic zero state if the input is open or shorted. Unbalanced RS-423 and RS-232 Fail-Safe 00749911 00749910 FIGURE 2. DS78LS120 www.national.com5

Application Hints (Continued) 00749912 Balanced RS-422 Fail-Safe 00749913 00749914 For balanced operation with inputs open or shorted, receiver C will be in an indeterminate logic state. Receivers A and B will be in a logic zero state allowing the NOR gate to detect the open or short condition. The strobe will disable receivers A and B and may therefore be used to sample the fail-safe detector. Another method of fail-safe detection consists of filtering the output of NOR gate D so it would not indicate a fault condition when receiver inputs pass through the thresh- old region, generating an output transient. In a communications system, only the control signals are required to detect input fault conditions. Advantages of a balanced data transmission system over an unbalanced transmission system are: 1. High noise immunity 2. High data ratio 3. Long line lengths DS78LS120 www.national.com 6

(For Balanced Fail-Safe) Input Strobe A-Out B-Out C-Out D-Out 0 1 0100 1 1 1010 X10 0 X 1 0 0 1100 1 0 1100 X 0 1100 Schematic Diagram 00749902 DS78LS120 www.national.com7

Physical Dimensions inches (millimeters) unless otherwise noted Ceramic Dual-In-Line Package (J) Order Number DS78LS120J/883 Ceramic Dual-In-Line Package (W) Order Number DS78LS120W/883 DS78LS120 www.national.com 8

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com DS78LS120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe)