DS78LS120QML TI | Alldatasheet
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DS78LS120QML,DS78LS120 www.ti.com SNLS370C –SEPTEMBER 1999–REVISED APRIL 2013 DS78LS120/DS78LS120QMLDualDifferentialLineReceiver(NoiseFilteringandFail-Safe) Check forSamples: DS78LS120QML ,DS78LS120 1FEATURES DESCRIPTION The DS78LS120QML is a high performance,dual 2• Meets EIA Standards RS232-C, RS422 and differential,TTL compatiblelinereceiverfor bothRS423, FederalStandards 1020,1030 and MIL- balanced and unbalanced digitaldata transmission.188-114 The inputsarecompatiblewithEIA,Federaland MIL
- InputVoltageRange of±15V (Differentialor standards. Common-mode) The linereceiverwilldiscriminatea ±200 mV input• SeparateStrobeInputforEach Receiver signalover a common-mode range of ±10V and a
- 5k TypicalInputImpedance ±300 mV signalovera rangeof±15V.
- Optional180Ω TerminationResistor Circuitfeaturesincludehysteresisand response
- 50mV InputHysteresis controlforapplicationswhere controlledriseand fall times and/or high frequency noise rejectionare• 200mV InputThreshold desirable.Thresholdoffsetcontrolisprovidedforfail-• SeparateFail-safeMode safe detection,should the inputbe open or short. Each receiverincludesan optional180Ω terminating resistorand the outputgate containsa logicstrobe for time discrimination.The DS78LS120QML is specifiedovera −55°C to+125°C temperaturerange. Inputspecificationsmeet or exceed those of the popularDS7820 linereceiver. Connection Diagram Figure1. CDIP /CLGA See RETS Data Sheet See Package Number NFE0016A or NAD0016A Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Alltrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 1999–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
DS78LS120QML,DS78LS120 SNLS370C –SEPTEMBER 1999–REVISED APRIL 2013 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates. AbsoluteMaximum Ratings(1)(2) SupplyVoltage 7V InputVoltage ±25V StrobeVoltage 7V OutputSinkCurrent 50 mA StorageTemperatureRange −65°C to+150°C Maximum Power Dissipationat25°C (3) 1433 mV Lead Temperature(Soldering,4 sec) 260°C (1) “AbsoluteMaximum Ratings”arethosevaluesbeyond whichthesafetyofthedevicecannotbe ensured.Exceptfor“Operating TemperatureRange ”theyarenotmeant toimplythatthedevicesshouldbe operatedattheselimits.The tableof“Electrical Characteristics”providesconditionsforactualdeviceoperation. (2) IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheTISalesOffice/Distributorsforavailabilityand specifications. (3) DerateCDIP package 9.6mW/ °C above 25°C. OperatingConditions Min Max Units SupplyVoltage(VCC ) 4.5 5.5 V Temperature(TA) −55 +125 °C Common-Mode Voltage(VCM ) −15 +15 V ElectricalCharacteristics(1)(2) Symbol Parameter Conditions Min Typ Max Units VTH −7V ≤ VCM ≤ 7V 0.06 0.2 V DifferentialThresholdVoltage IOUT = −400 μA,VOUT ≥ 2.5V −15 ≤ VCM ≤15V 0.06 0.3 V VTL −7V ≤ VCM ≤7V −0.08 −0.2 V DifferentialThresholdVoltage IOUT = 4 mA, VOUT ≤ 0.5V −15V ≤ VCM ≤ 15V −0.08 −0.3 V VTH DifferentialThresholdVoltage IOUT = −400 μA,VOUT ≥ 2.5V −7V ≤ VCM ≤ 7V 0.47 0.7 V VTL withFail-SafeOffset= 5V IOUT = 4 mA, VOUT ≤ 0.5V −7V ≤ VCM ≤ 7V −0.2 −0.42 V R IN InputResistance −15V ≤ VCM ≤ 15V,0V ≤ VCC ≤ 7V 4 5 kΩ R T LineTerminationResistance TA = 25°C 100 180 300 Ω R O OffsetControlResistance TA = 25°C 42 56 70 kΩ IIND VCM = 10V 2 3.1 mA Data InputCurrent(Unterminated) VCM = 0V 0V ≤ VCC ≤ 7V 0 −0.5 mA VCM = −10V −2 −3.1 mA VTHB IOUT = −400 μA,VOUT ≥ 2.5V, −7V ≤ VCM 7V 0.1 0.4 V R S = 500Ω InputBalance(3) IOUT = 4 mA, VOUT ≤ 0.5V, R S = 500Ω VOH Logical“1”OutputVoltage IOUT = −400 μA,VDIFF = 1V,VCC = 4.5V 2.5 3 V VOL Logical“0”OutputVoltage IOUT = 4 mA, VDIFF = −1V,VCC = 4.5V 0.35 0.5 V ICC VCC = 5.5V VCM = 15V 10 16 mA Power SupplyCurrent VDIFF = −0.5V,(BothReceivers) VCM = −15V 10 16 mA (1) Unlessotherwisespecifiedmin/max limitsapplyacrossthe−55°C to+125°C temperaturerangefortheDS78LS120QML. Alltypical valuesareforTA = 25°C, VCC = 5V and VCM = 0V. (2) Allcurrentsintodevicepinsshown as positive,outofdevicepinsas negative,allvoltagesreferencedtogroundunlessotherwisenoted. Allvaluesshown as max ormin on absolutevaluebasis. (3) RefertoEIA-RS422 forexactconditions.
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DS78LS120QML,DS78LS120 www.ti.com SNLS370C –SEPTEMBER 1999–REVISED APRIL 2013 ElectricalCharacteristics(1)(2)(continued) Symbol Parameter Conditions Min Typ Max Units IIN (1) Logical“1”StrobeInputCurrent VSTROBE = 5.5V,VDIFF = 3V 1 100 μA IIN (0) Logical“0”StrobeInputCurrent VSTROBE = 0V,VDIFF = −3V −290 −400 μA VIH Logical“1”StrobeInputVoltage VOL ≤ 0.5,IOUT = 4mA 2.0 1.12 V VIL Logical“0”StrobeInputVoltage VOH ≥ 2.5V,IOUT ,= −400 μA 1.12 0.8 V IOS OutputShort-CircuitCurrent VOUT = 0V,VCC = 5.5V,VSTROBE = 0V (4) −30 −100 −170 mA (4) Onlyone outputata timeshouldbe shorted. SwitchingCharacteristics VCC = 5V,TA = 25°C Symbol Parameter Conditions Min Typ Max Units tpd0(D) DifferentialInputto“0”Output 38 60 ns tpd1(D) DifferentialInputto“1”Output 38 60 ns Response PinOpen, C L = 15 pF,R L = 2 kΩ tpd0(S) StrobeInputto“0”Output 16 25 ns tpd1(S) StrobeInputto“1”Output 12 25 ns AC TestCircuitand SwitchingTime Waveforms Includesprobeand testfixturecapacitance Figure2. Differentialand StrobeInputSignal Note:Optimum switchingresponseisobtainedby minimizingstraycapacitanceon Response Controlpin(noexternal connection). Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:DS78LS120QML DS78LS120
DS78LS120QML,DS78LS120 SNLS370C –SEPTEMBER 1999–REVISED APRIL 2013 www.ti.com APPLICATION HINTS Figure3. Balanced Data Transmission Figure4. Unbalanced Data Transmission Figure5. Logic LevelTranslator The DS78LS120QML may be used as a leveltranslatortointerfacebetween ±12V MOS, ECL, TTL and CMOS. To configure,biaseitherinputtoa voltageequalto½ thevoltageoftheinputsignal,and theotherinputtothe drivinggate.
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DS78LS120QML,DS78LS120 www.ti.com SNLS370C –SEPTEMBER 1999–REVISED APRIL 2013 LINE DRIVERS LinedriverswhichwillinterfacewiththeDS78LS120QML arelistedbelow. Balanced Drivers DS26LS31: Quad RS-422 LineDriver,DualCMOS DS7830, DS8830: DualTTL DS7831, DS8831: DualTRI-STATE TTL DS7832, DS8832: DualTRI-STATE TTL DS1691A, DS3691: Quad RS-423/DualRS-422 TTL DS1692, DS3692: Quad RS-423/DualTRI-STATE RS-422 TTL DS3487: Quad TRI-STATE RS-422 Unbalanced Drivers DS1488: Quad RS-232 DS75150: DualRS-232 RESPONSE CONTROL AND HYSTERESIS Inunbalanced(RS-232/RS-423)applicationsitisrecommended thattherisetimeand falltimeofthelinedriver be controlledtoreducecross-talk.EliminationofswitchingnoiseisaccomplishedintheDS78LS120QML by the 50 mV ofhysteresisincorporatedintheoutputgate.Thiseliminatestheoscillationswhichmay appearina line receiverdue totheinputsignalslowlyvaryingaboutthethresholdlevelforextendedperiodsoftime. High frequencynoisewhich issuperimposedon theinputsignalwhich may exceed 50 mV can be reducedin amplitudeby filteringthedeviceinput.On theDS78LS120QML, a highimpedance responsecontrolpininthe inputamplifierisavailabletofiltertheinputsignalwithoutaffectingtheterminationimpedance ofthetransmission line.Noisepulsewidthrejectionvs thevalueoftheresponsecontrolcapacitorisshown inFigure6 and Figure7. Thiscombinationoffiltersfollowedby hysteresiswilloptimizeperformanceina worse case noiseenvironment. Figure6. Noise Pulse Width vs Response ControlCapacitor Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:DS78LS120QML DS78LS120
DS78LS120QML,DS78LS120 SNLS370C –SEPTEMBER 1999–REVISED APRIL 2013 www.ti.com Figure7. TRANSMISSION LINE TERMINATION On a transmissionlinewhich is electricallylong,itis advisableto terminatethe linein itscharacteristic impedance to preventsignalreflectionand itsassociatednoise/cross-talk.A 180Ω terminationresistoris providedintheDS78LS120QML linereceiver.To use theterminationresistor,connectpins2 and 3 togetherand pins 13 and 14 together.The 180Ω resistorprovidesa good compromise between linereflections,power dissipationinthedriver,and IR dropinthetransmissionline.Ifpower dissipationand IR droparestilla concern, a capacitormay be connectedinserieswiththeresistortominimizepower loss. The valueof the capacitorisrecommended to be the linelength(time)dividedby 3 timesthe resistorvalue. Example:ifthetransmissionlineis1,000feetlong,(approximately1000 ns),and theterminationresistorvalueis 180Ω,thecapacitorvalueshouldbe 1852 pF.For additionalapplicationdetails,refertoapplicationnotesAN-22 and AN-108. FAIL-SAFE OPERATION Communicationsystemsrequireelementsofa systemtodetectthepresenceofsignalsinthetransmissionlines, and itisdesirabletohave thesystem shut-downina fail-safemode ifthetransmissionlineisopen or shorted. To facilitatethedetectionofinputopens orshorts,theDS78LS120QML incorporatesan inputthresholdvoltage offset.Thisfeaturewillforcethelinereceivertoa specificlogicstateifpresenceofeitherfaultisa condition. Given thatthereceiverinputthresholdis±200 mV, an inputsignalgreaterthan±200 mV insuresthereceiverwill be ina specificlogicstate.When theoffsetcontrolinput(pins1 and 15) isconnectedtoVCC = 5V, theinput thresholdsare offsetfrom 200 mV to 700 mV, referredto the non-invertinginput,or −200 mV to −700 mV, referredtotheinvertinginput.Therefore,iftheinputisopen or shorted,theinputwillbe greaterthantheinput thresholdand thereceiverwillremainina specifiedlogicstate. The inputcircuitofthereceiverconsistsofa 5k resistorterminatedtogroundthrough120Ω on bothinputs.This networkactsas an attenuator,and permitsoperationwithcommon-mode inputvoltagesgreaterthan±15V. The offsetcontrolinputisactuallyanotherinputtotheattenuator,butitsresistorvalueis56k.The offsetcontrolinput isconnectedtotheinvertinginputsideoftheattenuator,and theinputvoltagetotheamplifieristhesum ofthe invertinginputplus0.09timesthevoltageon theoffsetcontrolinput.When theoffsetcontrolinputisconnected to5V theinputamplifierwillsee VIN(INVERTING) +0.45V orVIN(INVERTING) +0.9V when thecontrolinputisconnected to 10V. The offsetcontrolinputwillnot significantlyaffectthe differentialperformanceof the receiverover its common-mode operatingrange,and willnotchange theinputimpedance balanceofthereceiver. Itisrecommended thatthereceiverbe terminated(500Ω or less)toinsureitwilldetectan open circuitinthe presenceofnoise. The offsetcontrolcan be used to insurefail-safeoperationforunbalancedinterface(RS-423)or forbalanced interface(RS-422)operation.
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DS78LS120QML,DS78LS120 www.ti.com SNLS370C –SEPTEMBER 1999–REVISED APRIL 2013 For unbalancedoperation,the receiverwould be inan indeterminatelogicstateifthe offsetcontrolinputwas open.Connectingthefail-safeoffsetpinto5V, offsetsthereceiverthresholdto0.45V.The outputisforcedtoa logiczerostateiftheinputisopen orshorted. Figure8. Unbalanced RS-423 and RS-232 Fail-Safe Figure9. Balanced RS-422 Fail-Safe Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:DS78LS120QML DS78LS120
DS78LS120QML,DS78LS120 SNLS370C –SEPTEMBER 1999–REVISED APRIL 2013 www.ti.com For balancedoperationwithinputsopen orshorted,receiverC willbe inan indeterminatelogicstate.Receivers A and B willbe ina logiczerostateallowingtheNOR gatetodetecttheopen orshortcondition.The strobewill disablereceiversA and B and may thereforebe used tosample thefail-safedetector.Anothermethod offail- safedetectionconsistsof filteringthe outputof NOR gate D so itwould not indicatea faultconditionwhen receiverinputspass throughthethresholdregion,generatingan outputtransient. Ina communicationssystem,onlythecontrolsignalsarerequiredtodetectinputfaultconditions.Advantagesof a balanceddatatransmissionsystemoveran unbalancedtransmissionsystemare: 1. Highnoiseimmunity 2. Highdataratio 3. Long linelengths TruthTable (ForBalancedFail-Safe) Input Strobe A-Out B-Out C-Out D-Out 0 1 0 1 0 0 1 1 1 0 1 0 X 1 0 0 X 1 0 0 1 1 0 0 1 0 1 1 0 0 X 0 1 1 0 0 Schematic Diagram
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DS78LS120QML,DS78LS120 www.ti.com SNLS370C –SEPTEMBER 1999–REVISED APRIL 2013
REVISION HISTORY
Changes from RevisionB (April2013)toRevisionC Page Copyright© 1999–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:DS78LS120QML DS78LS120
www.ti.com 29-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DS78LS120J/883 Active Production CDIP (NFE) | 16 25 | TUBE No Call TI Level-1-NA-UNLIM -55 to 125 DS78LS120J/883 Q DS78LS120J/883.A Active Production CDIP (NFE) | 16 25 | TUBE No Call TI Level-1-NA-UNLIM -55 to 125 DS78LS120J/883 Q (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) DS78LS120J/883 NFE CDIP 16 25 506.98 15.24 13440 NA DS78LS120J/883.A NFE CDIP 16 25 506.98 15.24 13440 NA Pack Materials-Page 1
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