DS7800

DS7800 NSC | Alldatasheet

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Y 31 volt (max) output swing Y 1 mW power dissipation in normal state Y Standard 5V power supply Y Temperature range: DS7800 b55§Ct o a125§C DS8800 0 §Ct o a70§C Y Compatible with all MOS devices Schematic and Connection Diagrams TL/F/5827–1 Typical Applications 4-Channel Analog Switch TL/F/5827–3 *Analog signals within the range of a8V to b8V. Metal Can Package TL/F/5827–2 Top View Order Number DS7800H or DS8800H See NS Package Number H10C Bipolar to MOS Interfacing TL/F/5827–4 C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. V CC Supply Voltage 7.0V V2 Supply Voltage b30V V3 Supply Voltage 30V V3–V2 Voltage Differential 40V Input Voltage 5.5V Storage Temperature b65§Ct o a150§C Lead Temperature (Soldering, 4 seconds) 260 §C Maximum Power Dissipation * at 25 §C Metal Can (TO-5) Package 690 mW *Derate metal can package 4.6 mW/ §C above 25 §C. Operating Conditions Min Max Units Supply Voltage, V CC DS7800 4.5 5.5 V DS8800 4.75 5.25 V Temperature (T DS7800 b55 a125 §C DS8800 0 a70 §C Electrical Characteristics (Notes 2 and 3) Symbol Parameter Conditions Min Typ Max Units(Note 6) VIH Logical ‘‘1’’ Input Voltage V CC e Min 2.0 V VIL Logical ‘‘0’’ Input Voltage V CC e Min 0.8 V IIH Logical ‘‘1’’ Input Current V CC e Max V IN e 2.4V 5 mA VIN e 5.5V 1 mA IIL Logical ‘‘0’’ Input Current V CC e Max, V IN e 0.4V b0.2 b0.4 mA IOL Output Sink Current V CC e Min, V IN e 2V, DS7800 1.6 mA V3 Open DS8800 2.3 mA IOH Output Leakage Voltage V CC e Max, V IN e 0.8V (Notes 4 and 7) 10 mA RO Output Collector Resistor T A e 25§C 11.5 16.0 20.0 k X VOL Logical ‘‘0’’ Output Voltage V CC e Min, V IN e 2.0V (Note 7) V 2 a 2.0 V ICC(MAX) Power Supply Current V CC e Max, V IN e 4.5V (Note 5) 0.85 1.6 mAOutput ‘‘ON’’ Per Gate ICC(MIN) Power Supply Current V CC e Max, V IN e 0V (Note 5) 0.22 0.41 mAOutput ‘‘OFF’’ Per Gate Switching Characteristics TA e 25§C, nominal power supplies unless otherwise noted Symbol Parameter Conditions Min Typ Max Units tpd0 Transition Time to Logical T A e 25§C, C e 15 pF (Note 8) 25 70 125 ns‘‘0’’ Output tpd1 Transition Time to Logical T A e 25§C, C e 15 pF (Note 9) 25 62 125 ns‘‘1’’ Output Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Unless otherwise specified min/max limits apply across the b55§Ct o a125§C temperature range for the DS7800 and across the 0 §Ct o a70§C range for the DS8800. Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown as max or min on absolute value basis. Note 4: Current measured is drawn from V 3 supply. Note 5: Current measured is drawn from V CC supply. Note 6: All typical values are measured at T A e 25§C with V CC e 5.0V, V 2 eb 22V, V 3 ea 8V. Note 7: Specification applies for all allowable values of V 2 and V 3. Note 8: Measured from 1.5V on input to 50% level on output. Note 9: Measured from 1.5V on input to logic ‘‘0’’ voltage, plus 1V.

The two input diodes perform the AND function on TTL in- put voltage levels. When at least one input voltage is a logi- cal ‘‘0’’, current from V CC (nominally 5.0V) passes through R1 and out the input(s) which is at the low voltage. Other than small leakage currents, this current drawn from V CC through the 20 k X resistor is the only source of power dissi- pation in the logical ‘‘1’’ output state. When both inputs are at logical ‘‘1’’ levels, current passes through R 1 and diverts to transistor Q 1, turning it on and thus pulling current through R 2. Current is then supplied to the PNP transistor, Q 2. The voltage losses caused by cur- rent through Q 1,D 3, and Q 2 necessitate that node P reach a voltage sufficient to overcome these losses before current begins to flow. To achieve this voltage at node P, the inputs must be raised to a voltage level which is one diode poten- tial lower than node P. Since these levels are exactly the same as those experienced with conventional TTL, the in- terfacing with these types of circuits is achieved. Transistor Q 2 provides ‘‘constant current switching’’ to the output due to the common base connection of Q 2. When at least one input is at the logical ‘‘0’’ level, no current is deliv- ered to Q 2; so that its collector supplies essentially zero current to the output stage. But when both inputs are raised to a logical ‘‘1’’ level current is supplied to Q Selecting Power Supply Voltage The graph shows the boundary conditions which must be used for proper operation of the unit. The range of operation for power supply V 2 is shown on the X axis. It must be between b25V and b8V. The allowable range for power supply V 3 is governed by supply V 2. With a value chosen for V2,V 3 may be selected as any value along a vertical line passing through the V 2 value and terminated by the bounda- ries of the operating region. A voltage difference between power supplies of at least 5V should be maintained for ade- quate signal swing. Since this current is relatively constant, the collector of Q acts as a constant current source for the output stage. Logic inversion is performed since logical ‘‘1’’ input voltages cause current to be supplied to Q 2 and Q 3. And when Q 3 turns on the output voltage drops to the logical ‘‘0’’ level. The reason for the PNP current source, Q 2, is so that the output stage can be driven from a high impedance. This allows voltage V 2 to be adjusted in accordance with the application. Negative voltages to b25V can be applied to V2. Since the output will neither source nor sink large amounts of current, the output voltage range is almost ex- clusively dependent upon the values selected for V 2 and V 3. Maximum leakage current through the output transistor Q 3 is specified at 10 mA under worst-case voltage between V 2 and V 3. This will result in a logical ‘‘1’’ output voltage which is 0.2V below V 3. Likewise the clamping action of diodes D 4, D5, and D 6, prevents the logical ‘‘0’’ output voltage from falling lower than 2V above V 2, thus establishing the ouput voltage swing at typically 2 volts less than the voltage sepa- ration between V 2 and V 3. TL/F/5827–5 Switching Time Waveforms TL/F/5827–6

Physical Dimensions inches (millimeters) Metal Can Package (H) Order Number DS7800H or DS8800H LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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